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The article presents a theoretical and experimental assessment of noise levels during the analog-to-digital conversion of TV broadcast microwave signals. Mathematical expressions are derived to calculate the mean quantization noise power for different brightness distribution models on TV images, considering both linear and nonlinear characteristics of the "light-to-signal" converter. For the first time, the dependence of the average quantization noise power on the compression coefficient is obtained for an inversely proportional distribution of brightness on the television image. This is particularly relevant when the input unipolar positive TV broadcast luminance signal is small, i.e., when the signal level is below the first quantization level. Additionally, analytical expressions are provided to calculate the level of restriction noise and the ratio of restriction noise power to quantizing noise power, particularly when the brightness distribution on TV images follows an exponentially decreasing model or an inversely proportional model with a logarithmic quantization scale. The impact of quantization and restriction noise on image quality was experimentally tested in an Additive White Gaussian Noise (AWGN) channel. [ABSTRACT FROM AUTHOR]

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

Equivalent‐time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down‐conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in‐phase/quadrature gain imbalance instead of requiring a high‐speed analog‐to‐digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent‐time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent‐time sampling using DDC. [ABSTRACT FROM AUTHOR]

Copyright of Informatics Control Measurement in Economy & Environment Protection / Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska is the property of Lublin University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively. [ABSTRACT FROM AUTHOR]

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown. [ABSTRACT FROM AUTHOR]

The article explores the design and use of the analyzer developed by the authors for investigating the quality of compression, recording, transmission, and reproduction of speech signals in audio communication channels. The peculiarities of the construction of measurement channels of a self-adjusting system are studied. Parameters for assessing the quality of channels are selected, and methods for their calculation are determined. An example of determining the quality of compression-decompression in satellite channels for transmitting audio speech is provided. A polyharmonic signal, consisting of the sum of many harmonic components with the same amplitude and phase, is proposed as the input test signal for the compressor. Such a signal approximates real speech and music signals transmitted through the channel. The actual frequency characteristic is determined at the output of the decompressor by analyzing the spectrum, which, for the MPEG Layer3 compression method, significantly depends on the bit rate of compressed data transmission. Another characteristic application of the analyzer is experiments to study the structural organization of connecting possibilities of elements in complex nominations at the phonetic level in the concept of the "golden" ratio. A hypothesis is put forward about the harmony of these words at the acoustic level. It is proved that the harmonious structure of juxtapositions should be considered as the arrangement of components of such nominations by a system of perfect relationships, among which the proportion corresponding to the division of the whole into two parts and called the "golden" ratio plays a fundamental role.

This paper proposes a system for measuring unknown resistances for metal oxide MQ gas sensors. The circuit configuration is based on the Anderson current loop interface, which connects directly to an Arduino Mega 2560. We analyze errors arising from variations in supply voltage of conventional divider circuits, including those introduced by the Analog-to-Digital Conversion (ADC) of microcontroller. To enhance the accuracy of resistance measurements, a voting technique for selecting the optimal unknown resistances is introduced. In this technique, the digital voltage at each node is analyzed to determine the frequency of occurrence of each level. If a particular voltage level has a frequency of occurrence greater than the reference threshold k, it is selected. If no voltage level meets this criterion, the average of the observed voltage levels is used. From the experimental results, unknown resistances were measured in the range of 362 – 15, $397~\Omega $ with a maximum approximated error of 0.55% with $k =90$ %, while the gas content was measured with a maximum error of approximately 0.24% under conditions of power supply voltage fluctuation from 4.9 to 5.1 V.

This work presents a small-area 2nd-order continuous-time $\Delta \Sigma $ Modulator (CT $\Delta \Sigma \text{M}$ ) with a single low dropout regulator (LDO) serving as both the power supply for the CT $\Delta \Sigma \text{M}$ and reference voltage buffer. The CT $\Delta \Sigma \text{M}$ is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and $\text{V}_{ref}$ for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT $\Delta \Sigma \text{M}$ consumes $300 ~\mu \text{W}$ of power when clocked at 10.24 MHz. The CT $\Delta \Sigma \text{M}$ achieves a state-of-the-art area of 0.07 mm2.

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown.

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing. [ABSTRACT FROM AUTHOR]

The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s digitizer application-specific integrated circuit (ASIC) intended for use inside the DUNE Far Detector. ColdADC_P2 contains two 16 MS/s pipelined analog-to-digital converters (ADCs) that each digitizes the output of eight sample-and-hold amplifiers (SHAs). Because the application requires immersion in liquid argon (LAr), ColdADC_P2 was developed using specialized design techniques for long-term reliability in cryogenic environments and a customized cryogenic standard cell library. ColdADC_P2, with a die area of approximately 52.4 mm2 and fabricated in 65-nm CMOS technology, achieves 130- μ V rms noise performance and 11.8-bit effective-number-of-bits (ENOB) at a temperature of 77 K, with channel-to-channel crosstalk of < 0.06% while dissipating 338 mW (21 mW per channel). Residual nonlinearity that is consistent with dielectric absorption in the capacitors internal to the ADC is corrected using a lookup table.

Abstract Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range.

This research paper delves into a comprehensive investigation concerning the impact of additive noise and quantization error on the precision of amplitude, offset, and phase estimates of a sine wave fitted to a set of data points acquired by a waveform digitizer. Simulation results are used to validate the expressions presented. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-ΣΔM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors' modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors' system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range. [ABSTRACT FROM AUTHOR]

Manifold models in data analysis and signal processing have become more prominent in recent years. In this paper, we will look at one of the main tasks of modern signal processing, namely, at analog-to-digital (A/D) conversion in connection with a simple manifold model — the circle. We will focus on Sigma-Delta modulation which is a popular method for A/D conversion of bandlimited signals that employs coarse quantization coupled with oversampling. Classical Sigma-Delta schemes provide mismatches and large errors at the initialization point if the signal to be converted is defined on the circle. In this paper, our goal is to get around these problems for Sigma-Delta schemes. Our results show how to design an update for the first and the second order schemes based on the reconstruction error analysis such that for the updated scheme the reconstruction error is improved. [ABSTRACT FROM AUTHOR]

A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm2 and fabricated in 180-nm CMOS technology, achieves 22 e- equivalent noise charge (ENC) and a dynamic range of 190 ke- (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a 256 × 256 pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron.

This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.

The analog-to-digital converter (ADC) is not only a key component in analog in-memory computing (IMC) accelerators but also a bottleneck for the efficiency and accuracy of these systems. While the tradeoffs between power consumption, latency, and area in ADC design are well studied, it is relatively unknown which ADC implementations are optimal for algorithmic accuracy, particularly for neural network inference. We explore the design space of the ADC with a focus on accuracy, investigating the sensitivity of neural network outputs to component variability inside the ADC and how this sensitivity depends on the ADC architecture. The compact models of the pipeline, cyclic, successive-approximation-register (SAR) and ramp ADCs are developed, and these models are used in a system-level accuracy simulation of analog neural network inference. Our results show how the accuracy on a complex image recognition benchmark (ResNet50 on ImageNet) depends on the capacitance mismatch, comparator offset, and effective number of bits (ENOB) for each of the four ADC architectures. We find that robustness to component variations depends strongly on the ADC design and that inference accuracy is particularly sensitive to the value-dependent error characteristics of the ADC, which cannot be captured by the conventional ENOB precision metric.

This paper reviews the state of the art on bandpass Σ Δ modulators (BP- Σ Δ Ms) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP- Σ Δ M analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing.

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all-pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm2. The ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to-noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM. [ABSTRACT FROM AUTHOR]

In this article, a 6-GHz, 2-bit, fourth-order continuous-time delta–sigma (CT $\Delta \Sigma $) analog-to-digital converter (ADC) fabricated in 28-nm CMOS is presented. It achieves −101- and −105-dBc total harmonic distortion (THD)/third-order inter-modulation (IM3) typically and 72.3-dB signal to noise and distortion ratio (SNDR) in 120-MHz bandwidth (BW). The ADC comprises four cascaded integrators with inverter-based amplifiers, an offset compensated 2-bit quantizer, and calibrated 2-bit feedback (FB) digital-to-analog converter (DAC). The DAC and quantizer employ blind digital calibration techniques enabling the wideband linearity performance. The ADC does not require any external test signal during calibration. The power dissipation of the modulator core, including demultiplexer, is 108.8 mW. [ABSTRACT FROM AUTHOR]

The growing demand for bandwidth and energy efficiency requires new solutions for signal detection and processing. We demonstrate a concept for high-bandwidth signal detection with low-speed photodetectors and electronics. The method is based on the parallel optical sampling of a high-bandwidth signal with sinc-pulse sequences provided by a Mach-Zehnder modulator. For the electronic detection and processing this parallel sampling enables to divide the high-bandwidth optical signal with the bandwidth $B$ into $N$ electrical signals with the baseband bandwidth of $B/(\text{2}\,N)$. In proof-of-concept experiments with $N=3$, we present the detection of 24 GHz optical signals by detectors with a bandwidth of only 4 GHz. For ideal components, the sampling and bandwidth down-conversion does not add an excess error to the signals and even for the non-ideal components of our proof-of-concept setup, it is below 1%. Thus, the rms error for the measurement of the 24 GHz signal was reduced by a factor of about 3.4 and the effective number of bits were increased by 1.8.

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction. [ABSTRACT FROM AUTHOR]

Wearable sensors have demonstrated wide applications from medical treatment, health monitoring to real-time tracking, human-machine interface, smart home, and motion capture because of the capability of in situ and online monitoring. Data acquisition is extremely important for wearable sensors, including modules of probes, signal conditioning, and analog-to-digital conversion. However, signal conditioning, analog-to-digital conversion, and data transmission have received less attention than probes, especially flexible sensing materials, in research on wearable sensors. Here, as a supplement, this paper systematically reviews the recent progress of characteristics, applications, and optimizations of transistor amplifiers and typical filters in signal conditioning, and mainstream analog-to-digital conversion strategies. Moreover, possible research directions on the data acquisition of wearable sensors are discussed at the end of the paper. [ABSTRACT FROM AUTHOR]

Determining the quality of sensing devices exhibiting minimal digitization complexity is addressed. Measurements of such sensor systems are characterized by multivariate binary distributions and assessing sensitivity via the Cramér-Rao lower bound turns out to be intractable. In this context, the Fisher matrix of the exponential family and a lower bound for arbitrary probabilistic models are discussed. The conservative approximation for Fisher’s information matrix rests on a surrogate exponential family distribution connected to the actual data-generating system by two compact equivalences. Without characterizing the likelihood and its support, this probabilistic notion enables designing estimators that consistently achieve the sensitivity level defined by the inverse of the conservative information matrix. For hard-limited multivariate Gaussian signal models, a quadratic exponential surrogate distribution tames statistical complexity such that a quantitative and conservative assessment of Fisher information becomes possible. This result is exploited for the Fisherian quantization loss analysis of an array with low-complexity binary sensors in comparison to an ideal system featuring infinite amplitude resolution. Additionally, data-driven assessment by estimating a conservative approximation for the Fisher matrix under recursive binary sampling as implemented in ΣΔ-modulating analog-to-digital converters is demonstrated. [ABSTRACT FROM AUTHOR]

Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In this article, we show an example of a time-interleaved analog demultiplexer (ADeMUX) with four track-and-hold (T/H) circuits based on switched emitter followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar-CMOS (BiCMOS) technology for parallel operation of four CMOS ADCs. The 50% duty cycle of the clock signal facilitates its generation and can save power consumption in the clock path or enable higher sampling rates compared with the 25% duty-cycle clock of other ADeMUX architectures. We show that using switched preamplifiers in front of the SEFs can double the bandwidth of each T/H lane. Experimental verification shows up to 57-GHz input bandwidth while requiring only 16-GHz input bandwidth for each of the ADCs that can be connected to the four 32-GS/s output channels. The circuit achieves 3–6-bit accuracy and is suitable for 100-GBd signaling and beyond with pulse amplitude modulation. To demonstrate the capability of higher sampling rates, measurement results at 4 $\times $ 50 GS/s = 200 GS/s are provided as well although significant advancement of the measurement environment is needed for a complete evaluation. [ABSTRACT FROM AUTHOR]

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm2, including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s. [ABSTRACT FROM AUTHOR]

This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.

Classical sampling is based on acquiring signal amplitudes at specific points in time, with the minimal sampling rate dictated by the degrees of freedom in the signal. The samplers in this framework are controlled by a global clock that operates at a rate greater than or equal to the minimal sampling rate. At high sampling rates, clocks are power-consuming and prone to electromagnetic interference. An integrate-and-fire time encoding machine (IF-TEM) is an alternative power-efficient sampling mechanism which does not require a global clock. Here, the samples are irregularly spaced threshold-based samples. In this paper, we investigate the problem of sampling FRI signals using an IF-TEM. We provide theoretical guarantees for a recently proposed recovery method to perfectly recover an FRI input. In addition, we propose a modified sampling approach in the presence of noise that is more robust than existing techniques. This method is also proven to ensure recovery in the noise-free setting. The modified approach requires twice the number of measurements compared to the existing method, however, it results in lower error in the presence of noise for the same number of measurements. Our results enable designing low-cost and energy-efficient analog-to-digital converters for FRI signals. [ABSTRACT FROM AUTHOR]

This brief discusses the use of Artificial Intelligence (AI) to manage the operation and improve the performance of Analog-to-Digital Converters (ADCs) based on Sigma-Delta Modulators ($\Sigma \Delta $ Ms). The reconfigurable nature of $\Sigma \Delta $ Ms can be enhanced by AI algorithms in order to adapt the specifications of ADCs to diverse input signal requirements, environment interferences, noise levels, battery status, etc. A high degree of programmability is required, which demands for scaling-friendly, mostly-digital analog circuit techniques as well as suitable topologies of Artificial Neural Networks (ANNs) to implement the AI engine. Moreover, the practical implementation of AI-assisted $\Sigma \Delta $ Ms requires to adopt diverse design strategies – from the $\Sigma \Delta \text{M}$ architecture itself to AI modules and circuit building blocks – which are overviewed in this brief. As an application and case study, an ANN-assisted ADC for Software-Defined Radio (SDR) and Cognitive Radio (CR) is considered. The system is based on the use of a widely-tunable Band-Pass (BP)- $\Sigma \Delta \text{M}$ , and an ANN is used to predict the occupancy of frequency bands and modify the notch frequency of the BP- $\Sigma \Delta \text{M}$ accordingly. [ABSTRACT FROM AUTHOR]

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm2 in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM). [ABSTRACT FROM AUTHOR]

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator's output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66 dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5 V, exhibits a power consumption of 38 μ W, and uses a silicon area of 0.052 mm2, it is suitable for single battery-operated systems on a chip. [ABSTRACT FROM AUTHOR]

A control-bounded analog-to-digital converter consists of a linear analog system that is subject to digital control, and a digital filter that estimates the analog input signal from the digital control signals. Such converters have many commonalities with delta–sigma converters, but they can use more general analog filters. The paper describes the operating principle, gives a transfer function analysis, and describes the digital filtering. In addition, the paper discusses two examples of such architectures. The first example is a cascade structure reminiscent of, but simpler than, a high-order MASH converter. The second example combines two attractive properties that have so far been considered incompatible. Its nominal conversion noise (assuming ideal components) essentially equals that of the first example. However, its analog filter is a fully connected network to which the input signal is fed in parallel, which potentially makes it more robust against nonidealities. [ABSTRACT FROM AUTHOR]

Electrical-optical signal processing has been shown to be a promising path to overcome the limitations of state-of-the-art all-electrical data converters. In addition to ultra-broadband signal processing, it allows leveraging ultra-low jitter mode-locked lasers and thus increasing the aperture jitter limited effective number of bits at high analog signal frequencies. In this paper, we review our recent progress towards optically enabled time- and frequency-interleaved analog-to-digital converters, as well as their monolithic integration in electronic-photonic integrated circuits. For signal frequencies up to 65 GHz, an optoelectronic track-and-hold amplifier based on the source-emitter-follower architecture is shown as a power efficient approach in optically enabled BiCMOS technology. At higher signal frequencies, integrated photonic filters enable signal slicing in the frequency domain and further scaling of the conversion bandwidth, with the reconstruction of a 140 GHz optical signal being shown. We further show how such optically enabled data converter architectures can be applied to a nonlinear Fourier transform based integrated transceiver in particular and discuss their applicability to broadband optical links in general.

Wireless full-duplex (FD) transceivers have become more commonplace in the recent years, enabled by improvements in hardware as well as in signal processing algorithms dedicated to self-interference (SI) mitigation. A key design target for any FD radio is to limit the analog-to-digital converter (ADC) quantization noise affecting the signal of interest (SoI), which results from the difference in dynamic range between the SI and the SoI at the input of the ADC. Indeed, when using conventional ADCs, since the SI power is much larger than that of the SoI, the SI spans most of the ADC’s dynamic range and the SoI becomes distorted by a large quantization noise. Reducing the power of the SI before the ADC, for example via analog domain SI cancellation, is so far the only means to mitigate this undesired effect. In this paper we consider the use of so-called modulo ADCs as a new tool to reduce the quantization noise that affects the SoI in the presence of SI. We demonstrate theoretically and numerically that by substituting the conventional ADCs with modulo-ADCs, which fold the analog input signal before analog-to-digital conversion, and by using appropriately designed analog gain control and digital-domain SI cancellation, one can reduce the quantization noise that affects the SoI. As such, the work in this paper provides a new technique for counteracting the detrimental effect of SI in analog-to-digital conversion and, thus, provides a new route to be explored in order to enhance the performance of FD radios.

The dual-mode auto-calibrating resistance thermometer (DART) has recently been proposed for highly accurate temperature measurement based on noise thermometry. In this paper, it is demonstrated that calibration and operation of the DART at part-per-million (ppm) level should be possible with the hardware developed. For this purpose, we have extensively tested a representative signal path comprising the basic DART components. This includes a low-noise amplifier connected to a 24-bit ÎŁ Î" ADC and a metrology-grade voltage reference. A Josephson arbitrary waveform synthesizer (JAWS) generates a pseudo-noise consisting of low-distortion multitones superimposed on a low-frequency square-wave reference voltage. Using this signal, a fast and efficient calibration scheme for the signal path gain is demonstrated. The reference voltage stabilizes the gain at ppm level. We observed gain fluctuations within ± 2 ÎĽ V V âˆ' 1 over a period of 19 d, a temperature coefficient of âˆ' 0.5 ÎĽ V V âˆ' 1 K âˆ' 1 , and insignificant nonlinearity within an uncertainty band of ± 2 ÎĽ V V âˆ' 1 for rms input levels between 5 µV and 80 µV. The behavior of the signal path with a 300 Ω resistor as a noise source was also investigated. From the observed stability of the voltage reference and flatness of the noise gain between 10 kHz and 225 kHz, we estimate that the presented hardware components are suitable for temperature measurements with systematic uncertainties well below 10 ÎĽ K K âˆ' 1 . [ABSTRACT FROM AUTHOR]

The major limitation of the photonic digitization schemes based on the phase-shifting of modulation transfer function lies in its relatively low bit resolution, which is log2(2N ), where N is the number of optical channels or modulators. In this paper, we propose a novel photonic digitization scheme based on hierarchical quantization, which could greatly improve the system resolution with a relatively simple configuration. It is shown that 6N quantization levels, can be realized by using only three Mach-Zehnder modulators (MZMs) and a hierarchical quantization module (HQM) in the proposed scheme. By adjusting the fine quantization module inside HQM, the system resolution can be enhanced greatly. A proof-of-concept experiment is implemented, which fully verifies the correctness of the approach. Since simpler configuration and higher resolution are achieved, the proposed scheme provides a promising solution for high-performance photonic analog-to-digital conversion.

Today’s ultra-wideband optical equipment enables fiber-based data links with up to 1.6 Tbit/s per wavelength at a symbol rate of 128 Gbaud. However, high input signal path losses need to be overcome in commercial products when the digitizers are integrated with the digital signal processor in a deep-submicrometer FinFET-CMOS transceiver application specific integrated circuit (ASIC). This currently limits the analog-to-digital converter (ADC) sampling rate and the detectable link symbol rate to 97 GS/s and 66 Gbaud, respectively. Four of these bandwidth-limited ADCs can be time-interleaved with the presented analog 1-to-4 demultiplexer front end in a SiGe-BiCMOS technology that allows high bandwidths with transistor cutoff frequencies above 300 GHz. The sampling front end effectively divides the necessary ADC bandwidth by the time-interleaving factor, enabling the detection of ultra-high symbol rates of up to 128 Gbaud with only 16-GHz bandwidth requirement for the four ADCs. At these frequencies, subsequent circuits and chip interconnects exhibit significantly lower signal path losses than at 64 GHz—half the symbol rate—and therefore require only a reduced processing power for channel equalization in the analog and digital domain. We demonstrate sampling operation with a large-signal 3-dB bandwidth of 36 GHz and a 6-dB bandwidth of 50 GHz at 128 GS/s in an experimental testbed, as well as the reception of 128-Gbit/s NRZ/OOK and 256-Gbit/s PAM4 signals. The linearity reaches more than 3-bit effective number of bits (ENOB) with a sinusoidal input signal of 500 mVpp on each of the four output channels. The power consumption is equivalent to a sampling efficiency of 20 pJ/sample, narrowing the gap to slower CMOS solutions and enabling cost-efficient coherent optical links with up to 1 Tbit/s. [ABSTRACT FROM AUTHOR]