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Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology ("2.5D" stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traffic regularly. A load balancing strategy balances the traffics on the two network layers and optimizes the resources utilization. In the aforementioned strategy, after detecting congestion in the CPU layer, packets can be moved to the interposer one. It can be concluded that this transferring encounters the bottleneck of the edge portion that is connected to memory blocks. In this paper, we propose a Controlled Load Balancing Mechanism (CLBM) which efficiently controls bottleneck in load balancing methods. As a result, the CLBM selects an appropriate network based on the destination address without comparing latencies of two networks. Moreover, a multicast fault-tolerant ring is introduced to propagate network congestion information. The experimental results showed that, as compared with the absence of load balancing method and traditional load balancing strategy, our CLBM strategy achieves 37.82% and 17.22% average latency improvements and 22.19% and 8.55% average total power with minor overhead. [ABSTRACT FROM AUTHOR]

Early diagnosis of multiple sclerosis (MS) through the delineation of lesions in the brain magnetic resonance imaging is important in preventing the deteriorating condition of MS. This study aims to develop a modified U‐Net model for automating lesions segmentation in MS more accurately. The proposed modified U‐Net uses residual dense blocks to replace the standard convolutional stacks and incorporates three axes (axial, sagittal, and coronal) of 2D slice images as input. Furthermore, a custom fusion method is also introduced for merging the predicted lesions from different axes. The model was implemented on ISBI2015 and OpenMS data sets. On ISBI2015, the proposed model achieves the best overall score of 93.090% and DSC of 0.857 on the OpenMS data set. [ABSTRACT FROM AUTHOR]

In 2.5D stacking technology, multiple chips have stacked side‐by‐side on a silicon interposer layer. The network‐on‐chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked vertically. The network‐on‐chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock‐free routing algorithm on the CPU layer and interposer layer is essential. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform interconnection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub‐networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner. [ABSTRACT FROM AUTHOR]

Networks are an important means for the representation and analysis of data in a variety of research and application areas. While there are many efficient methods to create layouts for networks to support their visual analysis, approaches for the comparison of networks are still underexplored. Especially when it comes to the comparison of weighted networks, which is an important task in several areas, such as biology and biomedicine, there is a lack of efficient visualization approaches. With the availability of affordable high-quality virtual reality (VR) devices, such as head-mounted displays (HMDs), the research field of immersive analytics emerged and showed great potential for using the new technology for visual data exploration. However, the use of immersive technology for the comparison of networks is still underexplored. With this work, we explore how weighted networks can be visually compared in an immersive VR environment and investigate how visual representations can benefit from the extended 3D design space. For this purpose, we develop different encodings for 3D node-link diagrams supporting the visualization of two networks within a single representation and evaluate them in a pilot user study. We incorporate the results into a more extensive user study comparing node-link representations with matrix representations encoding two networks simultaneously. The data and tasks designed for our experiments are similar to those occurring in real-world scenarios. Our evaluation shows significantly better results for the node-link representations, which is contrary to comparable 2D experiments and indicates a high potential for using VR for the visual comparison of networks. [ABSTRACT FROM AUTHOR]

In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto–electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of −10 dBm at a BER lower than 10−12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively. [ABSTRACT FROM PUBLISHER]

As the trends driven by Moore’s law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration. [ABSTRACT FROM PUBLISHER]

3D-stacked DRAM has been actively studied to overcome the limits of conventional DRAM. The Hybrid Memory Cube (HMC) is a type of 3D-stacked DRAM that has drawn great attention because of its usability for server systems and processing-in-memory (PIM) architecture. Since HMC is not directly stacked on the processor die where the central processing units (CPUs) and graphic processing units (GPUs) are integrated, HMC has to be linked to other processor components through high speed serial links. Therefore, the communication bandwidth and latency should be carefully estimated to evaluate the performance of HMC. However, most existing HMC simulators employ only simple HMC modeling. In this paper, we propose a cycle-accurate simulator for hybrid memory cube called CasHMC. It provides a cycle-by-cycle simulation of every module in an HMC and generates analysis results including a bandwidth graph and statistical data. Furthermore, CasHMC is implemented in C++ as a single wrapped object that includes an HMC controller, communication links, and HMC memory. Instantiating this single wrapped object facilitates simultaneous simulation in parallel with other simulators that generate memory access patterns such as a processor simulator or a memory trace generator. [ABSTRACT FROM PUBLISHER]

Silicon interposers enable the integration of multiple stacks of in-package memory to provide higher bandwidth or lower energy for memory accesses. Once the interposer has been paid for, there are new opportunities to exploit the interposer. In this article, the authors exploit the interposer to "disintegrate" a multicore CPU chip into smaller chips that collectively cost less to manufacture than a single large chip. They study the performance-cost tradeoffs of interposer-based, multichip, multicore systems and propose new interposer network-on-chip (NoC) organizations to mitigate the performance challenges while preserving the cost benefits. Although this article focuses on NoC support for disintegrated systems, it paves the way for a range of new research problems in interposer-based disintegrated systems. [ABSTRACT FROM PUBLISHER]

For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integrate these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. Current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively. [ABSTRACT FROM AUTHOR]

In 2003, the authors predicted that reconfigurable systems would emerge within 10 years. They expected the arrival of a "Holy Grail"' memory component and chip and wafer stacking. These advances did not occur, which meant that field-programmable gate arrays (the key enabler of reconfigurable systems) did not achieve the breakthrough advance that would enable them for mobile applications. Ten years later, there is no Holy Grail memory component, and there's no wafer stacking; chip stacking is emerging. Reconfigurable systems should appear in markets where equipment has access to continuous power, but financial incentives and the lack of a versatile memory component inhibit their emergence in mobile systems. [ABSTRACT FROM PUBLISHER]

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation. [ABSTRACT FROM AUTHOR]

In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity. [ABSTRACT FROM AUTHOR]