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This article examines the feasibility of integrating solid-state plasma surface p-i-n (S-PIN) diodes into on-chip slots using silicon-on-insulator technology. Two categories of solid-state plasma S-PIN diodes are characterized. Simulations analyze the current–voltage (I–V) characteristics, carrier concentrations, potential distribution, and thermal considerations of both single and dual S-PIN diodes, with optimization of their structural parameters and sizes. Experimental tests on fabricated S-PIN diodes of varying sizes with bias lines embedded in the on-chip slots show favorable I–V characteristics for both types of diodes. The measured results closely align with simulation predictions for the diodes' conduction onset voltages. Additionally, a cavity-backed slot antenna is proposed to evaluate and compare radiation characteristics resulting from integrating different types of S-PIN diodes. [ABSTRACT FROM AUTHOR]

This article introduces a new, low cost and complexity, wideband Ku/K‐band combined low‐noise amplifier (LNA) Filter designed for large satellite phased array systems in advanced 22 nm Fully Depleted Silicon on Insulator Technology. The LNA achieves the required 20 dB gain through a two‐stage configuration using the cascode configuration. To effectively reject the transmitter (TX) signal, the LNA integrates 4 distributed parallel LC notch filters. Measured IP1dB at 29 GHz (TX band) demonstrates a 25 dB increase compared to IP1dB at 19 GHz (RX Band), with a remarkable 15 dB enhancement over the LNA without the filter. The 1‐dB gain bandwidth spans from 16 to 21 GHz, representing a 27% fractional bandwidth. Over the entire bandwidth, input/output return losses exceed 10 dB, maintaining a low noise figure (NF) of less than 3.5 dB. Inclusion of two filters at the input and middle of the first stage results in approximately 0.6 dB of increase in NF when compared to the LNA without the filter. [ABSTRACT FROM AUTHOR]

Besides being impacted by quantum confinement effects, the channel electrostatics of ultra-thin-body silicon-on-insulator (SOI) MOS devices, with channel thicknesses less than 10 nm, are also likely to be impacted by interface trap states. In this work, we comprehensively investigated the effect of band edge energy (surface passivation energy) on the band structure of the silicon channel. We propose to utilize this band edge energy (Δ E e d g e ) to study the effect of interface traps on device electrostatics, which is generally used to passivate the channel/oxide interface. First, by using s p 3 d 5 s ∗ semi-empirical tight-binding methodology with a fully passivated interface (Δ E e d g e > --> 5 eV) and by including suitable bandgap correction for different device temperatures, the band structure is obtained, which is solved self-consistently with Poisson's equation to accurately determine the channel electrostatics, without the effect of trap states. Interface trap states are now seen in the band structure through suitably varying the edge energy (− 5 eV < Δ E e d g e < 5 eV) based on which the interface trap density (D i t ) and the interface trap charge density (Q i t ) are determined. Through incorporating Q i t in the boundary condition for solving Poisson's equation self-consistently with the band structure, channel electrostatics is recomputed to analyze the effect of traps for a wide range of device conditions. Finally, the degradation in the integrated charge density due to interface traps is accurately modeled for different SOI channel thickness and device temperatures. [ABSTRACT FROM AUTHOR]

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

We analyze the two classic methods for chirped Integrated Bragg Gratings (IBGs) in Silicon-on-Insulator technology using the transfer matrix method based on the effective refractive index (neff) technique, which translates the geometry of an IBG into a matrix of neff depending on the wavelength. We also implement a procedure that allows engineering of the chirped IBG parameters, given a required bandwidth (BW) and group delay (GD). Finally, a complementary method for designing chirped IBG is proposed, showing a significant improvement in the bandwidth of the device or a moderation in the variation of the geometrical parameters of the grating. [ABSTRACT FROM AUTHOR]

Over the past decades Silicon on Insulator (SoI) technology has tantalized the interest of researchers in the design of numerous nonlinear Photonic Integrated Circuits (PIC's) to provide a variety of devices. In this manuscript, four different types of optical add/drop resonators are proposed and compared using their simulated microcomb notch filter performance. The four types of resonators are (i) rectangular waveguide based conventional ring resonator, (ii) slot waveguide based ring resonator, (iii) rectangular waveguide based racetrack resonator, and (iv) slot waveguide based racetrack resonator, for variety of active/passive applications. The resonator parameters: Free Spectral Range (FSR), Full Width at Half Maximum (FWHM), Finesse (F) and Quality factor (Q-factor) are evaluated and compared for four resonators. The resonators are optimized for different parameters, such as ring radius (R), gap (g) between the waveguides and coupling length (Lc). The optimized R of ~ 30 μm with the power coupled 'g' of 55 nm is found after performing rigorous simulations for the entire optical conventional band (C-band) i.e., in 1530 nm – 1565 nm using Finite Element Method (FEM). The manuscript provides valuable insights into the design considerations and performance trade-offs of different optical resonators in PICs showing symmetricity along x-axis and y-axis. These findings can guide the development of efficient and high-performance integrated photonic devices for various applications, including communication and computing systems. [ABSTRACT FROM AUTHOR]

In this paper, a compact mid-infrared (MIR) transverse-electric (TE)-pass polarizer is presented and numerically examined. The introduced polarizer is built on silicon-on-sapphire (SOS) platform. Such platform boasts key features such as minimal power consuming, superior linearity, and transmission with high speed, making it particularly advantageous for various applications, especially in the MIR spectrum. The proposed design is complementary metal-oxide-semiconductor (CMOS)-compatible based on bi-metallic materials, aluminium doped zinc oxide and titanium nitride, as alternative plasmonic materials. Large coupling between the surface plasmon and fundamental transverse magnetic (TM) modes is occurred in the silicon core by the bimetallic effect. Nevertheless, the transverse-electric mode can travel with negligible losses. The suggested TE-pass polarizer attains, at a 2 µm operating wavelength, an extinction ratio (ER) of 17.5 dB accompanied by an insertion loss (IL) of 0.1 dB at a device length of 3 µm. Moreover, the introduced polarizer design is simple and has high resilience to fabrication errors. [ABSTRACT FROM AUTHOR]

This paper presents a highly sensitive hybrid plasmonic liquid crystal channel-based temperature sensor. The proposed structure has V-groove waveguide channel infiltrated with nematic liquid crystal (NLC) material of type E7 and coated by a gold (Au) layer to excite the surface plasmon resonance at the metal/dielectric interface. The NLC refractive indices depend on the temperature which affects the resonance wavelength where coupling occurs between the core and surface plasmon modes. The full vectorial finite element method is employed to evaluate the sensing performance of the reported sensor. The numerical results show that the suggested sensor can achieve an average temperature sensitivity of 24.5 nm/°C over a temperature range from 15 to 40 °C. The obtained wavelength sensitivity is higher than those of most similar temperature sensors based on silica-silicon or silicon-on-insulator technology in literature. In addition, the average amplitude sensitivity and figure of merit of the presented sensor are 0.135 °C− 1 and 0.43 °C− 1, respectively. Moreover, the introduced structure is complementary metal-oxide-semiconductor compatible with simple design and good fabrication tolerance of ± 5% where the temperature sensitivity is better than 23 nm/°C. [ABSTRACT FROM AUTHOR]

This paper presents for the first time a quad-core oscillator based on a very compact interstacked transformer that tightly couples the four cores without oscillation mode ambiguity thanks to its strong magnetic coupling factor. As a proof of concept, a 19.125 GHz oscillator for a narrowband 77 GHz radar system was designed in 28 nm fully depleted silicon-on-insulator CMOS technology with a general purpose back-end-of-line. The soundness of the proposed quad-core oscillator topology is demonstrated by comparison with state-of-the-art quad-core solutions, highlighting a significant advantage in terms of area occupation and power consumption. The proposed topology can be profitably exploited in several RF/mm-wave applications, such as radar and wireless communication systems. [ABSTRACT FROM AUTHOR]

On‐chip spatial and polarization multiplexing has emerged as a powerful strategy to boost the data transmission capacity of integrated optical transceivers. State‐of‐the‐art multiplexers require accurate control of the relative phase or the spatial distribution among different guided optical modes, seriously compromising the optical transmission bandwidth and performance of the devices. To overcome this limitation, a new approach based on the coupling between guided modes in integrated waveguides and optical beams free‐propagating on the chip plane is proposed. The engineering of the evanescent coupling between the guided modes and free‐propagating beams allows spatial and polarization multiplexing with state‐of‐the‐art performance. A two‐polarization multiplexed link and a three‐mode multiplexed link using standard 220‐nm‐thick silicon‐on‐insulator technology have been developed. The two‐polarization link shows a measured −35 dB crosstalk bandwidth of 180 nm, while the three‐mode link exhibits a −20 dB crosstalk bandwidth of 195 nm. These links are used to demonstrate error‐free operation (bit‐error‐rate <10−9) in multiplexing and demultiplexing of two and three non‐return‐to‐zero signals at 40 Gbps each, with power penalties below 0.08 and 1.5 dB for the two‐polarization and three‐mode links, respectively. The approach demonstrated for two polarizations and three modes is transferable to future implementation of more complex multiplexing schemes. [ABSTRACT FROM AUTHOR]

A commercial thermo-optic phase shifter (TOPS) is an efficient solution to the imbalance problem in the fabrication process of Mach–Zehnder modulator (MZM) arms. The TOPS consumes electrical power and transforms it into thermal energy, which changes the real part of the effective refractive index at the waveguide and adjusts the MZM transfer function to work in the linear region. The common model being used today is constructed with only one heater; however, this solution requires more electrical power, which can increase the transmitter system cost. To reduce the system energy cost, we propose a pioneering optimal double titanium nitride heater model under forward biasing at 1550 nm wavelength using the standard silicon-on-insulator technology. Numerical investigations were carried out on the key relative geometrical parameters, heat distribution at the silicon layer, thermal crosstalk, and laser wavelength drift. Results show that the optimal TOPS design can function with a low electrical power of 19.1 mW to achieve a π-phase shift, with a low thermal crosstalk of 0.404 and very low optical losses over 1 mm length. Thus, the proposed device can be used for improving the imbalance problem in MZMs with low electrical power consumption and low losses. This functionality can be utilized to obtain better performances in transmitter systems for data centers and long-range optical communication system applications. [ABSTRACT FROM AUTHOR]

The effect of quantum confinement has become significant in terms of its impact on the scalability and electrostatics of ultra-thin-body double-gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson's equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the s p 3 d 5 s ∗ tight-binding method (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively. [ABSTRACT FROM AUTHOR]

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical characteristics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible. [ABSTRACT FROM AUTHOR]

In the present work, a method to determine the optical waveguide properties of silicon‐on‐insulator (SOI) integrated circuits has been developed. According to the explicit relations between transfer functions of a microring resonator and the waveguide properties the inner optical parameters could be extracted. An increase in accuracy can be achieved by measuring the transfer functions of additional elements, such as a straight waveguide and a directional coupler. It is shown that the developed method allows one to determine the coupling coefficient, damping decrement, Bragg grating coupler efficiency, and waveguide dispersion with high accuracy. The obtained optical waveguide properties are used for modeling the transmission of a Mach–Zehnder interferometer which is used as a control element. The modeling results demonstrate a good agreement with the experimental characteristics. The developed method paves the way to local characterization of large‐scale SOI integrated circuits by using the aforementioned structures as reference elements. [ABSTRACT FROM AUTHOR]

A fully depleted silicon-on-insulator (FDSOI) device is a promising structure for future ultrascaled devices because of its high radiation resistance. The buried oxide (BOX) layer of an FDSOI device not only enhances its robustness against single event effects (SEE) but also greatly reduces its ability to resist the effect of the total ionizing dose (TID). We studied factors such as the thickness of BOX layers and the bias state of FDSOI devices and proposed a 22 nm N-type FDSOI 2D device structure. The method of adding fixed charges to the BOX layer and adding state charges to the interface was used to simulate the TID effect. We showed that the thinner the BOX layer, the better the device's ability to resist the effects of the TID. Increasing the total radiation dose causes the electron density of the channel to increase, indicating that the electron mobility of the channel is degraded. Because a large number of electrons are generated by irradiation, their density increases, causing a large number of electrons to collide with each other and scatter under a bias voltage, resulting in decreased electron mobility. By activating the built-in radiation model of the Sentaurus next-generation technology computer-aided design (TCAD) simulation tool, the device was used to simulate the TID effect under different doses in different bias states (OFF, ON, and transmission). The results showed that the most unappealing bias state of the TID effect for the short-channel N-type FDSOI device is the off state. This research provides new insights into the TID for FDSOI devices and can provide guidelines for future applications of radiation-hardened FDSOI-based circuits. The study of single particle effects plays an important role in the study of image sensors in space stations. [ABSTRACT FROM AUTHOR]

Microfluidic systems are widely used in fundamental research and industrial applications due to their unique behavior, enhanced control, and manipulation opportunities of liquids in constrained geometries. In micrometer-sized channels, electric fields are efficient mechanisms for manipulating liquids, leading to deflection, injection, poration or electrochemical modification of cells and droplets. While PDMS-based microfluidic devices are used due to their inexpensive fabrication, they are limited in terms of electrode integration. Using silicon as the channel material, microfabrication techniques can be used to create nearby electrodes. Despite the advantages that silicon provides, its opacity has prevented its usage in most important microfluidic applications that need optical access. To overcome this barrier, silicon-on-insulator technology in microfluidics is introduced to create optical viewports and channel-interfacing electrodes. More specifically, the microfluidic channel walls are directly electrified via selective, nanoscale etching to introduce insulation segments inside the silicon device layer, thereby achieving the most homogeneous electric field distributions and lowest operation voltages feasible across microfluidic channels. These ideal electrostatic conditions enable a drastic energy reduction, as effectively shown via picoinjection and fluorescence-activated droplet sorting applications at voltages below 6 and 15 V, respectively, facilitating low-voltage electric field applications in next-generation microfluidics. [ABSTRACT FROM AUTHOR]

Low frequency noise (LFN) and random telegraph noise (RTN) are investigated statistically on nanoscale MOSFETs of 28 nm fully depleted silicon-on-insulator technology. The analysis reveals that the mean noise level is well described by the carrier number fluctuations with a correlated mobility fluctuations model. As for the RTN, it is shown that the mean amplitude of signals is driven by correlated mobility fluctuations in strong inversion. The comparison between the extracted parameters of the LFN and RTN analysis demonstrates that the remote Coulomb scattering impact due to the trapped and detrapped charges remains the same on average for this technology, whether it is the average noise spectrum of all devices or the average amplitude of the detected RTN signals. [ABSTRACT FROM AUTHOR]

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications. [ABSTRACT FROM AUTHOR]

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices. [ABSTRACT FROM AUTHOR]

Photonic logic gates have important applications in fast data processing and optical communication. This study aims to design a series of ultra-compact non-volatile and reprogrammable photonic logic gates based on the Sb2Se3 phase-change material. A direct binary search algorithm was adopted for the design, and four types of photonic logic gates (OR, NOT, AND, and XOR) are created using silicon-on-insulator technology. The proposed structures had very small sizes of 2.4 μm × 2.4 μm. Three-dimensional finite-difference time-domain simulation results show that, in the C-band near 1550 nm, the OR, NOT, AND, and XOR gates exhibit good logical contrast of 7.64, 6.1, 3.3, and 18.92 dB, respectively. This series of photonic logic gates can be applied in optoelectronic fusion chip solutions and 6G communication systems. [ABSTRACT FROM AUTHOR]

We designed and manufactured two single-mode fiber-to-chip three-dimensional (3D) edge couplers with taper and semi-cone structures on a 3.5 µm silicon device layer of a silicon-on-insulator. The 3D finite-difference time-domain is used to simulate and optimize the structure of the edge couplers within the 1550 nm band. The simulation results reveal a maximum coupling efficiency of the 3D edge couplers above 91.42% for the TE mode. The 3 dB coupling tolerances of the TE mode in horizontal and vertical directions are ±4.5 and ±1.5 µm, respectively. Laser-direct-writing grayscale lithography and inductive coupled plasma-reactive ion etching are used in the fabrication of 3D edge couplers. Experimental data show that 3D couplers have a maximum coupling efficiency of about 83.41% in the TE mode. [ABSTRACT FROM AUTHOR]

• Improved surface potential equation (SPE) for dynamically-depleted (DD) SOI MOS devices. • Details on the origins of previous DD-SOI MOS device SPE issues. • Description of the front-depletion/back-accumulation (DA) operation mode. • Appropriate mathematical conditioning at flat band-condition. This paper provides an improved surface potential equation for compact modeling of dynamically depleted silicon-on-insulator MOS device. It removes the non-physical front-gate capacitance prediction and the discontinuity at the flat-band condition present in previous works. It also includes for the first time the back gate effect observed at negative back gate voltage when the silicon film is partially depleted. It relies on, firstly, an approximated description of the front-depletion/back-accumulation mode of operation that has always been ignored by now, and secondly, an appropriate mathematical conditioning. The model is validated by 3D TCAD simulations. [ABSTRACT FROM AUTHOR]

A biosensor for detecting DNA hybridization via refractive index sensing has been demonstrated using a subwavelength grating (SWG) waveguide. Waveguide dimensions are selected by parametric optimizations to increase the mode-analyte overlap with considerations of typical silicon-on-insulator fabrications technology. DNA layer is added with a linker layer on silicon pillars of the SWG waveguide to optimize and detect the DNA hybridization. Some essential characteristics such as mode overlap factor, change in effective refractive index, waveguide sensitivity, and shift in resonance wavelength are computed for the different dimensional parameters of the SWG waveguide in DNA hybridization along with mode field intensity and normalized power using the finite element method. The DNA hybridization is shown by variation in normalized power of interacting light in cladding region of the waveguide for 0% to 100% fractional change of dsDNA and ssDNA. Waveguide sensitivity, shift in resonance wavelength, device sensitivity, and intrinsic limit of detection are obtained to ∼ 0.157, 7.01, 605 nm/RIU, and 1.30 × 10−4 RIU, respectively, for the optimized structure of SWG waveguide in sensing of DNA hybridization, which could be suitable aspects for detecting DNA hybridization. [ABSTRACT FROM AUTHOR]

The results of studying the contribution of the self-heating mechanism to the CVCs of high-power LDMOS (laterally diffused metal oxide semiconductor) transistors made according to the silicon-on-insulator technology with a long drift region with topological norms of 0.5 microns at high control voltages are discussed. It is shown that the action of this mechanism significantly changes the CVC of n- and p-type transistors. Differences in the influence of the self-heating mechanism on the characteristics of transistors of the n- and p-type are determined. The results obtained also open up new opportunities for improving the characteristics of microcircuits during their development and methods for further improvement of the LDMOS technology. [ABSTRACT FROM AUTHOR]

Fully depleted Silicon on insulator technology (FDSOI) is proposed to solve the various non-ideal effects when the process size of integrated circuits is reduced to 45 nm. The research of traditional FDSOI devices is mostly based on simulation software, which requires a lot of calculation and takes a long time. In this paper, a deep learning (DL) based electrical characteristic prediction method for FDSOI devices is proposed. DL algorithm is used to train the simulation data and establish the relationship between the physical parameters and electrical characteristics of the device. The network structure used in the experiment has high prediction accuracy. The mean square error of electrical parameters and transfer characteristic curve is only 4.34 × 10â€"4 and 2.44 × 10â€"3 respectively. This method can quickly and accurately predict the electrical characteristics of FDSOI devices without microelectronic expertise. In addition, this method can be extended to study the effects of various physical variables on device performance, which provides a new research method for the field of microelectronics. [ABSTRACT FROM AUTHOR]

It is possible to achieve selective electrochemical etching between different materials, such as p- and n-type silicon. However, achieving selective electrochemical etching on two different regions of the same p-type silicon material is a problem that has rarely been considered. Herein, a novel selective electrochemical etching technique for cantilever-type silicon-on-insulator (SOI) wafer-based microswitches is proposed. In this study, a p-type handle layer was selectively etched, and a p-type device layer was passivated. This was achieved using a circuit with two voltage sources: voltages of −1.2 and 0 V were applied to the handle and device layers, respectively. It was found that the proposed etching process can effectively prevent the in-use sticking of a cantilever-type switch. This is accomplished by increasing the gap between the device layer and its underlying handle layer and increasing the roughness of these layers. The technique is applicable to the fabrication of various cantilever-type SOI microelectromechanical systems, irrespective of the resistivity of the SOI wafer. HIGHLIGHTS: • The roughness of the handle layer was increased using the proposed selective electrochemical etching technique. The roughness of the handle layer was about 82.9 nm after electrochemical etching with HF vapor, and it was about 18.6 nm after electrochemical etching with aqueous hydrofluoric acid (HF). • The detachment length of the fabricated cantilever was increased. Touch switches with lengths and widths of 100, 300, and 500 µm were fabricated. The detachment length was increased from 100 µm before electrochemical etching to 500 µm after 4-min electrochemical etching with aqueous HF, and the gap between the cantilever and the substrate was increased from 1.00 to 1.25 µm. The effectiveness of the selective electrochemical etching for preventing fabrication sticking was confirmed. • The pressure required to cause in-use sticking was increased. We took switches with length 300 µm and width 500 µm as examples. For the switch without electrochemical etching, the pressure that caused sticking was 35.5 kPa; for the switch etched with HF vapor, this was 639 kPa. The effectiveness of the selective electrochemical etching in preventing in-use sticking was thus confirmed. [ABSTRACT FROM AUTHOR]

In this letter, we have explored the DC, small and large-signal RF reliability of the Power Amplifier (PA) cell for mm-wave applications under DC and RF stress. The PA cell comprises of a single transistor that employs 45RFSOI technology. For the first time here, a PA cell consisting of p-channel partially depleted Silicon-On-Insulator (PD-SOI) FET has been investigated for large-signal reliability behavior. At the same stress conditions, the impact of hot carrier degradation (HCD) on a p-channel FET (PFET) PA cell is also compared with the n-channel FET (NFET) PA cell. As the reliability of the PFET PA cell is superior than NFETs, a deeper investigation of hot carrier degradation and its impact on PA cell reliability is carried out. The PA cell is subjected to extensive RF characterization for varying DC stress and RF power at the gate terminal. The behavior of the time slope exponent of the PFET PA cell is studied to understand the nature of defects. Accelerated aging experiments using DC bias at drain/gate terminals and RF power at the gate terminal is performed. These results show that the RF reliability of the PFET PA cell is superior than its counterpart NFET PA cell at mm-wave frequencies. [ABSTRACT FROM AUTHOR]

This paper presents a 77 GHz two path power amplifier (PA) for automotive radar applications. It was fabricated in 28-nm fully depleted silicon-on-insulator CMOS technology, which provides transistors with a transition frequency of about 270 GHz and a general-purpose low cost back-end-of-line. The proposed PA consists of a 50 Ω input buffer followed by two power units, which are made up of a current-reuse common source driver for improved efficiency and a stacked cascode power stage for enhanced output power. A peak detector was also embedded into the PA for output power monitoring. The designed PA achieved a saturated output power as high as 17.4 dBm at 77 GHz with an excellent power added efficiency of 19%, while drawing 150 mA from a 2 V power supply. The core die size was 500 μm × 300 μm. [ABSTRACT FROM AUTHOR]

The electrically detected orbital spectrum of a mesoscopic silicon device containing a small number of donors has been investigated. The device was fabricated on silicon-on-insulator with an optically active channel containing 6 × 10 5 substitutional bismuth centers introduced by ion implantation. The 1 s (A 1) → 2 p ± orbital transition at the energy associated with isolated bismuth donors was detected via a change in photocurrent when illuminated by THz light from a free electron laser. The spectral dependence on bias, temperature, and laser intensity is explored to determine optimum conditions for detecting orbital transitions in smaller devices with fewer donors. These results suggest that photo-induced impact ionization can offer a route for the spectroscopic detection of few impurities providing a useful tool for the development of solid-state quantum technologies. [ABSTRACT FROM AUTHOR]

This work proposes a structure which allows characterization of graphene monolayers under combined electric field and mechanical strain modulation. Our approach is based on a cantilever integrated into a two-dimensional graphene-based Field effect transistor (FET). This allows us to change graphene properties either separately or together via two methods. The first way involves electric field induced by the gate. The second is induction of mechanical strain caused by external force pushing the cantilever up or down. We fabricated devices using silicon-on-insulator wafer with practically zero value of residual stress and a high-quality dielectric layer which allowed us to precisely characterize structures using both mentioned stimuli. We used the electric field/strain interplay to control resistivity and position of the charge neutrality point often described as the Dirac point of graphene. Furthermore, values of mechanical stress can be obtained during the preparation of thin films, which enables the cantilever to bend after the structure is released. Our device demonstrates a novel method of tuning the physical properties of graphene in silicon and/or complementary metal-oxide-semiconductor technology and is thus promising for tunable physical or chemical sensors. [ABSTRACT FROM AUTHOR]

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices' tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs' TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors' sensitivity to the TID charge and reduce the threshold voltage shift by >2x. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor's robustness. [ABSTRACT FROM AUTHOR]

This letter presents a low‐noise amplifier with a 3 dB‐bandwidth, from 55 to 74 GHz, excellent noise performance and low power consumption based on a three‐stage common‐source topology. For the first time to the authors' best knowledge, an analytical equation that also considers the gate–drain capacitance is derived for the employed shunt–series transformer feedback input matching network. To enable shunt–series transformer feedback matching without significant gain reduction a highly asymmetric transformer is designed. Furthermore, a compact transformer‐implemented T‐shaped output matching network is investigated to minimize the required area. To prove these concepts, the circuit has been fabricated in a 22 nm fully depleted silicon‐on‐insulator technology. Thanks to the transformer‐based matching, an ultra‐compact active footprint of 0.039 mm2 is achieved. At a power consumption of 8.4 mW from a 0.41 V supply an average noise figure of 4.8 dB and a peak gain of 14.2 dB has been measured. In‐ and output matching better than −10 dB over the 19 GHz wide 3 dB‐bandwidth are demonstrated. [ABSTRACT FROM AUTHOR]

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch-off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off-state. Adopting the new freewheeling circuit, the reverse recovery charge (QRR) and the peak reverse recovery current (IRRM) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process. [ABSTRACT FROM AUTHOR]

• Highly oriented crystalline si on epi‑Gd2O3/Si(111) substrate by RF sputtering. • At 850oC annealing, epi‑regrowth at Gd2O3/Si interface improves Gd2O3 crystallinity. • 850oC annealing fuses smaller Si grains into larger ones, enhancing crystallinity. • Low-cost technique for the fabrication of Silicon-on-Insulator technology. Silicon-on-Insulator (SOI) technology has been the center of attraction with the advancement in Radio Frequency (RF) technology and the advent of Internet-of-Things due to its low-power operation with reduced parasitic and short-channel effects. However, the state-of-the-art smart-cut method used for the SOI wafer is costly. Alternatively, the notion of using the Si channel layer on epitaxial rare-earth oxide has been proposed. In literature, the existing techniques used to achieve the same, such as Molecular beam Epitaxy or reduced-pressure chemical vapor deposition technique, are either costly or non-high-volume manufacturable. In this context, we propose a method to fabricate the highly oriented crystalline Si(111) channel layer (Top-Si) on an epitaxial Gd 2 O 3 /Si(111) virtual substrate (SOXI) utilizing the solid phase epitaxy using the high-volume manufacturing friendly (HVM), low-cost RF magnetron sputtering technique. First, we have shown the multicrystalline Si and epitaxial Gd 2 O 3 layer grown on Si(111) substrate, as confirmed using high-resolution X-ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM). Second, we investigated the impact of rapid thermal annealing at 850 °C on the heterostructure using HRXRD and TEM. It is observed that the high-temperature annealing transforms the Top-Si layer into the highly oriented crystalline Si(111) layer by fusing smaller grains towards larger grains. Hence, we demonstrate a low-cost, HVM-friendly technique for the fabrication of SOXI wafers. [ABSTRACT FROM AUTHOR]

We have been developing silicon-on-insulator (SOI) pixel detectors with a pinned depleted diode (PDD) structure, named "XRPIX", for X-ray astronomy. The PDD structure is formed in a thick p-type substrate, to which high negative voltage is applied to make it fully depleted. A pinned p-well is introduced at the backside of the insulator layer to reduce a dark current generation at the Si-SiO 2 interface and to fix the back-gate voltage of the SOI transistors. An n-well is further introduced between the p-well and the substrate to make a potential barrier between them and suppress a leakage current. An optimization study on the n-well dopant concentration is necessary because a higher dopant concentration could result in a higher potential barrier but also in a larger sense-node capacitance leading to a lower spectroscopic performance, and vice versa. Based on a device simulation, we fabricated five candidate chips having different n-well dopant concentrations. We successfully found out the best n-well design, which suppressed a large leakage current and showed satisfactory X-ray spectroscopic performance. Too low and too high n-well dopant concentration chips showed a large leakage current and degraded X-ray spectroscopic performance, respectively. We also found that the dependency of X-ray spectroscopic performance on the n-well dopant concentration can be largely explained by the difference in sense-node capacitance. [ABSTRACT FROM AUTHOR]

The test chip including transistors and Static Random Access Memory (SRAM) is proposed and fabricated by an advanced 22 nm Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-on-Insulator (UTBB FD-SOI) technology. Experimental results of Co-60 irradiation and heavy ion experiments are presented. Total Ionizing Dose (TID) experiment results show that the threshold voltage shift of the transistor is about 100 mV when the dose is 500 krad(Si) and the SRAM irradiated to a dose of at least 300 krad(Si) can maintain its functionality, which means that 22 nm UTBB FD-SOI devices exhibit significantly improved total dose tolerance performance compared to the previous generation process. TID-induced threshold voltage shift in conventional-well nMOSFET can be mitigated by applying biasing to back-gate, while back-gate biasing is invalid for TID mitigation of the conventional-well pMOSFET. Heavy ion experimental results make known that 22 nm UTBB FD-SOI technology has contributions to Single Event Effect (SEE) hardness and the hardened SRAM has higher single event upset (SEU) tolerance and even SEU immunity. The research indicates that the circuits manufactured by 22 nm UTBB FD-SOI technology have great potential space applications in harsh radiation environments. • Back-gate biasing is valid for TID mitigation in RBB NMOS, which is invalid in RBB PMOS. • The 22 nm SRAM irradiated to a dose of 300 krad(Si) can maintain its functionality. • No error was recorded in DICE SRAM under all heavy ion experimental conditions. • The 22 nm UTBB FD-SOI has great potential applications in radiation environments. [ABSTRACT FROM AUTHOR]

• Epitaxial cubic-Gd 2 O 3 with (222) oriented planes on Si (111) by RF sputtering. • Phase evolution and chemical dynamics study with rapid thermal annealing (RTA). • 850 °C RTA, enhancement in epi‑Gd 2 O 3 phase by epi‑regrowth of amorphous interface. • Si out-diffusion in Gd 2 O 3 (> 900 °C) causes degradation in film crystallinity. • Low-cost solution for buried oxide layer in Silicon-on-Insulator technology. Epitaxial growth of Si on rare-earth oxides on Si wafer using sputter technology promises cheaper and high-volume manufacturing of Silicon-on-insulator (SOI) wafers over costly solutions like the smart-cut method. Further, rapid thermal annealing (RTA) in standard complementary metal–oxide–semiconductor (CMOS) processing affects the performance of SOI substrate through chemical and crystal phase change. Herein, we present a systematic study on the rich physical and chemical phase evolution of epitaxial Gd 2 O 3 grown on Si (111) using RF sputtering subjected to RTA temperatures (850 − 1050 °C). First, X-ray diffraction analysis shows a significant enhancement of the epitaxial cubic phase in as-deposited Gd 2 O 3 at an optimum RTA temperature of 850 °C, which is partially explained by epitaxial-regrowth of an amorphous layer at Gd 2 O 3 /Si interface as observed in Transmission Electron Microscopy. Secondly, the degradation of crystallinity beyond 900 °C is correlated with temperature-dependent Si diffusion into Gd 2 O 3 that becomes observable by X-ray photoelectron spectroscopy. The Gd 2 O 3 crystallinity is completely quenched into the amorphous gadolinium silicate phase at 1050 °C. Eventually, we employed X-ray reflectivity modeling to evaluate the film thickness variation with RTA. This study provides a detailed insight into the structural and chemical dynamics occurring in epitaxial-Gd 2 O 3 film for CMOS-relevant temperatures. [ABSTRACT FROM AUTHOR]

• Parasitic capacitances of interconnects in FD-SOI devices were extracted using e-test and virtual fabrication modelling. • Poly-to-contact capacitance varies between 2aF and 10aF, representing 10% to 30% of the total interconnect capacitance. • Virtual fabrication modelling provides a fair estimation of parasitic capacitance in interconnects stacks. This paper describes an extraction methodology for segmenting the different contributions to interconnect and contact driven parasitic capacitance present on a 28 nm Fully Depleted Silicon On Insulator technology. The segmentation was enabled by creating specific test structures that had been designed, processed, and electrically tested across full wafer mappings. A 3D semiconductor process model, including capacitance extraction, was subsequently built and calibrated using the statistical distribution of actual silicon data. Once fully calibrated (<3% mean deviation to actual data), the model was used to understand the sensitivity of parasitic capacitance to specific process/design parameters and to enable Design Technology Co-Optimization. [ABSTRACT FROM AUTHOR]

The present work focuses on experimental investigations of a bistable silicon-on-insulator (SOI) micro-ring resonator (MRR). The resonator exploits a continuous-wave operation of the carrier-induced bistability demonstrating a stable hysteresis response at the through and drop ports when the input power exceeds the threshold value. Flipping the optical input power provides a convenient mechanism for a switching of the MRR output characteristics between two steady states having a long holding time. The transition of the resonator output between these states is experimentally investigated. It is shown that the switching speed is limited by a low-to-high transition of 188 ns. Obtained results shows an application of the passive SOI MRR as an all-optical memory cell with two complementary outputs. • Robust performance of passive ring resonator as all-optical memory cell is presented. • Principle of operation is based on carrier-induced bistability. • Free-carrier effect yields the long holding time and high switching speed. [ABSTRACT FROM AUTHOR]

The article reports that the EDFAS Education Subcommittee strives for the development and delivery of educational products to the EDFAS membership, and Keeping with its strategic focus on reaching a broader audience, including facilitating Q&A and educational exchanges on the ASM Connect platform.

• Radio frequency (RF) sputtering to demonstrate epitaxial growth of Gadolinia on Si (111). • Crystal quality examination using high resolution x-ray diffraction. • Electrical quality assessment using capacitance-voltage measurement. • Crystal phase transfer with RF power tuning. • Potential low cost solution for buried oxide layer in silicon-on-insulator technology. Rare earth oxides such as Gadolinia ( Gd 2 O 3) are extensively explored for buried oxide (BOX) application as a replacement for silicon dioxide (SiO 2) in silicon-on-insulator (SOI) substrates. Of all the proposed methods, molecular-beam-epitaxy-based techniques have shown perfectly single-crystalline growth of Gd 2 O 3. We present a radio frequency (RF) magnetron sputter based low-cost technique to grow single-crystalline Gd 2 O 3 on Si (111) substrate. We show a gradual phase transition of the Gd 2 O 3 layer from monoclinic to cubic by engineering the Gd 2 O 3 deposition rate–i.e., tuning the RF power. We present a comparison amongst three samples as follows: (a) monoclinic ; (b) monoclinic+cubic ; (c) cubic at three different RF powers keeping the rest of the process conditions such as chamber pressure, Argon flow rate, etc., fixed. Further, we present a detailed structural characterization of all the three samples using a high-resolution X-ray diffraction system. Using the ω − 2 θ and pole-figure measurements we show a highly textured monoclinic Gd 2 O 3 layer formation with (-402) crystal orientation in experiment (a). In experiment (c) we show phase transition of Gd 2 O 3 from monoclinic to cubic by tuning the RF power. Finally, with experiment (b), we demonstrate that the aforementioned phase transition is a gradual phenomenon by highlighting a coexistence of both the monoclinic and cubic phases at an intermediate RF power. To ensure the electrical characteristics of the grown dielectric we present a metal oxide semiconductor capacitor structure fabrication for the monoclinic and the cubic Gd 2 O 3 layers and benchmark the interface trap density, and dielectric constant against state-of-the-art literature. We show an improvement in the interface trap density, and reduction in the hysteresis from monoclinic to cubic phase transition due to an improved epitaxial relation between cubic Gd 2 O 3 and Si(111) substrate. Such low-cost methods of growing single-crystalline Gd 2 O 3 layer has the potential to replace the SiO 2 BOX layer, and significantly bring down the manufacturing cost of the existing SOI wafer technology. [ABSTRACT FROM AUTHOR]

Subwavelength grating (SWG) metamaterials have garnered a great interest for their singular capability to shape the material properties and the propagation of light, allowing the realization of devices with unprecedented performance. However, practical SWG implementations are limited by fabrication constraints, such as minimum feature size, that restrict the available design space or compromise compatibility with high-volume fabrication technologies. Indeed, most successful SWG realizations so far relied on electron-beam lithographic techniques, compromising the scalability of the approach. Here, we report the experimental demonstration of an SWG metamaterial engineered beam splitter fabricated with deep-ultraviolet immersion lithography in a 300-mm silicon-on-insulator technology. The metamaterial beam splitter exhibits high performance over a measured bandwidth exceeding 186 nm centered at 1550 nm. These results open a new route for the development of scalable silicon photonic circuits exploiting flexible metamaterial engineering. [ABSTRACT FROM AUTHOR]