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• The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for devices with different channel lengths and fin widths. • The temperature rise increases the current due to GIDL and its dependence on the device width. • For a fixed negative gate voltage the channel length reduction increases the GIDL current for nanowires independent of the temperature, except for devices suffering from threshold voltage roll-off due to short-channel effect. • Three-dimensional TCAD simulations showed that drain leakage is mainly composed of band-to-band tunneling rather than junction leakage, even at high temperatures. • The band-to-band generation rate intensity is larger in the bottom nanowire, with Ω-gate architecture than in the top GAA nanowire. • Band-to-band generation becomes higher as length is reduced and fin width is increased and is larger in the drain extension and gate overlap regions. • The temperature rise changes valence and conduction energy levels causing the reduction of the lateral distance between the two levels, favoring the transversal band-to-band tunneling. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling. [ABSTRACT FROM AUTHOR]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]