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This paper presents folded cascode Low Noise Amplifier (LNA) designed for Wireless Local Area Network (WLAN) applications. The proposed LNA uses complementary current reuse technique and diode connected forward body biasing technique to lower the power consumption and boost the transconductance for gain enhancement. Moreover, post linearization is done by P-MOS (Metal Oxide Semiconductor) Inter Modulation Distortion (IMD) sinker which reduces inter modulation distortion present at the input and achieves better linearity of the LNA. Under cadence virtuoso environment, using 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology, the designed LNA exhibit high gain (S21) of 25.4 dB followed by noise figure of 1.75 dB at a reduced supply voltage of 0.6 V. The other important parameters including reflection coefficient (S11) − 12 dB, power dissipation (Pdc) 3.23 mW and Third order Input Intercept Point (IIP3) − 4.43 dBm are also achieved. This demonstrates the applicability of proposed LNA for wireless applications functioning in 5.2 GHz. [ABSTRACT FROM AUTHOR]

Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain's response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation. [ABSTRACT FROM AUTHOR]

This paper presents a low-noise amplifier (LNA) with an integrated input and output matching network designed using RF-SOI technology. This LNA was designed with a resistive feedback topology and an inductive peaking technology to provide 600 MHz of bandwidth in the N79 band (4.4 GHz to 5.0 GHz). Generally, the resistive feedback structure used in broadband applications allows the input and output impedance to be made to satisfy the broadband conditions through low-impedance feedback. However, feedback impedance for excessive broadband characteristics can degrade the noise performance as a consequence. To achieve a better noise performance for a bandwidth of 600 MHz, the paper provided an optimized noise performance by selecting the feedback resistor value optimized for the N79 band. Additionally, an inductive peaking technique was applied to the designed low-noise amplifier to achieve a better optimized output matching network. The designed low-noise amplifier simulated a gain of 20.68 dB and 19.94 dB from 4.4 to 5.0 GHz, with noise figures of 1.57 dB and 1.73 dB, respectively. The input and output matching networks were also integrated, and the power consumption was designed to be 9.95 mA at a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs. [ABSTRACT FROM AUTHOR]

This paper presents a 30–36 GHz limiter low‐noise amplifier (limiter‐LNA) MMIC for high power and high mobility millimeter‐wave radar systems. The PIN‐diode limiter network and the LNA are codesigned to realize high input‐power handling capability, good small‐signal performance, and small chip area. A two‐state matching capacitor is presented to improve both the input‐power handling capability at the high input‐power level and the input return loss at the small‐signal level. The proposed circuit is fabricated with a combined PIN/0.15‐µm‐GaAs‐pHEMT process. The limiter‐LNA is capable of handling 39 dBm continuous wave (CW) input‐power without failure with only two limiter stages. The measured noise figure is 1.8–2.5 dB, the small‐signal gain is 18.5 ± 0.5 dB, the output power at 1 dB compression point is larger than 11 dBm, and the dc power consumption is 72 mW. The chip area, including testing pads, is only 2.1 mm × 1.0 mm. This limiter‐LNA MMIC is believed to have the highest input‐power handling capability and smallest chip area among limiter‐LNA MMICs at this frequency range reported up to date. [ABSTRACT FROM AUTHOR]

This paper presents the design, development, and performance evaluation of a compact wideband phased array active helical antenna for monitoring HF interference. Traditional multi-element HF antenna designs are often subjected to size restrictions. The front-to-back ratio of the proposed circularly polarized phased array exceeds 20 dB across the operating range. This array enables the simultaneous monitoring of vertically and horizontally polarized signals, offering a practical alternative to larger antennas, particularly in space-constrained scenarios. Through advanced low-noise amplifier design, efficiency and bandwidth are optimized while mitigating mutual coupling effects. Optimal beamformer design enhances array performance with respect to more traditional array design approaches. The test results verify exceptional performance with an average axial ratio of 2 dB and a high front-to-back ratio beyond the desired frequency range. This study offers valuable insights into the design and deployment of compact wideband phased array antennas, providing an effective solution for monitoring HF interference. [ABSTRACT FROM AUTHOR]

A broadband differential-MMIC low-noise amplifier (DLNA) using metamorphic high-electron-mobility transistors of 70 nm in Gallium Arsenide (70 nm GaAs mHEMT technology) is presented. The design and results of the performance measurements of the DLNA in the frequency band from 1 to 16 GHz are shown, with a high dynamic range, and a noise figure ( N F ) below 1.3 dB is obtained. In this work, two low-noise amplifiers (LNAs) were designed and manufactured in the OMMIC foundry: a dual LNA, which we call balanced, and a differential LNA, which we call DLNA. However, the paper focuses primarily on DLNA because of its differential architecture. Both use a 70 nm GaAs mHEMT space-qualified technology with a cutoff frequency of 300 GHz. With a low power bias V b i a s / I b i a s (5 V/40.5 mA), N F < 1.07 dB "on wafer" was achieved, from 2 to 16 GHz; while with the measurements made "on jig", N F = 1.1 dB, from 1 to 10 GHz. Furthermore, it was obtained that N F < 1.5 dB, from 1 to 16 GHz, with a figure of merit equal to 145.5 GHz/mW. Finally, with the proposed topology, several LNAs were designed and manufactured, both in the OMMIC process and in other foundries with other processes, such as UMS. The experimental results showed that the N F of the DLNA MMIC with multioctave bandwidth that was built in the frequency range of the L-, S-, C-, and X-bands was satisfactory. [ABSTRACT FROM AUTHOR]

The design of ultra-wide-band (UWB) low-noise amplifiers (LNAs) entails a large number of design challenges and tradeoffs, which include sustaining good input matching over a wide bandwidth along with finding a proper compromise between various LNA performance metrics, such as gain, bandwidth, noise figure, power, and linearity. This paper presents a design approach for UWB LNAs based on the inversion coefficient (IC). The proposed approach is a graphical design approach where the proper operating point is chosen based on predefined constraints. A complete systematic solution is presented for the problem of UWB input matching with a high degree of analytical accuracy. The design approach is illustrated through the design of two UWB stacked common-gate LNAs in 65 nm technology. The post-layout simulation results show very good agreement with analytical expectations. The first LNA achieves an S 11 better than −8.2 dB over a 27.6 GHz frequency range, a gain of 12.4 dB over a 16.5 GHz bandwidth, a minimum noise-figure, NF, of 4.5 dB, and an I I P 3 of −5.2 dBm while consuming only 530 μ W. The second LNA achieves an S 11 better than −15 dB over an 8.8 GHz frequency range, a gain of 12.5 dB over a 6.8 GHz bandwidth, a minimum NF of 4 dB, and an I I P 3 of −4.3 dBm while consuming only 550 μ W. [ABSTRACT FROM AUTHOR]

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26–28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V. [ABSTRACT FROM AUTHOR]

Low-noise fluxgate magnetometers are normally comprised of three separate devices: a power supply, the sensor head/electronics and an analog-to-digital converter (ADC). This paper presents a parallel rod fluxgate magnetometer in a single printed circuit board of size = 5 × 12 cm, weight = 45 g, and sensor head average power dissipation = 40 mW. The open-loop noise spectral density = 5 p T r m s / Hz @ 1 Hz , competitive with state-of-the-art devices. This is realized using a new amorphous wire core material and programmable mixed-signal electronics with low amplifier and ADC noise. We have compared the sensor performance to a low-noise observatory magnetometer and found sub-nT correlation when tracking the Y (East-West) component of the Earth's geomagnetic field. [ABSTRACT FROM AUTHOR]

This paper updates the development of a warm front-end electronics (WFEE) dedicated to cryogenic sensors readout. It belongs to the X-ray integral field unit instrument of ESA's future space observatory: ATHENA. This instrument integrates cryogenic elements such as 3168 transition edge sensors as detectors, multiplexed into 96 channels using time-division multiplexing (TDM). One TDM channel will be read out by two stages of superconducting quantum interference device (SQUID), followed by a WFEE and finally, a digital readout system, both two last stages operating at about 300 K. In the WFEE, 96 TDM channels will be distributed in 48 application-specific integrated circuits (ASIC). Each channel includes one low-noise amplifier to amplify the multiplexed signal and 5 configurable current sources to bias the SQUIDs and TES in the cryogenic stages. Additionally, two channels within the same ASIC share a serial bus "RS485/I 2 C" to configure the current sources (current SlowDACs) and housekeeping elements that monitor the temperature, current and voltage of the ASIC. The ASIC presented in this paper, "AwaXe_v3" (AwaXe: Athena Warm Asic for the X-ifu Electronics), is developed for the WFEE using an AMS 350 nm SiGe BiCMOS technology. It is the first prototype of the WFEE integrating two complete TDM channels. Representative measurement results that characterise the main components of the WFEE will be discussed in this paper as an update on the use of ASIC for the TES/SQUID readout. [ABSTRACT FROM AUTHOR]

Summary: Wideband low‐noise amplifiers (LNAs) are widely used in 5G and 6G communication systems. This paper first analyzes two common bandwidth extension technologies: the stagger tuning technique and the magnetically coupled resonators (MCR) technique. Then, a four‐stage LNA based on double‐tuned transformer combined with stagger tuning idea and MCR idea was proposed. In order to improve the broadband characteristics of the LNA, the loose coupling double‐tuned transformer is carefully designed. Compared with the traditional stagger tuning LNA, it has better broadband characteristics, lower element error sensitivity, and lower design complexity. This designs a gain bandwidth product of 1.48 T with a −3‐dB bandwidth in 9.11 GHz and the noise factor is lower than 3 dB, which covers more than 45% −3‐dB fractional bandwidth. The LNA consumes 37‐mW power with a 1.1‐V supply and occupies 1.22 × 0.4 mm2. [ABSTRACT FROM AUTHOR]

The small current detection circuit is the core component of the accurate detection of the nanopore sensor. In this paper, a compact, low-noise, and high-speed trans-impedance amplifier is built for the nanopore detection system. The amplifier consists of two amplification stages. The first stage performs low-noise trans-impedance amplification by using ADA4530-1, which is a high-performance FET operational amplifier, and a high-ohm feedback resistor of 1 GΩ. The high pass shelf filter in the second stage recovers the higher frequency above the 3 dB cutoff in the first stage to extend the maximum bandwidth up to 50 kHz. The amplifier shows a low noise below sub-2 pA rms when tuned to have a bandwidth of around 5 kHz. It also guarantees a stable frequency response in the nanopore sensor. [ABSTRACT FROM AUTHOR]

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13 μ m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2 W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28 dB with an NF about 2.3 dB and an IP1 dB above − 14 dBm. The state error of attenuator is less than + ∕ − 0. 6 dB with step error less than + ∕ − 0. 3 dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of 5 × 5. 6 mm2. This receiver draws only 128 mA with a 3.3 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 n V / H z @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 (( µ V / H z )·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode. [ABSTRACT FROM AUTHOR]

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5–8 GHz band, with a chip area of 1.56 × 1.46 mm2. Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process. [ABSTRACT FROM AUTHOR]

This paper presents the design of a low-noise amplifier (LNA) with a bypass mode for the n77/79 bands in 5G New Radio (NR). The proposed LNA integrates internal matching networks for both input and output, combining two LNAs for the n77 and n79 bands into a single chip. Additionally, a bypass mode is integrated to accommodate the flexible operation of the receiving system in response to varying input signal levels. For each frequency band, we designed a low-noise amplifier for the n77 band to expand the bandwidth to 900 MHz (3.3 GHz to 4.2 GHz) using resistive–capacitance (RC) feedback and series inductive-peaking techniques. For the n79 band, only the RC feedback technique was employed to optimize the performance of the LNA for its 600 MHz bandwidth (4.4 GHz to 5.0 GHz). Because wideband techniques can lead to a trade-off between gain and noise, causing potential degradation in noise performance, appropriate bandwidth design becomes crucial. The designed n77 band low-noise amplifier achieved a simulated gain of 22.6 dB and a noise figure of 1.7 dB. Similarly, the n79 band exhibited a gain of 21.1 dB and a noise figure of 1.5 dB with a current consumption of 10 mA at a 1.2 supply voltage. The bypass mode was designed with S21 of −3.7 dB and −5.0 dB for n77 and n79, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier's total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13. [ABSTRACT FROM AUTHOR]

There is a continuously evolving, unmet need for RF (Radio Frequency) Filters that operate contiguously over multiple frequency octaves or bands. Unlike traditional switched filter banks, these new filters require similar levels of RF performance but with more filters and a smaller overall footprint. Legacy systems typically operate over a sub-octave and filters meant to break down information from the aperture to sub-bands (octave wide) or a little less. These wideband filters, pre-LNA (low noise amplifier), were minimal loss but very large. This paper will examine two new solutions to miniature, wideband, and contiguous filtering, their different capabilities, and where the new filter technologies can enable new overall system capabilities. The commercial (cell phone) vs DoD (Department of Defense) requirement differences which drive very different needs for RF filters highlight the SWAP-C (Size, Weight, and Power - Cost) challenge as wideband, contiguous vs. not, is considered. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a broadband superheterodyne receiver (RX) front‐end for millimeter‐wave (mm‐Wave) imaging radar is presented. Realized in 28‐nm CMOS technology, the proposed RX incorporates a wideband low‐noise amplifier (LNA), double‐balanced passive mixers for the dual down‐conversion, a differential power divider, a differential intermediate frequency filters, a current‐mode‐logic divider‐by‐2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four‐stage LNA is devised to realize the high gain and low noise figure (NF) with a common‐gate input stage and three pseudodifferential common‐source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer‐based matching networks with the peak‐staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double‐balanced mixers are implemented with a highly symmetrical layout for broadband down‐conversion. Simulation results show that the mm‐Wave RX front‐end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2‐mW power and occupies a chip size of 1.6 × 0.5 mm2 including all the testing pads. The proposed RX is suitable for W‐band imaging systems. [ABSTRACT FROM AUTHOR]

This paper studies how nonlinear distortion is generated in the combination of an inverter-based low-noise amplifier and a passive mixer. The dominant nonlinearity appears to be the quadratic V gs V ds mixing term in the passive mixer that first causes low-frequency IM2 and then upconverts it to IM3. Adding a common-mode feedback (CMFB) cancels the IM2 in a pseudo-differential structure, and hence also reduces the IM3 caused by the cascaded second order nonlinearities significantly. The effect of CMFB gain, bandwidth and linearity were analyzed, and it is concluded that from the linearity point of view, the feedback circuit does not have to be very wideband since the dominant distortion products originate from baseband. Finally, the paper takes a look at the spurious tones rising in the mixing, and how to extend the analysis to include the actual frequency translation effect. [ABSTRACT FROM AUTHOR]

With the rapid and continuous development of nanomanufacturing technology, the demands for both large range and high precision metrology of structured surfaces are becoming increasingly urgent. This paper proposes a metrological measurement system based on a commercial atomic force microscope. By using the nano-positioning platform from SIOS, the measurement range of the system expands from 110 μm × 110 μm × 20 μm to 25 mm × 25 mm × 5 mm. A signal amplifier with low noise and a high common mode rejection ratio that decreases the noise level of the measurement system to 2 nm is designed. Integration of the metrological system, signal processing, and calibration of the whole system is introduced. Three experimental studies are carried out on an ultrahigh step, an atomic deposition grating, and a cutting tool. The experimental results demonstrate high measurement repeatability and reproducibility in both vertical and lateral directions. By repeating 10 times of measurement, the expended uncertainties of the step and the grating measurement are 36.24 nm and 0.60 nm, respectively. Additionally, measurement of a cutting tool tip is conducted to illustrate the performance of the system. The Ra and Rz values of the tool tip arc ripple are 29.8 nm and 189 nm, respectively. [ABSTRACT FROM AUTHOR]

In this paper, design of erbium-doped fiber amplifiers (EDFA) based 16 channel wavelength-division multiplexing (WDM) system for different pump powers and input signal levels using counter propagating pumping scheme is reported. Wavelength range between 1548 and 1560 nm in C-band with channel spacing of 0.75 nm at a bit rate of 10 Gbps are used. Input power given to all the channels is taken between −20 and −35 dBm with 3 dBm variation. Pump power levels between 100 and 500 mW at 980 nm wavelength are used. Low gain flatness with high gains and low noise figures are achieved with the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents the design strategy of a microwave low noise amplifier (LNA) in microstrip technology for sub-6 GHz 5G communication systems. A microstrip coupler is exploited to design a DC block in order to avoid unwanted parasitic effects generated by lumped elements and to facilitate fabrication. Bias and matching networks are implemented using microstrip transmission lines. Based on the designed circuit, a prototype is fabricated and measured using an Agilent Technologies (hp)® ATF13786 field effect transistor. The proposed LNA is simulated and measured at 3.5 GHz. The results demonstrate that the proposed LNA achieves high gain of 12.7 dB, noise figure less than 2 dB, input and output reflection coefficients less than –10 dB, and unconditional stability over the desired bandwidth. Regarding the large signal results, the proposed LNA yields excellent performance with an output power of 16.4 dBm, and a power added efficiency (PAE) of 18%. Furthermore, the proposed LNA exhibits good linearity with an output compression point at 1 dB (OP1dB) of 0 dBm, and a third-order intercept point (OIP3) greater than +37.7 dBm. [ABSTRACT FROM AUTHOR]

This paper presents a low noise amplifier (LNA) for nonlinear radar applications combined with a composite right-handed and left-handed (CRLH) filter, a type of metamaterial. The proposed LNA consists of an input matching network, output matching network, and a CRLH filter combined. The LNA with a CRLH filter has advantages of broadband, low noise, and high frequency selectivity. It filters the harmonic frequency resulting in broadband operation and has a flat S-parameter value with a gain of more than 10 dBm in a wideband ranging from 4 GHz to 8 GHz. The noise figure value was measured at 1.521 dB and 1.682 dB at 4 GHz and 8 GHz, respectively, and 1.542 dB at 6 GHz, in middle frequency. [ABSTRACT FROM AUTHOR]

This paper discusses the design of a 4.4∼5.0 GHz low-noise amplifier (LNA) using a 0.5-μm GaAs pHEMT process. The transistor size was optimized to address the mismatch between optimal noise and input impedance owing to the unique noise sources of the transistor and parasitic characteristics, achieving a low noise figure with high input and noise optimal impedance matching without additional inter-stage loss components. The designed low-noise amplifier consumed 48 mW of power in the 4.4∼5.0 GHz range, demonstrating more than 23 dB of gain and a low noise figure of less than 0.9 dB. The size of the fabricated circuit was 1.8×1.4 mm². [ABSTRACT FROM AUTHOR]

In the paper, a wideband miniaturized impedance-transforming quadrature four-feed network with a flat output phase difference is presented and applied to the design of an active integrated GNSS antenna where no extra impedance matching circuit is needed. The features of impedance transformation and flat output phase difference are achieved by the proposed miniaturized rat-race coupler. When combining the proposed rat-race coupler with two trans-directional (TRD) couplers, a four-feed network with stable sequential quadrature phase shifts is obtained in the whole GNSS band. Since the quadrature four-feed network has the feature of impedance transformation, integration with a low-noise amplifier (LNA) can be realized without extra impedance matching circuits, which reduce the overall size and losses. For validation, a simple rectangular patch is applied as the radiator, and the active prototype is fabricated. Measurement results show that over the entire GNSS band from 1.164 GHz to 1.610 GHz, the miniaturized integrated antenna exhibits a return loss of more than 10 dB, an axial ratio of less than 3 dB axial ratio, and a gain of greater than 16 dBic. [ABSTRACT FROM AUTHOR]

This paper proposes a design of a 38 GHz Low Noise Amplifier (LNA) that uses a three-stage common source inductive degeneration topology with a gain of 27 dB and noise figure of 1.78 dB using 0.1 µm GaAs pHEMT as an active device. The novelty of the design is the usage of inductive load in series with the resistor instead of resistive load, resulting in higher gain performance. A recent pp1010 active device of WIN foundry was explored for this LNA design at the Q band. The high transition frequency offered by this technology succeeded in obtaining competitive results with a minimum number of cells. The designed LNA obtained the lowest noise compared to other recently published LNA designs at the Q band. The total power consumption of this design is 57 mW. [ABSTRACT FROM AUTHOR]

This paper proposes a low-noise amplifier (LNA) for terahertz communication systems. The amplifier is designed based on 90 nm InP high-electron-mobility transistor (HEMT) technology. In order to achieve high gain of LNA, the proposed amplifier adopts a five-stage amplification structure. At the same time, the use of staggered tuning technology has achieved a large bandwidth of terahertz low-noise amplification. In addition, capacitors are used for interstage isolation, sector lines are used for RF bypass, and Microstrip is used to design matching circuits. The entire LNA circuit was validated using accurate electromagnetic simulation. The simulation results show that at 140 GHz, the small signal gain is 25 dB, the noise figure is 4.4 dB, the input 1 dB compression point is −19 dBm, and the 3 dB bandwidth reaches 60 GHz (110–170 GHz), which validates the effectiveness of the design. [ABSTRACT FROM AUTHOR]

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In this paper, a modified compensated matching method for designing a low-noise broadband microwave amplifier with guaranteed stability is proposed. Compensated matching method is formulated as an optimization problem. A hybrid optimization algorithm based on the combination of the genetic algorithm and conjugate gradients method is used to the design of the low-noise stable broadband RF amplifier. The new hybrid algorithm obtains low-noise figure, gain flatness, stability, and loss factor correlated with each reactive element and matching network accomplishment included. An 8-16 GHz broadband microwave amplifier is designed to verify its application. This paper shows that a hybrid technique improves the accuracy of the design and speeds up the design procedure significantly. [ABSTRACT FROM AUTHOR]

Summary: Cascode HEMTs exhibit high gain and broadband performance. Promising reverse transmission makes matching networks simpler and insensitive to impedance on either side of the HEMT. On the other hand, common source (CS) HEMTs with intentional small inductance at the source provide simultaneous match for optimum noise and input impedance. This paper provides a performance comparison of 4×50 μm cascode HEMTs‐based low‐noise amplifier and 4×50 μm CS HEMTs‐based low‐noise amplifiers with specific emphasis on robustness, including survivability and reverse recovery time (RRT). Cascode LNA survives an input power of 33 dBm while CS LNA handles 30 dBm power, each having a 1 k Ω passive limiting resistor on the gate bias line. RRT of cascode LNA is also better. Better survivability and RRT for cascode LNA are attributed to its HEMT's stacked configuration. The designs of LNAs are described, along with their small‐signal, noise, and large‐signal characteristics in the X‐band. Cascode LNA has a better input match, while CS LNA has a better output match. Gains are comparable, while CS LNA has better P1dB at higher band edge frequency. The noise figure for both LNAs is less than 1.9 dB, with CS LNA having a slight edge over cascode. This study benefits RF designers in choosing appropriate HEMT topology as per application for designing robust low‐noise amplifiers. [ABSTRACT FROM AUTHOR]

Accurate location information is crucial for ensuring the reliability of service robots, such as field vehicles and agricultural robots. These practical robots often encounter fluctuating or inclined terrains in dynamic conditions during operation. Additionally, the performance of mobile robots depends on the physical size and weight of the localization system–physically heavy systems may degrade performance. In this paper, we present a compact, lightweight RTK‐GNSS device weighing under 40 g, which achieves centimeter‐level accuracy across different attitudes and dynamic situations. To enhance signal reception and positioning performance, we lessen noise levels in the power circuit and radio‐frequency signal conditioning using a low‐dropout regulator and low‐noise amplifier. Utilizing the configured device, we verified centimeter‐level accuracy through experiments of tracking an unmanned ground vehicle. The potential of the device is substantiated via three application scenarios—a localization of a moving human for a wearable device, a heading estimation of a mobile robot in stationary conditions, and practical field tests in various signal‐reception environments. Attributable to its compact dimensions and lightweight features, the proposed device can yield a low system strain while maintaining high accuracy and reliable performance, rendering it highly adaptable for various robotic applications. [ABSTRACT FROM AUTHOR]

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design's novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 μ W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/ (H z) at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition. [ABSTRACT FROM AUTHOR]

The Center for Axion and Precision Physics Research at the Institute for Basic Science in Republic of Korea is home to multiple active axion search experiments using cavity haloscopes that operate within the frequency range of 1–6 GHz. The haloscopes convert axions to photons, resulting in an output power of about 10 - 24 –10 - 22 W. To detect such a small signal amidst noise, quantum-limited noise amplifiers and ultra-low-temperature environment (a few tenths of mK) are required for all critical readout components to minimize noise from all active and passive lossy components. Our primary objective is to achieve the highest possible scanning-frequency speed, which includes the time for maintenance and system calibration. This paper presents the development and operation of low-noise amplifiers for haloscope experiments targeting different frequency ranges and provides design, operational, and performance details of the amplifiers. [ABSTRACT FROM AUTHOR]

This paper presents an overview of the different types of low noise amplifiers (LNAs) at 2.4 GHz frequency and the design of a single-stage inductive degenerated commonsource narrow-band low-noise amplifier with a current reuse technique. The CLC with current reuse at the source forms an input-matching configuration in the common source input stage. Because of the CLC circuit used, the LNA achieved impedance matching between the source and the input of the LNA. The current reuse technique used here ensured an enhanced gain. The low noise amplifier simulated in Cadence Virtuoso 180 nm library achieved a gain of 23.06 dB with a noise figure of 0.15 dB. The S11 is -17.17 dB, S22 is -16.4 dB and S12 is at -45.5 dB. The power consumed is 5 mW and has unconditional stability with a stability factor kf of 6.8. Corner analyses validate the stability of the circuit despite variations in process, voltage, and temperature (PVT). The layout of the circuit leaves a footprint of 1.2mm x0.83mm. [ABSTRACT FROM AUTHOR]

This paper presents a new approach of the design of a W-band low noise amplifier (LNA) in a 0.13 µm CMOS technology for narrowband and wideband applications. The proposed LNA utilizes input matching bandwidth extensions based on the source degeneration topology, and it is designed and optimized at a center frequency of 94 GHz and a supply voltage of 1.2 V. The obtained results exhibit a noise figure of 3 dB, a power gain of 32 dB, and a VSWR of 1.1. The design technique of this LNA is based on an agreeable tradeoff between the available gain of 30 dB and the noise figure of 3 dB, which leads to good bilateral stability and high linearity described by an input third-order intercept point of -17 dBm. A detailed performance analysis is presented and discussed along this paper. With the aim of a complete and robust integration, all lumped elements and transmission lines are integrated on a silicon PCB having ɛr = 11.7 and a dielectric loss TanΔ = 0.001 for low manufacturing costs. The prominent results of this LNA indicate that it is suitable for 94 GHz-image-radar and RFIC-5G mobile systems. [ABSTRACT FROM AUTHOR]

This paper presents a V‐band digitally controlled low noise variable gain amplifier (LNVGA) in 28‐nm bulk CMOS process. The amplifier includes three stages and the first stage is used to realize wideband high gain and low noise figure (NF). The gain control is implemented in the second and third stages with current steering and split cascode topology, respectively. A source degeneration inductor and a series inductor are introduced to reduce the phase variation in the second stage. The phase response function is analyzed, and the phase reduction of 1.2° is achieved. Moreover, with the combination of these two different topologies, the phase variation can be further reduced. The measurement results show the LNVGA has a peak gain of 16 dB with a 3‐dB bandwidth of 45–59 GHz. The measured gain control range is 0–16 dB in 16 different gain states and the minimum phase variation is 3.5° with power consumption of 23 mW. [ABSTRACT FROM AUTHOR]

This paper presents a 28 GHz GaN enhanced single‐sideband time‐modulated phased array (ESTMPA), based on a monolithic microwave integrated circuit (MMIC), including both a time‐modulated circuit and an RF front‐end module (FEM). The time‐modulated circuit mainly consists of a numerically controlled attenuator to balance the amplitude, compact phase shifters to generate balanced signals, a reconfigurable power divider, and a quadrature power divider. The FEM mainly consists of a low noise amplifier and a power amplifier, featuring codesign of input/output networks. Based on the in‐phase/quadrature (I/Q) composite modulation technique, a stepped modulation waveform, realized by the time‐modulated circuit, is used to enable a weighted array of phases. This helps generate a scanned beam at the first positive sideband and eliminate the undesired sidebands. The final MMIC‐based four‐element ESTMPA shows a relative suppression level of −16 dB at the positive fifth sideband and −13 dB at the zeroth sideband, and a much higher level at the other undesired sidebands. As a result, a wider signal bandwidth and a higher harmonic efficiency are achieved. In addition, the ESTMPA shows a beam sweeping angle from −30° to 30° in far‐field measurement. [ABSTRACT FROM AUTHOR]

A fully integrated low-power area-efficient receiver using a low–intermediate frequency topology for BDS-3 and GPS L1 bands is presented in this paper. Accurate localization can be achieved without requiring off-chip low-noise amplifiers. The receiver bandwidths for GPS and BDS-3 are 2 MHz and 4 MHz, respectively. Digitally assisted calibration schemes, such as RC calibration, automatic gain control, and DC offset correction are integrated to resist the effects of the process, voltage, and temperature (PVT) variations. The receiver—fabricated in a standard 55 nm CMOS technology—provides a maximum gain of 113.2 dB, a gain control range of 61 dB, and a minimum noise figure of 1.74 dB under a 1.2 V supply. The receiver, with and without the frequency synthesizer that provides the local oscillator frequency, consumes 8.7 mA and 4.8 mA, with areas of 0.73 mm2 and 0.345 mm2, respectively. [ABSTRACT FROM AUTHOR]

The backward Raman amplifier (RA) can considered as one of the best solutions for optical communication, especially in Wavelength Division Multiplexing technology. They reduce the nonlinear effects, have low noise figure and a wide frequency range. The work in this paper aims to reduce the attenuation of optical signal due to its propagation optical fiber and increase both amplifier gain and output signal power. Two backward Raman models are proposed. Proposal one model consists of two cascaded RAs and the other (proposal two) consists of three cascaded RAs. Three backward pump power levels 200, 400, and 600 mW are used to simulate the models with the three types of fibers: single-mode fiber, Truewave, and Freelight, at an amplifier length of 100 km. Proposal two achieves a maximum gain of 31 dB at 600 mW pump power 600 mW using Truewave optical fiber, with 27.7 dBm maximum output signal power. This proposal is evaluated showing 11.15% gain enhancement and 200 mW saved power when compared to previously published work. [ABSTRACT FROM AUTHOR]

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor's Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed. [ABSTRACT FROM AUTHOR]

The presence of RF components in mixed-signal circuits make it a challenging task to resolve tradeoffs among performance specifications. In order to ease the process of circuit design, these tradeoffs are being analyzed using multi-objective optimization methodologies. This paper presents a hybrid multi-objective optimization framework (MHPSO), a combination of particle swarm optimization and simulated annealing. The framework emphasizes on preserving nondominated solutions in an external archive. The multi-dimensional space excluding the archive is divided into several sub-spaces according to a velocity-temperature mapping scheme. Further, the solutions in each sub-space are optimized using simulated annealing for generation of a Pareto front. The framework is extended by incorporating crowding distance comparison operator (MHPSO-CD) to maintain nondominated solutions in the archive. The effectiveness of proposed methodologies is demonstrated for performance space exploration of three electronic circuits, i.e., a two-stage operational amplifier, a folded cascode operational amplifier, and a low noise amplifier with inductive source degeneration. Additionally, the performance of proposed algorithms (MHPSO, MHPSO-CD) are evaluated on various test functions, and the results are compared with standard multi-objective evolutionary algorithms. [ABSTRACT FROM AUTHOR]

Copyright of Journal of South China University of Technology (Natural Science Edition) is the property of South China University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) that is compatible with n257 (26.5–29.5 GHz) and n258 (24.25–27.5 GHz) frequency bands for fifth-generation mobile communications system (5G) and millimeter-wave radar. The total circuit size of the LNA is 2.5 × 1.5 mm2. To guarantee a trade-off between noise figure (NF) and small signal gain, the transmission lines are connected to the source of gallium nitride (GaN)-on-SiC high electron mobility transistors (HEMT) by analyzing the nonlinear small signal equivalent circuit. A series of stability enhancement measures including source degeneration, an RC series network, and RF choke are put forward to enhance the stability of designed LNA. The designed GaN-based MMIC LNA adopts hybrid-matching networks (MNs) with co-design strategy to realize low NF and broadband characteristics across 5G n257 and n258 frequency band. Due to the different priorities of these hybrid-MNs, distinguished design strategies are employed to benefit small signal gain, input-output return loss, and NF performance. In order to meet the testing conditions of MMIC, an impeccable system for measuring small has been built to ensure the accuracy of the measured results. According to the measured results for small signal, the three-stage MMIC LNA has a linear gain of 18.2–20.3 dB and an NF of 2.5–3.1 dB with an input–output return loss better than 10 dB in the whole n257 and n258 frequency bands. [ABSTRACT FROM AUTHOR]

Deep brain stimulation (DBS) is an effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases, and has been consolidated as a first-line tool in the last two decades. Closed-loop deep brain stimulation (CLDBS) pushes this tool further by automatically adjusting the stimulation parameters to the brain response in real time. The main contribution of this paper is a low-size/power-controlled, compact and complete CLDBS system with two simultaneous acquisition channels, two simultaneous neurostimulation channels and wireless communication. Each channel has a low-noise amplifier (LNA) buffer in differential configuration to eliminate the DC signal component of the input. Energy management is efficiently done by the control and communication unit. The battery supports almost 9 h with both the acquisition and stimulation circuits active. If only the stimulation circuit is used as an Open Loop DBS, the battery can hold sufficient voltage for 24 h of operation. The whole system is low-cost and portable and therefore it could be used as a wearable device. [ABSTRACT FROM AUTHOR]