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The goal of this paper is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based HEMTs. To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several WG = 2 mm p-type GaN HEMTs with different LGD or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed-up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 kHz to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on RON compared to off-state stress. Third, by comparing the results on identical devices having shorter LGD, we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer) we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.

This paper reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk (ARW) of 0.05/h and bias instability of 0.42/h within a full scale of 300/s, making it a very promising solution for angular measurement in high-end industrial applications.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

In this paper, an evaluation of machine learning classifiers to be applied in wafer defect detection is described. The objective is to establish the best machine learning classifier for Wafer Defect Detection application. k-Nearest Neighbours (k-NN), Logistic Regression, Stochastic Gradient Descent, and Support Vector Machine were evaluated with 3 defects categories and one non-defect category. The key metrics for the evaluation are classification accuracy, classification precision and classification recall. 855 images were used to train, test and validate the classifier. Each image went through the embedding process by InceptionV3 algorithms before the evaluated classifier classifies the images.

In semiconductor foundries, wafer map defect analysis is crucial to prevent yield excursion. However, traditional manual inspection can hardly meet the high throughput demand. Deep learning based automatic defect detection shows promising efforts to achieve high accuracy and efficiency, yet the current approaches’ performance is limited by the imbalanced dataset and lack of interpretability. In this paper, we propose a Variational Autoencoder Enhanced Deep Learning Model (VAEDLM) for wafer defect imbalanced classification. It is light-weighted and effective in wafer defect pattern recognition on imbalanced dataset. It used variational autoencoder and decoder to generate similar wafer defect maps and a refined deep convolutional neural network for feature learning. We demonstrate the method using an authentic wafer map dataset, WM-811K. The performance is not only significantly improved after data augmentation, but it also beats the state-of-the art methods, reaching 99.19% accuracy, 99.10% recall, 99.23% precision, 99.96% AUC and 99.16% for F1-score. It clearly demonstrates the method’s efficacy to deal with the imbalanced defect pattern. Our study using saliency map and t-SNE further leads to enhanced interpretability.

Complementary metal-oxide-semiconductor (CMOS) image sensors have widely been used in internet of thinking (IoT) devices such as smartphones, smart watch and personal computer tablets [1] . The consumer market strongly requires higher sensitivity and higher speed image data processing to realize high functional CMOS image sensors such as three dimensionally stacked back-side-illuminated CMOS image sensors (3D-CIS) [2] . However, there are some serious technological issues in the fabrication of advanced CMOS image sensors as shown in Fig. 1 .

Rare earth (RE) doped oxides have demonstrated great potential for photonic applications and have also appeared as promising candidates for quantum memory devices and microwave to optical transducers. Here, we investigate the potential of Chemical Vapor Deposited (CVD) europium-doped Y2O3thin films on silicon as a new platform for integrated quantum devices. We aim at improving the optical properties of such thin films by carefully controlling the RE ion's environment. In particular, we study the effect of annealing post treatments and demonstrate that a significant source of broadening of the optical transition arises from interfacial reactions with the silicon substrate. We thus propose to encapsulate RE ions between undoped high-quality thick layers in order to limit the impact of interfacial reactions on their properties during thermal annealing. Using this approach, we succeeded in measuring a narrow inhomogeneous linewidth of 18 GHz and an ultra-narrow homogeneous linewidth of 5 MHz inferred from spectral hole width. These results are promising towards the use of these engineered RE doped thin films for the development of a scalable nanostructured spin-photon interface. In addition, our strategy could be applied to a large variety of oxide films for a broad range of applications. Paper published in Materials Advances.

Close integration of transducer arrays with supporting electronic circuits is essential in achieving efficient and compact ultrasound systems. An integral part of hybrid integration of 2D CMUT array to CMOS electronics is the introduction of through-glass-via (TGV) interconnects in glass substrates as an integral part of the 2D CMUT array fabrication. Micro-cracks around via locations, via discontinuity, and poor coplanarity between the vias and glass substrate are some of the challenges with laser-drilled, paste-filled copper-through-glass-via (Cu-TGV) interconnects. This study provides a detailed fabrication process for making $32\times 32$ -element 2D CMUT arrays on a composite glass substrate incorporating silicon-through-glass vias (Si-TGV) as interconnects using sacrificial release approach. On one column of a fabricated 2D CMUT array, we measured a mean resonant frequency of 5.6 MHz in air and an average device capacitance of 1.5 pF. With the introduction of a buried top electrode in the device structure, we achieved a collapse voltage of 93 V, which is considerably lower than the collapse voltage measured in our previously demonstrated 2D CMUT arrays with top electrode on top of the nitride plate. The fabricated array is flip-chip bonded on a custom-designed driving integrated circuit to demonstrate the complete system operation. We measured a peak-to-peak pressure of 1.82 MPa at 3.4 MHz, and 5 mm from the array surface in a 0.33 mm focal spot size. [2021-0101]

This paper analyzes the commonly used wafer-level S-parameter calibration methods LRRM, multiline TRL and LRM+ for the sensitivity to the thermal variation of electrical characteristics of planar calibration standards. We demonstrate that the calibration error of lumped-standard based methods can be significantly reduced by taking into account the variation of Load standard resistance over the temperature. The obtained results proved that for the evaluated commercially available calibration standards and for a given frequency range, the overall calibration error due to the temperature variation is in order of magnitude of repeatability of the manual system calibration. The proposed method can be successfully applied for different calibration substrates, temperature and frequency ranges, as well as to the in-situ calibration element.

Silicon ring resonator-based devices, such as modulators, detectors, filters, and switches, play important roles in integrated photonic circuits for optical communication, high-performance computing, and sensing applications. However, the high sensitivity to fabrication variations has limited their volume manufacturability and commercial adoption. Here, we report a low-cost post-fabrication trimming method to tune the resonance wavelength of a silicon ring resonator and correct for fabrication variations at wafer-scale. We use a Ge implant to create an index trimmable section in the ring resonator and an on-chip heater to apply a precise and localized thermal annealing to tune and set its resonance to a desired wavelength. We demonstrate resonance wavelength trimming of ring resonators fabricated across a 300 mm silicon-on-insulator (SOI) wafer to within +/-32 pm of a target wavelength of 1310 nm, providing a viable path to high-volume manufacturing and opening up new practical applications for these devices., Comment: 6 Pages, 5 figures. Accepted for publication in Journal of Lightwave Technology, 03 May 2021

Organic semiconducting polymers have opened a new paradigm for soft electronics due to their intrinsic flexibility and solution processibility. However, the contradiction between the mechanical stretchability and electronic performances restricts the implementation of high-mobility polymers with rigid molecular backbone in deformable devices. Here, we report the realization of high mobility and stretchability on curvilinear polymer microstructures fabricated by capillary-gradient assembly method. Curvilinear polymer microstructure arrays are fabricated with highly ordered molecular packing, controllable pattern, and wafer-scale homogeneity, leading to hole mobilities of 4.3 and 2.6 cm2 V−1 s−1 under zero and 100% strain, respectively. Fully stretchable field-effect transistors and logic circuits can be integrated in solution process. Long-range homogeneity is demonstrated with the narrow distribution of height, width, mobility, on-off ratio and threshold voltage across a four-inch wafer. This solution-assembly method provides a platform for wafer-scale and reproducible integration of high-performance soft electronic devices and circuits based on organic semiconductors., Though stretchable semiconducting polymers are advantageous for electronic applications requiring low cost, the low performance of patterned microstructures remains a challenge. Here, the authors realize high mobility, stretchable polymer microstructures via a capillary-gradient assembly method.

Advanced materials 34(1), 2105923 (2021). doi:10.1002/adma.202105923, Nanoporosity in silicon results in interface-dominated mechanics, fluidics, and photonics that are often superior to the ones of the bulk material. However, their active control, for example, by electronic stimuli, is challenging due to the absence of intrinsic piezoelectricity in the base material. Here, for large-scale nanoporous silicon cantilevers wetted by aqueous electrolytes, electrosorption-induced mechanical stress generation of up to 600 kPa that is reversible and adjustable at will by potential variations of ���1 V is shown. Laser cantilever bending experiments in combination with in operando voltammetry and step coulombmetry allow this large electro-actuation to be traced to the concerted action of 100 billions of parallel nanopores per square centimeter cross-section and determination of the capacitive charge���stress coupling parameter upon ion adsorption and desorption as well as the intimately related stress actuation dynamics for perchloric and isotonic saline solutions. A comparison with planar silicon surfaces reveals mechanistic insights on the observed electrocapillarity (Hellmann���Feynman interactions) with respect to the importance of oxide formation and wall roughness on the single-nanopore scale. The observation of robust electrochemo-mechanical actuation in a mainstream semiconductor with wafer-scale, self-organized nanoporosity opens up novel opportunities for on-chip integrated stress generation and actuorics at exceptionally low operation voltages., Published by Wiley-VCH, Weinheim

Monocrystalline silicon is one of the most important semiconductor materials, widely used in chip manufacturing, solar panels. Slicing is the first step in making chips and the surface quality of silicon wafers directly affects the quality of later processing and accounts for a large proportion in the chip manufacturing cost. Ultrasonic vibration assisted wire saw (UAWS) is an effective sawing process for cutting hard and brittle materials such as monocrystalline Si, which can significantly improve the surface quality of silicon wafers. In order to further study the formation mechanism of the surface morphology of single crystal silicon sliced by UAWS, a new model for prediction of wafer surface morphology in UAWS slicing single crystal silicon based on mixed material removal mode is presented and verified in this paper. Firstly, the surface model of diamond wire saw tool is established by equal probability method. Then according to the equation of transverse vibration dynamics about the wire saw with ultrasonic excitation, the trajectory equation of arbitrary abrasive particles on the surface of wire saw is derived and analyzed. Thirdly, a new model for prediction of the wafer surface morphology based on mixed material removal mode is presented, which can be used to predict the wafer surface morphology of single crystal silicon sliced by UAWS. Finally, the prediction model is verified by UAWS slicing experiment, and the effects of slicing parameters such as wire saw speed, feed speed and workpiece rotate speed on the surface quality of silicon wafer were studied. It shows that the predicted wafer surface morphology and the experimental wafer surface morphology are similar in some characteristics, and the average error between the experimental and the theoretical values of the wafer surface roughness is 11.9%, which verifies the validity of the prediction model.

Wafer map defect recognition (WMDR) is an important part of the integrated circuit manufacturing system. Although deep neural networks (DNNs) have been applied successfully in WMDR, class imbalance and lack of data with class labels affect their performance significantly. A new generative adversarial network (GAN), multi-granularity generative adversarial network (MGGAN), is proposed for wafer map augmentation and enhancement. To alleviate instability and mode collapse of traditional GANs, the lightweight convolution and a two-way information interaction of three subnetworks are considered. MGGAN consists of an auxiliary feature extractor (AFE), a generator (G) and a discriminator (D) for wafer map generation and WMDR. Firstly, a pretrained deep convolutional neural network (CNN), ResNet101, is employed as AFE to extract multi-granularity features from wafer maps. Secondly, in order to improve effectiveness of the adversarial training, a feature matching term is considered in the objective function of the feature generator to minimize the statistical difference between the real images and the generated images. Finally, MGGAN has been successfully applied to WMDR. The experiment results on an industrial dataset WM-811K demonstrate that MGGAN outperforms other typical GANs that aim to solve class imbalance problems and gains better recognition performance than those state-of-the-art DNNs on WMDR. This indicates effectiveness of MGGAN in image enhancement and generation. MGGAN obtains an accuracy of 88.02% on the original data and the pre-trained ResNet101 obtains 93.43% on the data enhanced by MGGAN.

This article presents a 140-GHz eight-element wafer-scale phased-array receiver based on intermediate-frequency (IF) beamforming with 5-bit phase and 4-bit gain control. The chip contains a shared local-oscillator (LO) multiplier chain and distribution network, active combiners, LC-based combiners, digitally tuned attenuators, for a near system-on-chip solution. A differential on-chip antenna feed (on the top metal) is electromagnetically (EM) coupled to a high-efficiency patch antenna (gold) on a 100-μm-thick quartz superstrate, and placed λ/2 (~140 GHz) apart in the horizontal and vertical directions. The 4x 2-element phased-array chip with attached quartz superstrate is wire-bonded to a printed circuit board containing IF and LO ports, and scans to ±35° in the elevation plane (E-plane). The measured channel NF is 7 dB and the array electronic gain is 27-28 dB with an RF front-end 3-dB bandwidth of 139-155 GHz and an IF bandwidth of 9.5-12.5 GHz. To evaluate the over-the-air performance, a communication link is demonstrated with 16-quadrature amplitude modulation (QAM) and 64-QAM waveforms, realizing up to 9-10-Gb/s data rates. To the best of our knowledge, this article presents the first CMOS wafer-scale phased-array receiver at 140 GHz with a low system noise figure and high data rate.

In this study, an ultrasound generation and sensing system using a femtosecond laser is developed specifically for noncontact inspection of a moving object. In the developed femtosecond laser ultrasonic system, a laser pulse source is divided into pump and probe laser pulses. Using a pump laser pulse with a subpicosecond duration, ultrasounds with ultrashort wavelengths (micrometer to tens of nanometers) are generated up to THz. Then, the resulting ultrasounds are measured using a probe laser pulse based on reflectometry at a sampling frequency of up to 1.5 THz. The developed system is used to generate and measure ultrasounds from a silicon wafer while the wafer is moving in a horizontal direction. Because of the ultrashort pulse duration of the probe and pump laser pulses, the contact time of these pluses with respect to a moving object is extremely short (subpicosecond), and the distortion of ultrasounds due to object motion is minimized. Ultrasounds are measured from the silicon wafer in both pulse-echo and pitch-catch modes, and it is validated that the ultrasounds acquired from a moving condition of the silicon wafer are in good agreement with those obtained from a stationary condition. Then, the thickness of a submicrometer coating layer deposited on the silicon wafer was successfully estimated while the silicon wafer was moving up to 20 mm/s.

We present a process for the manufacture of electron cryomicroscopy (cryoEM) specimen supports with an integrated foil–grid structure, using cryogenic vacuum evaporation (cryoEvap) and patterned electroplating on a silicon wafer substrate. The process is designed to produce a pattern of nanometre scale holes in a thin metal foil, which is attached to a pattern of micrometre scale grid bars that support it and allow handling of the millimetre scale device. All steps are carried out on a single 4 inch (100 mm) silicon wafer, without any need to handle individual grids during processing, and yield about 600 supports per wafer. The approach is generally applicable to the problem of creating a thin foil with nanometre scale features and a micrometre scale support structure; here it is used to make an all gold, HexAuFoil type design. It also allows for the addition of custom fiducial markers and patterns which aid in locating and identifying particular regions of a grid at several length scales: by eye, in an optical microscope, and in the electron microscope. Implemented at scale, this manufacturing process can supply ample grids to support the continued growth of cryoEM for determining the structure of biological molecules., Highlights • A method for manufacturing integrated cryoEM specimen supports is presented. • It is used to produce all gold, HexAuFoil type grids for motion-free imaging on 4 inch silicon wafers. • Custom fiducial markers are included in the grid design. • This method will allow scaled manufacture of supports to meet increasing demand. • The supports made improve the quality and throughput of high resolution structures determined by cryoEM.

This paper proposes an experimental-numerical hybrid method for estimating the residual stresses in a silicon wafer from the full-field deflection measurement. In the proposed method, the measured deflection distribution is approximated using regularized least-squares based on the superposition principle. Simultaneously, the residual stresses induced with the deflection are estimated. By applying the proposed method to a deflection distribution by finite element simulation, the basic principle of the proposed method is verified. Then, the proposed method is applied to the steel plate specimens mimicking a silicon wafer. The residual stresses obtained using the proposed method are compared with the results obtained using the X-ray diffraction method, and the appropriate regularization parameter is determined. Finally, the proposed method is successfully applied to the residual stress estimation of an actual silicon wafer. Because the deflection of a silicon is often measured during the inspection process, the proposed method of using the deflection to estimate the residual stresses is useful. Therefore, the proposed method is expected to be applied to the inspection process of silicon wafers.

Miniaturized, microfabricated microelectromechanical systems-based wafer probes are used here to evaluate different contact pad metallization at low tip forces (µm2) and sub-micrometre (0.6 × 0.6 µm2). The contact resistance of Au–Au, Ni–Au, Mo–Au, and Cr–Au was measured as a function of tip deflection. The tip force (loading) of the contacts was evaluated from the deflection of the cantilever. It was observed that an overtravel of 300 nm resulting in a contact force of ∼400 µN was sufficient to achieve a contact resistance 1000 Nm−1) and small contact pads enabled us to show that it is the length of the pad (in contact with the surface) which determines the contact resistivity rather than the total contact pad area.

A wafer consists of several chips, and a wafer map shows the locations of defective chips on the wafer. The locational pattern of defective chips on the wafer map provides crucial information for improving the semiconductor wafer fabrication process. Recently, automatic defect pattern classification using convolutional neural networks (CNN) has become popular because of its good classification performance. The good performance is guaranteed only when a large amount of well-balanced training and test data is available. However, such data are difficult to obtain in real practice because the training and test data are obtained by manual inspection. In this paper, we propose a systematic method to resolve the small and imbalanced wafer map data issues. Specifically, we first selected wafers showing clear defect patterns and then replicated them by randomly applying horizontal flip, vertical flip, and rotation. In the case study, we obtained real wafer map data from a semiconductor wafer company. By applying the proposed method, a large amount of well-balanced data was obtained. The CNN model for defect classification was fitted to the obtained data, and it showed good classification performance.

Heterogeneous integrated InP high electron mobility transistors (HEMTs) on quartz wafers are fabricated successfully by using a reverse-grown InP epitaxial structure and benzocyclobutene (BCB) bonding technology. The channel of the new device is In0.7Ga0.3As, and the gate length is 100 nm. A maximum extrinsic transconductance g m,max of 855.5 mS/mm and a maximum drain current of 536.5 mA/mm are obtained. The current gain cutoff frequency is as high as 262 GHz and the maximum oscillation frequency reaches 288 GHz. In addition, a small signal equivalent circuit model of heterogeneous integration of InP HEMTs on quartz wafer is built to characterize device performance.

In semiconductor manufacturing, the presence of abnormal chips in wafer products will reduce the yield of wafer products. The identification of the wafer map can find related problems in the wafer production process, and post-analysis is a necessary means to improve the wafer yield. In this study, we proposed the method that image-based multi-source and two-channel convolutional neural network for wafer map classification. This method consists of the following three main steps. First, using two different deep convolution neural networks (DCNN) to form a two-channel DCNN feature extraction model and extracting multiple sets of advanced features from multi-source data. Second, processing the multi-group data features extracted from different channels to obtain two sets of new multi-source features. Third, the multi-source features in the two channels are further processed to become a new set of classification features. Then input the new features into the combined classification model of error correction code and support vector machine (ECOC-SVM) to classify the defect pattern of the wafer map. The data used in the experiment comes from data sets in actual production (WM-811K). The experimental results showed that the proposed method has a good effect on the defect pattern recognition of wafer maps, and the effectiveness of the proposed method is confirmed. There are a total of 33,256 wafer maps, and the overall classification accuracy of 6552 test sets has reached 96.4%.

Sub-micrometer-thick lithium niobate on an insulator is a promising integrated photonic platform that provides optical field confinement and optical nonlinearity useful for state-of-the-art electro-optic modulators and wavelength converters. The fabrication of lithium niobate on insulator on a silicon substrate through ion slicing is advantageous for electronic-photonic integration but is challenging because of debonding and cracking due to the thermal expansion coefficient mismatch between silicon and lithium niobate. In this work, the fabrication of thin film lithium niobate on insulator on a silicon handle wafer is achieved, informed by structural modeling, and facilitated by accommodating for dissimilar wafer bows using a bonding apparatus. Structural finite element analysis of strain energy and stress, due to thermal expansion coefficient mismatch at elevated temperatures, is conducted. High strain energies and stresses that result in debonding and cracking, respectively, are studied through modeling and reduced by selecting optimized substrate thicknesses followed by an experimental technique to bond substrates with dissimilar bows. A lithium niobate thin film with a thickness of 800 nm is successfully transferred to an oxidized silicon wafer with a root mean square surface roughness of 5.6 nm.

We present a novel and facile scheme for fabricating wafer-scale arrays of highly uniform vertically aligned silicon nanowires (Si-NWs) in the diameter range of 50 to 200 nm. The key idea is to fabricate thin gold (Au) nanostructures using magnetron sputtering followed by de-wetting of Au and subsequent realization of wafer-scale and highly uniform Si-NWs arrays by metal-assisted chemical etching in low temperature (2 °C) without resorting to complex photolithography. The excellent properties of these Si-NWs arrays were also demonstrated numerically. A maximum exciton generation rate of 1.76 × 1024 and a maximum energy generation rate of 28 can be obtained from Si-NWs arrays with the diameter of 200 nm. The reflectivity of the Si-NWs arrays is declined with decreasing annealing temperature and is below 10% over a wide wavelength range at the annealing temperature of 200 °C. Our work provides a promising approach for constructing Si-NWs arrays with good photoelectric conversion performance.

Recently, perovskite has received extensive attention due to their excellent photoelectric properties, while the instability of perovskite quantum dots (PQDs) has always troubled us. Herein, we proposed a simple coating mechanism to protect PQDs. Using oleic acid (OA) for etching α-Al2O3 wafer to make the surface appear pore structure, and the PQDs was coated within the modified α-Al2O3 wafer, thereby improving the stability of PQDs. The CsPbX3@α-Al2O3 composite material can achieve the emission of blue-green–red (436 nm to 636 nm) through adjustable luminescence wavelength. The photoluminescence (PL) intensity of CsPbBr3@α-Al2O3 composite material exposure to the air after 28 days can maintain over 50%. It is worth noticing that the photoluminescent quantum yield (PLQY) of CsPbBrI2@α-Al2O3 composite material can reach 58%, the colour purity of CsPbBr3@α-Al2O3 and CsPbBrI2@α-Al2O3 achieve 97.1% and 99.8%, respectively. It was due to the high colour purity of the composite materials can the selected CIE colour coordinate monochromatic light encompassed 114% of NTSC colour gamut. Moreover, the warm white light-emitting diode (WLED) yielded bright natural white light and showed the luminous efficiency (LE) of 86.58 lm/W, colour rendering index (CRI) of 86.9, correlated colour temperature (CCT) of 4602 K. The LE and CRI reaches a relatively balanced value, which showed that this composite material has a certain development prospect in the WLED field.

In this article the accuracy of the LRM+ calibration is compared to that of the benchmark NIST multiline TRL procedure for the first time. The comparison is performed on NIST verified GaAs coplanar waveguide calibration reference material 8130. The NIST calibration comparison method is used to quantify the difference between measured S-parameters corrected by NIST multiline TRL and an advanced LRM+ calibration. The worst-case error bounds for LRM+ corrected S-parameter measurements are determined up to 110 GHz. It is demonstrated that the difference between benchmark multiline TRL and LRM+ is comparable with the measurement system drift. Verification results prove that LRM+ can be successfully used for accurate GaAs on-wafer calibration with customized standards. This overcomes some drawbacks of multiline TRL while providing the same calibration accuracy.

This paper addresses the background, implementation, and the on-wafer measurement results of an automatic analysis of the accuracy of S-parameters. The classic ripple-test is automated and expanded to the use of a dispersive transmission line as a reference. Consequently, it was the first time a dispersive coplanar line was used for the ripple-test. The novel technique is illustrated through a number of examples. Numerical and measurement results have verified the proposed method.

This paper proposes a new method to fabricate and evaluate Rb vapor cells sealed by two-step bonding for miniature atomic clocks. The proposed method achieves miniaturization and long-term frequency stability by the wafer-level process. First, the vapor cells are fabricated to seal only Rb atoms in vacuum to confirm the absence of residual gases. Second, the vapor cell is fabricated to seal with buffer gases to confirm the stability. The Allan deviation at an averaging time of 3000 s is 1.7 × 10−11. These results show that the proposed method has improved long-term stability compared to the vapor cell fabricated by the conventional method that uses an alkali-atom dispenser.

Although an InGaAs photo field-effect transistor (photo-FET) is a promising solution for high-performance photodetector due to its internal gain mechanism, the reported opto-electrical performance is limited by the low absorption caused by its thin body thickness and unoptimized electrical properties. To overcome this limitation, an InGaAs photo-FET with a metal gate reflector was demonstrated to achieve both high electrical and optical performance. We designed and optimized a metal-oxide-semiconductor (MOS) structure with the metal gate reflector by using numerical calculation and process optimization. Thanks to the optimization of both electrical and optical characteristics, the InGaAs photo-FETs were successfully demonstrated at the wavelengths of 1305 nm and 1550 nm. Therefore, this wafer-bonded InGaAs photo-FET with the metal gate reflector is a promising candidate for a high-performance and broad-band SWIR photodetector on a Si CMOS platform.

Si protrusions were fabricated by surface melting and resolidifying of a Si(111) wafer covered with a 100 nm thick molybdenum (Mo) layer, in which a narrow region was generated using a microgrinder. This region results in a narrow current path and thus localized resistive heating, leading to specific melting of the Si in the path. The melted Si flowed away from the path to both sides, which were at temperatures lower than that of the path. Consequently, two Si protrusions ∼400 μm in height capped with Mo silicide precipitates were formed on each side of the burned-out path, as revealed by scanning electron microscopy with energy-dispersive X-ray spectroscopy. The formation mechanism was discussed in terms of the non-uniform temperature, surface tension, interdiffusion, and freezing-point depression of the surface. This study revealed the potential of fabricating an array of self-assembled Si protrusions by resistive heating of narrow paths.

To achieve high-quality and low-cost ZnTe epitaxial films, a low-temperature (LT, 200 °C) ZnSe buffer layer with a thickness of 5 nm was grown on Si (111) wafers prior to the epitaxy of ZnTe layers by molecular beam epitaxy. Reflection high-energy electron diffraction patterns reveal that ZnTe epilayers grown at 335 °C with a thickness of 100 nm on the LT-ZnSe buffer layer present a completely two-dimensional growth mode. Film surfaces present smooth and flat morphology with the lowest surface roughness of ∼2.2 nm at a Te/Zn beam equivalent pressure ratio of 1.6. X-ray diffraction θ-2θ scanning indicates that the out-of-plane structure of ZnTe films is highly preferred with the (111) growth orientation of ZnSe/Si. X-ray diffraction φ scanning further confirms that the in-plane structure of ZnTe epilayer is also a single-crystal orientation growth. Thus, high-quality ZnTe (111) single-crystal epilayer with the lowest full-width at half-maximum of ∼200 arc sec and the smallest dislocation density of ∼1.12 × 108 cm−2 was grown on Si (111) wafers. In addition, the ZnSe buffer layer could alleviate the residual stress effectively for the heteroepitaxy of Si wafers. The most balanced residual stress for ZnTe/ZnSe/Si with σx of ∼96.5 MPa and σy of ∼94.2 MPa was obtained, which is essential for achieving high-performance and good mechanical properties of ZnTe-based devices.

Photonic crystals (PhCs) with rough surfaces can considerably enhance the formation of electromagnetic hotspots, which significantly promote surface-enhanced Raman scattering (SERS) activity. In this study, porous silicon PhCs with rough surfaces were synthesized. Deposition of gold nanoparticles on the substrate yielded a SERS substrate with good activity and reproducibility, consequently achieving the ultratrace detection of Rhodamine 6 G (R6G), with a minimum concentration of 10−15 M. The SERS activity of this substrate was simulated via finite element modeling. The experimental and theoretical results confirmed that the optical characteristics of the “black silicon,” created by inducing a rough surface, and the enhancement of the effective Raman susceptibility, or the time period of the light–matter interaction owing to photonic crystals, played an important role in the enhancement of the overall SERS activity. Furthermore, we demonstrated that the rough-surface porous silicon SERS substrate could be employed to selectively detect ultratrace military explosives containing picric acid (PA) with increased sensitivity. Accordingly, the detection limits of PA and the probe molecule R6G in the Raman spectra were 0.79 nM and 0.24 fM, respectively. This study suggests that the porous silicon PhCs with rough surfaces are promising candidates for ultratrace chemical sensing.

The dark-field defect inspection system occupies 70% of the market in the field of unpatterned wafer inspection. But the detection limit is still restrained by the haze signals. Signal-to-noise ratio (SNR) enhancement could effectively decrease the detection limit by decreasing the influence of the haze signals on the defect signals. The existing method of optimizing the inspection conditions, including beam path and collection channel, can enhance the SNR, but the effect is restrained by the system structure. The empirically designed aperture has been attempted to be used by blocking the scattering signals in a certain azimuth angle range. However, the performance is restrained, as a signal with a large SNR exists in the blocked scattering signals. In this paper, we propose a novel (we believe) aperture design method in the light of scattering field analysis to reduce the influence of the haze signals caused by the wafer surface roughness on the particle signals. On the basis of the bidirectional reflectance distribution function, apertures are designed according to the ratio field of the particle signal to haze and verified by the scattering model developed based on the tools of the National Institute of Standards and Technology. Additionally, incident conditions are optimized according to their influence on the SNR. It is noteworthy that the aperture designed under specific conditions cannot be used for all particles. Three aperture combination schemes are proposed in this paper, which can ensure the scattering characteristics such as intensity and sensitivity to meet the system requirements while improving the contrast. Simulation results verify that the detection limit decreases from 48 to 22 nm by introducing a well-designed aperture, with the case of p -polarized incident light when the threshold is 3 and the incident angle is 72°. Multiaperture schemes have better performance over others, especially the one-to-one scheme.

Carmustine was one of the first systemic chemotherapies to gain FDA approval for the treatment of brain tumors. More recently, carmustine-infused polymer wafers have been used to deliver locally higher doses of chemotherapy directly to the surgical tumor bed while obviating systemic side effects, such as myelosuppression and pulmonary toxicity.

This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

Over the last decade, lasers have been gradually employed for Si wafer dicing to replace blade dicing. Laser dicing has the potential to replace blade dicing as the future generation ultrathin wafer singulation method as it enables higher cutting speed, lower damage, and smaller kerf width but various technical challenges still remain to be resolved. In this article, laser ablation and dicing of Si wafers are reviewed in terms of the physics of laser-material interaction based on nanosecond, picosecond, and femtosecond pulse durations. The effects of various laser settings, dicing process parameters, and material factors on ablation rate, ablation precision and quality, and die fracture strength are discussed in detail. With the increasing usage of Cu stabilization layer on the backside of ultrathin Si wafers, we also review laser-material interaction in Cu and elaborate on recent findings on the effects of laser dicing through Si and Cu simultaneously on the microstructural and fracture strength properties of the die. Various approaches to improve the ablation rate, ablation quality, and die fracture strength are discussed.

Here, we report measurements made with an external vibration-insensitive single-shot interferometer, which is applicable for on-machine measurement. Previously, we developed a simple single-shot interferometry method in which the optical intensities of interference fringes appear not as sinusoidal distributions but have a sawtooth-like distribution, and the peak distortion direction depicts the slope of the measured surfaces. These properties allow use of this method in vibration-insensitive interferometry. In this study, we have experimentally confirmed this concept through measurement of a quarter of a Si wafer specimen 50 mm in diameter. The vibration source was a motorized linear stage the surface of which fluctuated between ±400 nm in height. The obtained surface profiles of the Si wafer were consistent with measurements made with a commercial interferometer within 30 nm.

This study reports a SiN x channel optical waveguide on a SiO2-covered bulk Si platform. The waveguide shows a low propagation loss of ∼0.6 dB/cm at 1550 and 1310 nm wavelengths. The SiN x film is deposited by reactive sputtering and is free from N–H species, which cause optical absorption loss at ∼1520 nm. No post-deposition high-temperature annealing is required as an increase in sputtering temperature, from room temperature to a moderate temperature of 200 °C, is effective for low-loss propagation. Based on chemical and optical analyses, the quality of the sputtered film at 200 °C is comparable to that prepared by low-pressure chemical vapor deposition at a high temperature of 820 °C. Fabricated fundamental passive optical devices (a multi-mode interferometer splitter and a directional coupler) reveal reasonable device function. A ring resonator shows a thermally stable operation because of the small thermo-optic coefficient for the SiN x , on the order of 10−5 K−1. The results indicate that the SiN x film by reactive sputtering at 200 °C can be favorably applied for photonic integration concerning CMOS back-end processing and hybrid-integration processing with non-CMOS materials. A Si-on-insulator wafer is not necessarily used as the platform, but a low-cost bulk Si wafer is replaced depending on the application. The reduction in the SiO2 under-cladding thickness, as thin as 1.0 µm, is examined regarding the potential in multilayered interconnects.

Accurate measurements of high-pressure are demanded urgently in the fields of ocean sciences, industrial controls, and oil explorations. However, conventional piezoresistive high-pressure sensors suffer from serious temperature drifts and eventually result in compromised accuracies. Herein, this paper presents a resonant high-pressure sensor with the pressure range of 30 MPa. This sensor composes of a glass wafer for vacuum package and an SOI wafer with integrated dual resonators and diaphragm structures to alleviate the temperature effect on sensor. High-pressure under measurement bends the pressure sensitive diaphragm, producing frequency shifts of suspended resonators. Finite element analyses were conducted to promote the structural strength of the sensor and optimize the pressure sensitivities and the temperature sensitivities to improve the accuracy of the sensor. Fabrication of the sensor was realized using the SOI-MEMS process. Characterization results showed the pressure sensitivities of the resonators were quantified as 0.43 kHz/MPa and 0.16 kHz/MPa with linear coefficients of 0.9999, respectively. The temperature sensitivities of the resonators were reduced from 44 Hz/°C to -1 Hz/°C. In addition, the accuracy of the sensor was higher than 0.02 %FS in the temperature range of -10°C to 60°C and the pressure range of 0.11 MPa to 5 MPa by using a polynomial algorithm. Simulative and experimental results indicate that the sensor may be a potential candidate in the field of high-pressure sensing.

We are presenting here fabrication of silicon (Si) nanowires (NWs) arrays by using Si (1 0 0) wafer as substrate, by metal assisted chemical etching (MACE) method. The Si-NWs growth on the Si wafer has been done by using etching time of 45 min in etching solution of hydrogen fluoride and hydrogen peroxide. X-ray diffraction (XRD) has been used for the structural analysis of NWs to estimate the crystalline size, micro-strain, dislocation density of fabricated nanostructures. The surface morphology of Si-NWs array has been studied through field effect scanning electron microscopy (FE-SEM). The optical properties like energy band gap of fabricated Si-NWs has been carried out through UV–Vis diffuse reflectance spectroscopy (UV DRS) and photoluminescence (PL) spectroscopy.

Monocrystalline silicon is currently one of the most used materials in the semiconductor industry. However, being hard and brittle, a silicon wafer commonly suffers from machining-induced subsurface damage (SSD). Detecting SSD is important for optimizing the machining process in order to improve the surface integrity of a machined wafer. Among the various detection methods, the polarized laser scattering (PLS) method has a huge potential in highly efficient detection. However, the surface scattering mechanism is not fully understood so far, which impedes the optimization of the PLS detection processes. This study resolves surface scattering based on the electromagnetic scattering theory. It is found that the depolarization caused by surface scattering increases with the surface roughness and the incident angle. With the consideration of the subsurface scattering characteristics and the distribution of the SSD, this study provides a solution for the PLS detection that comprises of the use of a horizontally polarized laser with vertical incidence to minimize the influence of surface scattering. This study provides a theoretical analysis of both surface and subsurface scattering to facilitate an optimized PLS detection.

A multicrystalline silicon solar cell was analyzed using Raman microspectroscopy. We measured the prominent Raman modes of silicon, nanocrystalline silicon and silver oxide in various regions of the solar cell to generate insights into the process and material quality of the finished device. First, by comparing the distribution of the transverse optical (TO) phonon peak position and full-width-at-half-maximum (FWHM) of the solar cell with a single crystal silicon wafer, the quality of the multicrystalline silicon surface was ascertained. Second, a similar analysis of the remnant saw marks on the device surface showed a discernably higher and wider distribution of TO phonon peak position and FWHM compared to a multicrystalline silicon surface. This indicated the presence of residual compressive stresses in the saw mark region. Third, by observing the silver fingers and bus bars, a residual silver oxide layer was identified, up to 25 μm away from the line edges. This was attributed to the screen printing of the silver paste and the subsequent firing process. Finally, Raman mapping on an embedded inclusion showed the presence of nanocrystalline silicon phase. The multicrystalline silicon region surrounding the inclusion was under tensile stress. A nondestructive, confocal Raman analysis of the inclusion provided a 3-D visualization of the defect, both inside and above the surface of the multicrystalline silicon wafer.

Scalable modeling and parameter extraction of the millimeter wave GaAs-based PIN diode for W-band switch design are presented in this paper. A direct-extraction method based on the S-parameters on wafer measurement is utilized to determine the extrinsic and intrinsic model parameters without any de-embedding test structures. Under turn-on and turn-off biased conditions, the modeled input reflection coefficients agree well with the measured data in the entire frequency ranges for GaAs-based PIN diode. The scalable normalization rules have been used to design W-band PIN diode switch successfully, good agreements are obtained between simulated and measured data to verify the accuracy of the proposed model.

This article presents a 96 μm x 106 μm sized single-crystalline silicon (SC-Si) /Au thermopile infrared (IR) detector, with the thermopile and IR absorber located at different layers of a double-deck micromechanical structure for improving detectivity. In order to enhance IR-heat absorption within such a tiny device size, an umbrella-shaped SiN IR absorbing membrane instead of traditional plane IR-absorbing film occupies the whole area of the top layer structure. The umbrella-shaped IR absorber is suspended on top of the IR-detecting thermopile layer, with a central umbrella-stick to support the suspending and conducting the absorbed IR-heat to the bottom thermopile layer. The bottom thermopile layer consists of six pairs of spiral-shaped SC-Si/Au thermocouples that feature several times higher Seebeck coefficient compared to the traditional polysilicon/metal thermocouples. By combining surface-micromachining technique with a specific bulk-micromachining process performed in (111) silicon wafer, the double-deck structured IR-detector is successfully fabricated only from the front side of a single (111) silicon wafer for IC-foundry compatible low-cost manufacturing. Testing results show that this device of about 100-μm scale achieves an ultrahigh IR detectivity of 1.01 x 10⁸ cm·Hz $^{{1/2}}·$ W⁻¹, which is two times improvement compared to the recently reported thermopile IR detectors, though the counterparts had larger device area. Featuring tiny size and batch fabrication capability, the proposed high-performance IR-detector is promising in both single-point detection and multipixel arrayed temperature imaging applications.

We report on SiC pn-junction diodes with a high blocking voltage over 3 kV. Although SiC radiation sensors have been developed with a Schottky barrier type due to a simple fabrication process in the early stages, pn junction structures are advantageous due to lower sensitivity of the surface defects. Thus, this system provides an ideal condition to investigate the effect of bulk crystal defects on the characteristics of the radiation sensor. The pn diodes were designed with a device simulator and fabricated with a 4-inch 4H-SiC wafer. The epitaxial layer was grown on an n-type substrate with sufficiently low doping concentration of Nd-Na =~ 5 × 1014 cm..3 and an average thickness of 52 μm. Fabricated pn diodes with a relatively large leakage current still show a clear peak of the Landau distribution in the charge spectrum, suggesting their practical availability as minimum ionizing particle detectors. The estimated electron-hole pair creation energy is consistent with the published studies and we expect good radiation tolerance. Feasibility based on the wafer processing indicates that the prototype devices are a good candidate for the muon beam monitor application in the coherent muon-to-electron transition experiment (COMET) at J-PARC.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL and attractive solution. The purpose of this paper is to review the performance improvements related to overlay and introduce edge placement error analysis for NIL. Improvements in overlay include an extension in the range for high order distortion correction and improvements in control methods such as imprint force, mask to wafer tip/tilt and wafer zone pneumatics near the wafer edge. We also introduce the pattern transfer scheme used to etch features with half pitches below 20nm.