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The document is the table of contents for the May 2024 issue of the IEEE Transactions on Semiconductor Manufacturing. It includes papers on various topics such as yield modeling, analysis, and enhancement, advanced processing, advanced process control, equipment and automation technology, non-silicon materials, emerging areas, and environment, safety, and health. The articles cover subjects such as chip-scale chemical mechanical polishing, threshold voltage deviation monitoring, curvilinear standard cell design, fabrication of silicon nanocone arrays, improving the reliability of through silicon vias, energy consumption and carbon emission reduction in HVAC systems, low-k silicon dioxide synthesis, chemical mechanical polishing of diamond epitaxial layers, conditional variable selection based on deep learning, and eco-friendly dry-cleaning and diagnostics of silicon dioxide deposition chambers. The document also includes an announcement for the call for nominations for the 2024 IEEE EDS Early Career Award. [Extracted from the article]

The "IEEE Transactions on Semiconductor Manufacturing" is a journal that publishes the latest advancements in the manufacturing of microelectronic and photonic components. It aims to enhance knowledge and improve manufacturing practices in the semiconductor industry. The journal covers various topics such as process integration, manufacturing equipment performance, yield analysis, metrology, and supply chain management. Papers submitted to the journal should focus on practical engineering techniques for solving manufacturing-related problems. The journal follows a peer-review process and encourages authors from low-income countries to submit their work. The standard length for regular papers is eight pages, and shorter contributions can be submitted as letters. The journal provides guidelines for manuscript preparation, including the use of the IEEE template style. It also accepts graphical abstracts and electronic supplements. Authors are responsible for preparing a publication-quality manuscript and may use English language editing services if needed. Plagiarism is strictly prohibited, and manuscripts found to have plagiarized content may be penalized. Authors are required to have an Open Researcher and Contributor ID (ORCID) and can submit their manuscripts online. The journal offers both traditional and open access publication options, with associated fees. Native language author names are supported, and page charges may apply for publication. The IEEE holds the copyright to the published material. [Extracted from the article]

Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process. [ABSTRACT FROM AUTHOR]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs. [ABSTRACT FROM AUTHOR]

For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (< $1 ~\mu \text{m}$), doped epitaxial SCD layers with very low (<1 nm) surface roughness are required. Conventional SCD chemical mechanical polishing (CMP) processes are insufficient to meet the requirements of such applications because the material removal rate (MRR) is often characterized inappropriately, and the material removal uniformity is seldom considered. In this study, chemical vapor deposition (CVD) growth of two lightly boron doped (p-) epilayers was performed on 3° misoriented (100) high pressure high temperature substrates of 4.5 x $4.5 mm^{2}$ area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications. [ABSTRACT FROM AUTHOR]

Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process. [ABSTRACT FROM AUTHOR]

In April 2022, I was invited to lecture at Villanova University, Villanova, PA, USA, and I met Dr. Pritpal Singh. Later, in June of that year during the IEEE TAB Series, I met the then President of the Humanitarian Activities Committee (HAC), Dr. Sampathkumar Veeraraghavan. Later, in July during the IEEE Latin American Electron Devices Conference (LAEDC) sponsored by the IEEE Electron Devices Society (EDS), I was invited to give a keynote talk and to be part of a panel. Mario Aleman conducted this panel session on Humanitarian Technology 2022, which also included both above-mentioned individuals. I also had the opportunity to meet the fourth panelist, Dr. Morgan Kiani (see). [ABSTRACT FROM AUTHOR]

Edge computing is an emerging computing paradigm representing decentralized and distributed information technology architecture. The demand for edge computing is primarily driven by the increased number of smart devices and the Internet of Things (IoT) that generate and transmit a substantial amount of data, that would otherwise be stored on cloud computing services. The edge architecture enables data and computation to be performed in close proximity to users and data sources and acts as the pathway toward upstream data centers. Rather than sending data to the cloud for processing, the analysis and work is done closer to where the source of the data is generated (). Edge services leverage local infrastructure resources allowing for reduced network latency, improved bandwidth utilization, and better energy efficiency compared to cloud computing. [ABSTRACT FROM AUTHOR]

Welcome to this March 2024 Special Issue on Advancing Sustainable Development Goals with AI This issue features research on how AI and data technologies can be used to advance the United Nations (UN) sustainable development goals (SDGs). [ABSTRACT FROM AUTHOR]

In this Article, we will introduce several interrelated problems present in municipal solid waste recycling efforts, both globally and locally. The introduction serves to demonstrate how the lack of adequate global waste tracking and community-level waste contamination are related issues. This article elaborates on how these issues could be addressed with the Internet of Things (IoT), artificial intelligence (AI), and open data technology deployment. We will investigate the existing and possible applicability of this solution in resource-constrained environments, as opposed to exclusive use in the typical “smart city” context. Finally, we will discuss the risks and limitations of this approach. [ABSTRACT FROM AUTHOR]

In 2015, the United Nations (UN) launched an ambitious set of 17 Sustainable Development Goals (SDGs) to end poverty, protect the planet, and ensure prosperity for all as part of the 2030 Agenda for Sustainable Development. Achieving these far-reaching goals requires effective tracking of progress across 169 targets and over 230 indicators. Furthermore, adopted in 2015, Africa Agenda 2063 is a strategic framework developed by the African Union (AU) to optimize the use of the continent’s resources for sustainable and inclusive growth. It aims to deliver on key aspirations shared by African nations including a high standard of living, well-educated citizens, good governance, strong cultural identity, and Africa’s strong voice in global affairs. Built around 20 goals and seven priority areas, Agenda 2063 provides a shared vision and roadmap for socioeconomic transformation in Africa over the next 50 years. However, numerous countries in Africa face considerable challenges in collecting, timely, granular, high-quality data to adequately monitor SDG metrics. Traditional data sources like surveys and administrative records often have gaps, especially at subnational levels. As a result, national statistics offices, particularly in Africa, lack the data needed to properly inform SDG-related policies and interventions. [ABSTRACT FROM AUTHOR]

The article announces the IEEE International Symposium on Technology and Society, scheduled from September 18-20 in Puebla, Mexico, focusing on the Social Implications of Artificial Intelligence (AI), inviting submissions from academia, industry, and government to explore AI's impacts.

As we enter a New Year, we can look back on another year of solid accomplishment at IEEE Transactions on Semiconductor Manufacturing. I am happy to report that our impact factor remains steady at 2.70, and our mean time to first decision remains competitive at 8.3 weeks. Our Editorial Board remains as strong as ever, with the addition of Dr. Jun-Haeng Lee in the area of machine learning and data science applications in 2023, and we are actively seeking new board members. Our submissions remain strong, as do the special sections from conferences (ASMC, ISSM and CS-MANTECH). The Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing appeared in the November issue, and two additional special issues are in preparation. Prof. Duane Boning of MIT and Dr. Bill Nehrer of Technology Consultancy are co-editing a special issue on “Semiconductor Design for Manufacturing,” which will be a collaborative effort with the IEEE Transactions on Electron Devices. Drs. Oliver Patterson of Intel and Tomasz Brozek of PDF Solutions are also co-editing a special issue on sustainable semiconductor manufacturing. We are also happy to announce the Best paper Award for 2023, in the companion editorial appearing in this issue. Congratulations to all the honorees, and we hope we will continue to see their submissions in the future. Our thanks go to Drs. Jeanne Bickford, Dragan Djurdjanovic and Mahadeva Iyer Natarajan for their work on this committee. [ABSTRACT FROM AUTHOR]

A scheduling problem for parallel batch processing machines (BPMs) with jobs having unequal ready times in semiconductor wafer fabrication facilities (wafer fabs) is studied in this paper. A blended objective function combining the total weighted tardiness (TWT) and the total electricity cost (TEC) under a time-of-use (TOU) tariff is considered. A genetic programming (GP) procedure is designed to automatically discover priority indices for a heuristic scheduling framework. Results of computational experiments are reported that demonstrate that the learned priority indices lead to high-quality schedules in a short amount of computing time. [ABSTRACT FROM AUTHOR]

This work introduces a practical reinforcement learning (RL) techniques to address the complex scheduling challenges in producing Active Matrix Organic Light Emitting Diode displays. Specifically, we focus on autonomous optimization of the photolithography process, a critical bottleneck in the fabrication. This provides an outperforming scheduling method compared with the existing rule-based approach which requires diverse rules and engineer experience on adapting dynamic environments. Our purposing RL network was designed to make effective schedules aligning with layered structures of the planning and scheduling modules for mass production. In the training phase, historical production data is utilized to create a representative discrete event simulation environment. The RL agent, based on the Deep Q-Network, undergoes episodic training to learn optimal scheduling policies. To ensure safe and reliable scheduling decisions, we further introduce action filters and parallel competing schedulers. The performance of RL-based Scheduler (RLS) is compared to the Rule-Based Scheduler (RBS) over actual fabrication in a year-long period. Based on key performance indicators, we validate the RLS outperforms the RBS, with a remarkable improvement in step target matching, reduced setup times, and enhanced lot assignments. This work also paves a way for the gradual integration of AI-based algorithms into smart manufacturing practices. [ABSTRACT FROM AUTHOR]

This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing demands a fast delivery of multiple gases to the tool. Hence this document provides formulas for the fluid-mechanical timescales of this delivery. This is done with a simple but realistic model of a gas-supply system, together with theory and computational-fluid-dynamic (CFD) simulations, and for representative but not comprehensive conditions relevant to etch. This timescale analysis shows that the rate-limiting process is (i) convection in the MFC-manifold tubing or (ii) convection in the tube between the flow splitter and the process chamber. This depends on (a) the lowest MFC sccm in the gas-supply system and (b) the total gas-supply-system sccm. Therefore, speeding up the gas delivery requires enhancing (i) and (ii). Moreover, (i) would become more important in view of a current trend towards smaller MFC sccms in etch. Examples on how to speed up the gas delivery and enhance the mixing are provided. The present analysis can be adapted to other conditions and manufacturing processes. [ABSTRACT FROM AUTHOR]

Doing high throughput high accuracy metrology in small geometries is challenging. One approach is to build easily measurable proxy targets onto dies and make a predictive model based on those signals. We use optical Pattern Shift Response (PSR) proxy targets to build predictive models of the electrical characteristics of devices in the Back End Of Line (BEOL). Given the wide choice of PSR targets, we explore how to select combinations of them to maximise the utility of the features for building an accurate Machine Learning (ML) model; we call this approach Multiplexed Optical Metrology. We also explore the trade-off between chip area dedicated to targets and achievable accuracy. We run ML experiments using different selections of targets measured at different stages of BEOL processing: post-lithography and post-Chemical-Mechanical-Planarisation (CMP). Our results show that a) reasonable predictive performance can be achieved for a reasonable area budget; b) ML model performance across target families varies significantly, thus justifying the need for careful selection of targets; c) longitudinal measurements of targets increases accuracy for no extra area penalty; d) increasing the number of targets gives some improvement in accuracy for a dataset of this size, but relatively small compared to the increase in area budget needed. Ultimately we aim to do die-level yield prediction using these techniques. We discuss how collecting a larger dataset with appropriate yield information is the logical next step to achieving this. [ABSTRACT FROM AUTHOR]

Accurate prediction of the remaining useful life (RUL) of an ion mill is vital for optimizing the overall performance of the ion mill etching (IME) process. However, due to the uneven distribution of important information, and the poorly understood failure mechanisms, fault prognosis in this process presents significant challenges. Deep neural networks have shown promising results for extracting, without domain knowledge, relevant features from condition monitoring data. This study proposes a multi-scale and multi-branch Transformer network based on the vanilla Transformer to predict the RUL of ion mills. To extract features on various scales, multi-scale feature extraction first generates receptive fields of various sizes, which are then integrated to obtain feature representations. The multi-branch Transformer uses the parallel attention mechanism and long short-term memory (LSTM) to capture both the adjacent location information and the crucial information of a given timestamp. Handcrafted features are also incorporated as additional input to enhance the prediction accuracy of the model. The proposed model is evaluated on a dataset from a semiconductor IME process. The experimental results demonstrate that the proposed model outperforms other deep neural network and further highlight the practical feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

The patterning of silicon and silicon oxide nanocones onto the surfaces of devices introduces interesting phenomena such as anti-reflection and super-transmissivity. While silicon nanocone formation is well-documented, current techniques to fabricate silicon oxide nanocones either involve complex fabrication procedures, non-deterministic placement, or poor uniformity. Here, we introduce a single-mask dry etching procedure for the fabrication of sharp silicon oxide nanocones with smooth sidewalls and deterministic distribution using electron beam lithography. Silicon oxide films deposited using plasma-enhanced chemical vapor deposition are etched using a thin alumina hard mask of selectivity > 88, enabling high aspect ratio nanocones with smooth sidewalls and arbitrary distribution across the target substrate. We further introduce a novel multi-step dry etching technique to achieve ultra-sharp amorphous silicon oxide nanocones with tip diameters of ~10 nm. The processes presented in this work may have applications in the fabrication of amorphous nanocone arrays onto arbitrary substrates or as nanoscale probes. [ABSTRACT FROM AUTHOR]

Single-image super-resolution (SISR) techniques have found wide applications in semiconductor defect inspection. Enhancing image resolution to improve inspection sensitivity and accuracy holds great significance. A novel SISR algorithm, called cross-convolutional residual network (CCRN), is proposed in this study. CCRN comprises a cross-convolutional module (CCM), which incorporates a cross-sharing mechanism that facilitates the fusion of features from different stages, enabling the extraction of more information from the image. Moreover, a global residual aggregation structure (GRA) is introduced. GRA captures and transfers different levels of residual features acquired from learning each CCM to the reconstruction layer. Experimental results demonstrate that the proposed SR algorithm outperforms existing state-of-the-art SR algorithms in terms of both visual and quantitative metrics when applied to optical, SEM, and TEM images of microfluidic chips, CMOS image sensors, and quantum dots, respectively. Additionally, CCRN significantly improves the accuracy of defect classification and inspection of unpatterned wafers, as evaluated using the WM-811K dataset. Notably, an increase in local defection testing accuracy from 79.00% to 89.00% and an improvement in classification accuracy from 93.69% to 96.06% are achieved. These findings underscore the potential applications of the proposed algorithm in improving semiconductor defect inspection and classification accuracies. [ABSTRACT FROM AUTHOR]

Since the invention of transistors and integrated circuits, the development of semiconductor processes has advanced rapidly. Current microchips contain hundreds of millions of transistors. The remarkable development of semiconductors thus far has also led to difficulties in designing tightly packed lithography patterns without unwanted defects called hotspots in the manufacturing process. Therefore, research areas focusing on these problems have received much attention. In particular, predicting hotspots during the design stage is essential for high productivity in the semiconductor industry. In this study, we developed a deep learning-based SEM image generation model to predict hotspots from layout patterns at the design stage. Our model combines a segmentation network and an image-to-image translation network based on a conditional generative adversarial network in parallel. Our proposed model can predict and display potential hotspots in scanning electron microscopy images generated from given layouts. Additionally, the model leverages prior knowledge of the optical diameter to predict patterns that are prone to hotspots. Our model shows improved performance over baseline models when evaluated on real-world industrial data. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

It has been a widely growing interest in using silicon carbide (SiC) in high-power electronic devices. Yet, SiC wafers may contain killer defects that could reduce fabrication yield and make the device fall into unexpected failures. To prevent these failures from happening, it is very important to develop inspection tools that can detect, characterize and locate these defects in a non-invasive way. Current inspection techniques such as Dark Field or Bright field microscopy are effectively able to visualize most such defects; however, there are some scenarios where the inspection becomes problematic or almost impossible, such as when the defects are too small or have low contrast or if the defects lie deep into the substrate. Thus, an alternative method is needed to face these challenges. In this paper, we demonstrate the application of coherent Fourier scatterometry (CFS) as a complementary tool in addition to the conventional techniques to overcome different and problematic scenarios of killer defects inspection on SiC samples. Scanning electron microscopy (SEM) has been used to assess the same defects to validate the findings of CFS. Great consistency has been demonstrated in the comparison between the results obtained with CFS and SEM. [ABSTRACT FROM AUTHOR]