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For neural recording applications, a low power neural signal acquisition amplifier has been proposed. Since extracellular neural signals are weak in amplitude and low in frequency, amplification of these signals with less noise and low power is a must for epilepsy prediction. The proposed amplifier employs anti parallel diode connected PMOS transistors as pseudo resistors to realize low frequency high pass function (LFHPF), Transconductance (gm - boosted) Low Noise Amplifier to achieve high gain and Gm-C LPF to select the desired band of neural signals. The proposed amplifier achieves a gain of 44.6 dB with 61.75% reduction in power consumption and 1 µV/ Hz less input referred noise compared to the conventional amplifier. These results have been authorized using the cadence spectre trainer with CMOS 180 nm. A greater part of driven based rectifier is used as MOSFET to supply adequate power, as this structure can be made fully implantable. Hence, the neural amplifier can be made compatible with a wireless programmable, implantable neural recording micro system. [ABSTRACT FROM AUTHOR]

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μW at 1 V power supply. The measurement results show an input-referred noise of 6.1 μVrms and occupy 0.04 mm2 silicon area.

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μ W at 1 V power supply. The measurement results show an input-referred noise of 6.1 μ V rms and occupy 0.04 mm 2 silicon area. [ABSTRACT FROM AUTHOR]

An ultralow power 0.6 V neural amplifier with on-chip analog spike detection is presented. A capacitively-coupled instrumentation amplifier (CCIA) with the current-reused and self-biased scheme is proposed to reduce the overall power consumption and to enhance the noise efficiency. The transistors in the amplifier are operated in the subthreshold region to enhance noise performance. The analog-domain spike detection based on a low power peak detector can reduce the overall power consumption. The circuit is fabricated using the standard 0.18 μm CMOS process. The passband of the circuit is from 6.4 Hz to 4.46 kHz. Input-referred noise is 10.68 μVrms. The supply voltage is 0.6 V, and the power consumption of the singlestage CCIA is 50.6 nW. The CCIA achieves a good noise efficiency factor and power efficiency factor of 1.79 and 1.93, respectively. The overall power consumption including two CCIAs, the programmable gain amplifier, and the analog spike detector is 269.8 nW. Input spikes with an amplitude of 50 μV at 100-Hz intervals are accurately detected.

This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper. [ABSTRACT FROM AUTHOR]

This report presents characterizations of in vivo neural recordings performed with a CMOS multichannel neural recording chip that uses rapid multiplexing directly at the electrodes, without any pre-amplification or buffering. Neural recordings were taken from a 16-channel microwire array implanted in rodent cortex, with comparison to a gold-standard commercial bench-top recording system. We were able to record well-isolated threshold crossings from 10 multiplexed electrodes and typical local field potential waveforms from 16, with strong agreement with the standard system (average SNR = 2.59 and 3.07 respectively). For 10 electrodes, the circuit achieves an effective area per channel of 0.0077 mm2, which is >5x smaller than typical multichannel chips. Extensive characterizations of noise and signal quality are presented and compared to fundamental theory, as well as results from in vivo and in vitro experiments. By demonstrating the validation of rapid multiplexing directly at the electrodes, this report confirms it as a promising approach for reducing circuit area in massively-multichannel neural recording systems, which is crucial for scaling recording site density and achieving large-scale sensing of brain activity with high spatiotemporal resolution. [ABSTRACT FROM AUTHOR]

A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31 dB mid-band gain and a low-pass cutoff frequency of 0.85 Hz. The circuit operates from a 1 V supply and draws 950 nA current at room temperature. [ABSTRACT FROM AUTHOR]

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5  $\mu$ m CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88  $\mu$ V $_{\text{rms}}$ , the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system. [ABSTRACT FROM AUTHOR]

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79Vrms and noise efficiency factor of 3.16. The IC consumes 2.4W at 1.2V supply and the die area is 0.09mm2. [ABSTRACT FROM AUTHOR]

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain−machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 μm × 20 μm) and 12 reference pixels (20 μm × 80 μm), densely packed on a 50 μm thick, 100 μm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 μVrms, while using 678 electrodes, with just 3 μW power dissipation per pixel and 45 μW per read-out channel (including data transmission). [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power, low-noise fully differential pseudo-open-loop preamplifier with programmable bandwidth for monitoring neural activities. The proposed pseudo-open-loop topology can achieve high-power-noise efficiency as well as high linearity and precise gain control over process. The proposed fully differential preamplifier can balance the common mode of the differential outputs without a common-mode feedback circuit, and bias the ac-coupled input transistors without an external reference. A current-ratio gain design can set a stable gain over process and bias current variations. A programmable embedded gm-C low-pass filter (LPF) can be tuned by adjusting bias current, so that the proposed preamplifier can be configured to be used in recording single neuron spikes or field potentials (EEG, ECoG). The proposed amplifier is configured to consume 400 nA at 2.5-V power supply; the total chip area is 0.189 mm2. The measured thermal noise floor is 85 nV/ $\surd $ Hz and input-referred noise is 1.69~\mu \text{V}_{\mathrm {rms}} from 0.3 Hz to 1 kHz when using a chopper stabilization technique to suppress 1/f noise. The fabricated preamplifier shows a noise efficiency factor of 2.43 in the fully differential topology. [ABSTRACT FROM PUBLISHER]

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-$\mu$m SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 \mu$m wide, 10 mm long, 20  \mu$m thick), achieving a crosstalk of dB. The probe base (5 \times$ 9 mm^2$ ) implements dual-band recording and a 171.6 Mbps digital interface. Measurement results show a total input-referred noise of 6.4 \mu and a total power consumption of 49.1 $\mu$W/channel. [ABSTRACT FROM PUBLISHER]

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves

This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection. For a two-channel amplifier, the measurements show a midband gain of 58.7 dB and a passband from 490 mHz to 10.5 kHz. The amplifier consumes 2.85 \mu\mboxA per channel from a 1-V supply and exhibits an input-referred noise of 3.04 \mu\mboxV_\mathrmrms from 0.1 Hz to 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than 50 dB in the passband. The amplifier is fabricated in a 90-nm CMOS process and occupies 0.137 \mboxmm^2 of chip area. [ABSTRACT FROM AUTHOR]

We present a 320-channel active probe for high-spatial-resolution neuromonitoring and responsive neurostimulation. The probe comprises an integrated circuit (IC) cell array bonded to the back side of a pitch-matched microelectrode array. The IC enables up to 256-site neural recording and 64-site neural stimulation at the spatial resolution of 400 \mum and 200 \mum, respectively. It is suitable for direct integration with electrode arrays with the shank pitch of integer multiples of 200 \mum. In the presented configuration, the IC is bonded with a 8\,\times\,8 400 \mum-pitch Utah electrode array (UEA) and up to additional 192 recording channels are used for peripheral neuromonitoring. The 0.35 \mum CMOS circuit array has a total die size of 3.5 mm\,\times\,3.65 mm. Each stimulator channel employs a current memory for simultaneous multi-site neurostimulation, outputs 20 \muA–250 \muA square or arbitrary waveform current, occupies 0.02 mm^2, and dissipates 2.76 \muW quiescent power. Each fully differential recording channel has two stages of amplification and filtering and an 8-bit single-slope ADC, occupies 0.035 mm^2 , and consumes 51.9 \muW. The neural probe has been experimentally validated in epileptic seizure propagation studies in a mouse hippocampal slice in vitro and in responsive neurostimulation for seizure suppression in an acute epilepsy rat model in vivo . [ABSTRACT FROM PUBLISHER]

This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μ m CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μ W, which makes it highly suitable for a multi-channel neural signal recording system. [ABSTRACT FROM AUTHOR]

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods. [ABSTRACT FROM AUTHOR]

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm2 area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger. [ABSTRACT FROM AUTHOR]