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This paper presents a time-of-flight (TOF) range imager with high-range resolution. The range imager employs a TOF measuring technique using an impulse photocurrent response and a high-speed lock-in pixel based on a draining-only modulation. To address a skew problem in a 2-D array of the pixels, a column-wise gating-clock skew calibration was implemented. Each pixel has an in-pixel buffer and decoupling capacitor to reduce row-wise skew. A test-implemented imager has $132 \times 120$ effective pixels. The skew calibration circuit successfully reduce the skew from 173 to 8 psrms. The range resolution was achieved to be 0.25 mm with a 32-mm range, which corresponds to a 1.7-ps time resolution.

This paper presents a CMOS time-of-flight (ToF) range image sensor using high-speed lock-in pixels with background light canceling capability. The proposed lock-in pixel uses MOS gate-induced lateral electric field control of depleted potential of pinned photodiode for implementing a multiple-tap charge modulator while achieving a high-speed charge transfer for high-time resolution. A TOF image sensor with 320 x 240 effective pixels is implemented using a 0.11- $\mu \text{m}$ CMOS image sensor process. The TOF sensor has a range resolution of less than 12 mm without background light and 20 mm under background line for the range from 0.8 to 1.8 m and integration time of 50 ms. The effectiveness of in-pixel background light canceling with a three-tap output pixel is demonstrated.

This paper presents a CMOS Time-of-Flight (TOF) range imager using pinned-photodiode based high-speed 4-tap lock-in pixels with lateral-electric-field charge modulators (LEFM) in a 0.11 um CIS process. The proposed lock-in pixel structure using lateral electric field control is suitable for implementing a multiple-tap charge modulator while achieving high-speed charge transfer for high time resolution. The TOF imager with the multiple-tap charge modulators is expected to have background light cancelling capability in one frame and to improve range resolution with the 4 time windows for a range-shifted light pulse. Measurement results of the implemented TOF imager with 160×240 pixels are reported.

A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

In the work described in this paper, an image reproduction scheme with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor was demonstrated. The sensor captures an object by compressing a sequence of images with focal-plane temporally random-coded shutters, followed by reconstruction of time-resolved images. Because signals are modulated pixel-by-pixel during capturing, the maximum frame rate is defined only by the charge transfer speed and can thus be higher than those of conventional ultra-high-speed cameras. The frame rate and optical efficiency of the multi-aperture scheme are discussed. To demonstrate the proposed imaging method, a 5×3 multi-aperture image sensor was fabricated. The average rising and falling times of the shutters were 1.53 ns and 1.69 ns, respectively. The maximum skew among the shutters was 3 ns. The sensor observed plasma emission by compressing it to 15 frames, and a series of 32 images at 200 Mfps was reconstructed. In the experiment, by correcting disparities and considering temporal pixel responses, artifacts in the reconstructed images were reduced. An improvement in PSNR from 25.8 dB to 30.8 dB was confirmed in simulations.

To demonstrate the low-noise performance of the multi-aperture imaging system using a selective averaging method, an ultra-high-sensitivity multi-aperture color camera with 2×2 apertures is being developed. In low-light conditions, random telegraph signal (RTS) noise and dark current white defects become visible, which greatly degrades the quality of the image. To reduce these kinds of noise as well as to increase the number of incident photons, the multi-aperture imaging system composed of an array of lens and CMOS image sensor (CIS), and the selective averaging for minimizing the synthetic sensor noise at every pixel is utilized. It is verified by simulation that the effective noise at the peak of noise histogram is reduced from 1.44 e- to 0.73 e- in a 2×2-aperture system, where RTS noise and dark current white defects have been successfully removed. In this work, a prototype based on low-noise color sensors with 1280×1024 pixels fabricated in 0.18um CIS technology is considered. The pixel pitch is 7.1μm×7.1μm. The noise of the sensor is around 1e- based on the folding-integration and cyclic column ADCs, and the low voltage differential signaling (LVDS) is used to improve the noise immunity. The synthetic F-number of the prototype is 0.6.

Ultra-high-speed cameras are a powerful tool for biology as well as physics and mechanics to analyze the process of ultra-high-speed phenomena. The frame rate of the state-of-the-art burst-readout ultra-high-speed silicon imagers has reached approximately 20Mfps [1,2]. To observe faster phenomena such as plasma generation in laser processing, the state of electrons in a chemical reaction, and so on, much faster cameras are desired. There are several factors that prevent the speed-up of the ultra-high-speed imager: high gate control voltages and high power dissipation for high-efficiency multi-stage charge transfer in CCD imagers, and the current density limit of the power and ground lines and RC-constant of the vertical readout lines in CMOS imagers. Computational imaging can be a promising option to break the design limit of solid-state ultra-high-speed imagers. Several dedicated CMOS imagers have been demonstrated [3,4]. This paper presents a demonstration of a single-chip ultra-high-speed multi-aperture CMOS imager based on compressive sampling. The imager performs single-shot burst-readout image acquisition at a frame rate of 200Mfps.