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Wide bandgap oxide semiconductors are very promising channel candidates for next-generation electronics due to their large-area manufacturing, high-quality dielectrics, low contact resistance, and low leakage current. However, the absence of ultra-short gate length (Lg) p-type transistors has restricted their application in future complementary metal-oxide-semiconductor (CMOS) integration. Inspired by the successfully grown high-hole mobility bilayer (BL) beta tellurium dioxide (\b{eta}-TeO2), we investigate the performance of sub-5-nm-Lg BL \b{eta}-TeO2 field-effect transistors (FETs) by utilizing first-principles quantum transport simulation. The distinctive anisotropy of BL \b{eta}-TeO2 yields different transport properties. In the y-direction, both the sub-5-nm-Lg n-type and p-type BL \b{eta}-TeO2 FETs can fulfill the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, which are superior to the reported oxide FETs (only n-type). Remarkably, we for the first time demonstrate the existence of the NMOS and PMOS symmetry in sub-5-nm-Lg oxide semiconductor FETs. As to the x-direction, the n-type BL \b{eta}-TeO2 FETs satisfy both the ITRS HP and low-power (LP) requirements with Lg down to 3 nm. Consequently, our work shed light on the tremendous prospects of BL \b{eta}-TeO2 for CMOS application.

Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors through ab initio quantum transport simulations. Our simulation results demonstrate that, through appropriate doping and dielectric engineering, the sub-1-nm devices can meet the requirement of extended 'ITRS'(International Technology Roadmap for Semiconductors) $L_g$=0.34 nm. Following device optimization, we achieve impressive maximum on-state current densities of 409 $\mu A / \mu m$ for n-type and 800 $\mu A / \mu m$ for p-type high-performance (HP) devices, while n-type and p-type low-power (LP) devices exhibit maximum on-state current densities of 75 $\mu A / \mu m$ and 187 $\mu A / \mu m$, respectively. We employed the Wentzel-Kramer-Brillouin (WKB) approximation to explain the physical mechanisms of underlap and spacer region optimization on transistor performance. The underlap and spacer regions primarily influence the transport properties of sub-1-nm transistors by respectively altering the width and body factor of the potential barriers. Compared to ML $MoS_2$ transistors with a 1 nm gate length, our sub-1-nm gate length HP and LP ML $MoS_2$ transistors exhibit lower energy-delay products. Hence the sub-1-nm gate length transistors have immense potential for driving the next generation of electronics.

Processing-in-memory architectures have been regarded as a promising solution for CNN acceleration. Existing PIM accelerator designs rely heavily on the experience of experts and require significant manual design overhead. Manual design cannot effectively optimize and explore architecture implementations. In this work, we develop an automatic framework PIMSYN for synthesizing PIM-based CNN accelerators, which greatly facilitates architecture design and helps generate energyefficient accelerators. PIMSYN can automatically transform CNN applications into execution workflows and hardware construction of PIM accelerators. To systematically optimize the architecture, we embed an architectural exploration flow into the synthesis framework, providing a more comprehensive design space. Experiments demonstrate that PIMSYN improves the power efficiency by several times compared with existing works. PIMSYN can be obtained from https://github.com/lixixi-jook/PIMSYN-NN.

Processing-in-memory (PIM) has shown extraordinary potential in accelerating neural networks. To evaluate the performance of PIM accelerators, we present an ISA-based simulation framework including a dedicated ISA targeting neural networks running on PIM architectures, a compiler, and a cycleaccurate configurable simulator. Compared with prior works, this work decouples software algorithms and hardware architectures through the proposed ISA, providing a more convenient way to evaluate the effectiveness of software/hardware optimizations. The simulator adopts an event-driven simulation approach and has better support for hardware parallelism. The framework is open-sourced at https://github.com/wangxy-2000/pimsim-nn.

Crossbar-based PIM DNN accelerators can provide massively parallel in-situ operations. A specifically designed compiler is important to achieve high performance for a wide variety of DNN workloads. However, some key compilation issues such as parallelism considerations, weight replication selection, and array mapping methods have not been solved. In this work, we propose PIMCOMP - a universal compilation framework for NVM crossbar-based PIM DNN accelerators. PIMCOMP is built on an abstract PIM accelerator architecture, which is compatible with the widely used Crossbar/IMA/Tile/Chip hierarchy. On this basis, we propose four general compilation stages for crossbar-based PIM accelerators: node partitioning, weight replicating, core mapping, and dataflow scheduling. We design two compilation modes with different inter-layer pipeline granularities to support high-throughput and low-latency application scenarios, respectively. Our experimental results show that PIMCMOP yields improvements of 1.6$\times$ and 2.4$\times$ in throughput and latency, respectively, relative to PUMA.

Twisted bilayers of van der Waals materials have recently attracted great attention due to their tunable strongly correlated phenomena. Here, we investigate the chirality-specific physics in 3D moir\'e superlattices induced by Eshelby twist. Our direct DFT calculations reveal helical rotation leads to optical circular dichroism, and chirality-specific nonlinear Hall effect, even though there is no magnetization or magnetic field. Both these phenomena can be reversed by changing the structural chirality. This provides a way to constructing chirality-specific materials.

For a long time, two-dimensional (2D) hexagonal MoS2 was proposed as a promising material for valleytronic system. However, the limited size of growth and low carrier motilities in MoS2 restrict its further application. Very recently, a new kind of hexagonal 2D MXene, MoSi2N4, was successfully synthesized with large size, excellent ambient stability, and considerable hole mobility. In this paper, based on the first-principles calculations, we predict that the valley-contrast properties can be realized in monolayer MoSi2N4 and its derivative MoSi2As4. Beyond the traditional two-level valleys, the valleys in monolayer MoSi2As4 are multiple-folded, implying a new valley dimension. Such multiple-folded valleys can be described by a three-band low-power Hamiltonian. This study presents the theoretical advance and the potential applications of monolayer MoSi2N4 and MoSi2As4 in valleytronic devices, especially multiple information processing.

Valleytronics is a rising topic to explore the emergent degree of freedom for charge carriers in energy band edges and has attracted a great interest due to many intriguing quantum phenomena and potential application in information processing industry. Creation of permanent valley polarization, i.e. unbalanced occupation at different valleys, is a chief challenge and also urgent question to be solved in valleytronics. Here we predict that the spin-orbit coupling and magnetic ordering allow spontaneous valley Zeeman-type splitting in pristine monolayer of VAgP2Se6 by using first-principles calculations. The Zeeman-type valley splitting can lead to permanent valley polarization after suitable doping. The Zeeman-type valley splitting is similar to the role of spin polarization in spintronics and is a vital requirement for practical devices in valleytronics. The nonequivalent valleys of VAgP2Se6 monolayer can emit or absorb circularly polarized photons with opposite chirality, and thus this material shows a great potential to work as a photonic spin filter and circularly-polarized-light resource. A valley pseudospin field effect transistor (VPFET) is designed based on the monolayer VAgP2Se6 akin to the spin field effect transistors. Beyond common transistors, VPFETs carry information of not only the electrons but also the valley pseudospins.