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In semiconductor device manufacturing, wafer materials may be exposed to intense light sources by optical metrology tools. The desired light fluence often needs to be maximized to levels just below the optical damage threshold of materials deposited on the wafer, such as ruthenium. We, therefore, investigate light-induced permanent structural changes to thin Ru films after exposure to single 400 nm wavelength femtosecond pulses in the fluence regime before catastrophic damage. For fluences below that where full-ablation occurs, small optical increases in the reflectivity of up to 4 % are observed in the aftermath with a weak probe beam. In this fluence regime, dark-field, scanning electron, and atomic force microscopy images reveal morphological changes such as top-level ablation, where only the top part of the ruthenium layer is ablated whereas the lower part still remains on the substrate, and nanovolcano formation. However, neither top-level ablation nor nanovolcano formation is responsible for the reflection increase. Instead, Electron Backscatter Diffraction reveals that in this low fluence regime where reflectivity increases, Ru grains melt and resolidify into larger grains, which is likely responsible for the observed reflectivity increases. This result is reminiscent of our earlier work on aluminum layers and it suggests that there may be more metals that display this behavior. [ABSTRACT FROM AUTHOR]

Modern semiconductor devices, such as gate-all-around nanosheet field-effect transistors (GAA NS FETs), are smaller than displacement damage cascades from fission neutrons. In this regime, device failure may occur through low-probability single events, rather than by parametric degradation previously seen in larger devices. Here, we present a statistical model that predicts the probability of a damage event in a small device and the probability distribution of the magnitude, i.e., number of displacements within the device, from each event. The model is developed first for neutron irradiation and then for energetic ion irradiation. The model is consistent with results from recent experiments in which lithium-ion irradiation produced stepwise increases in subthreshold current in GAA NS FETs. [ABSTRACT FROM AUTHOR]

Ridge microstructures were prepared by etching through samples consisting of a series of stacked InAs x P 1 − x quantum wells (QWs) with step graded composition grown on InP by molecular beam epitaxy. Different etching techniques were used: wet etching with HCl/H 2 O and reactive ion etching with CH 4 /H 2. These microstructures were characterized by low-temperature micro-photoluminescence. The photoluminescence (PL) emission associated with each QW was clearly identified. The PL was measured in detail across etched ridge stripes of various widths. Variations of the integrated PL intensities across the etched stripes were observed. The PL intensities for all QWs increase gradually from the edge to the center of the ridge microstructures. The PL intensity measured at the ridge center is systematically reduced for ridges which are 10 or 20 μ m wide as compared to ridges which are 30 μ m wide or larger. On the other hand, the spectral peak position of the PL lines remained constant with high accuracy (0.2–0.4 meV) across the microstructures. These observations are discussed in terms of the different possible mechanisms which determine the PL intensity variations, namely, non-radiative recombination at the etched walls and effects of stray electric fields which result from the etching process. Based on this discussion, we compare quantitatively the different etching processes which we have used. Altogether, this study illustrates the contribution that specially designed test structures, coupled with advanced spectroscopic characterization, can provide to the development of semiconductor photonic devices (e.g., lasers or waveguides) involving etching processes. [ABSTRACT FROM AUTHOR]

This document is a summary of a special issue in the Journal of Applied Physics on semiconductor physics. The special issue focuses on the research of new semiconductor materials, structures, and devices, as well as the development of characterization methods based on plasma, thermal, elastic, acoustic, and related effects. The articles cover various topics such as photothermal methods, theoretical and experimental models, modern materials like thin films and heterostructures, and imaging techniques. The research presented in this special issue has applications in microelectronics, optoelectronics, solar cells, medical instrumentation, and quantum computing. [Extracted from the article]

PN junctions play important roles in semiconductor devices. Flexoelectricity, an electromechanical coupling between strain gradient and electric polarization, has non-negligible contributions in nano-devices. The thermoflexoelectric effect is a phenomenon in which temperature gradients generate inhomogeneous strains and further induce flexoelectric polarizations. Therefore, temperature gradients can affect carrier transport in PN junctions through the thermoflexoelectric effect. In this paper, a one-dimensional model of the PN junction under a uniform temperature change is established. Exact solutions for the electromechanical fields in the PN junction are obtained for the first time. The effects of the temperature gradient, doping level, and flexoelectric coefficient on the electromechanical behaviors of the PN junction are numerically analyzed. The results indicate that carrier concentrations in the p and n regions are sensitive to temperature gradients because of the screening effect of the mobile charge on the flexoelectric polarization induced by the temperature gradient. Meanwhile, the flexoelectric field and the initial built-in electric field in the depletion region jointly determine the magnitude of the potential barrier, and thus, the temperature-gradient-induced flexoelectric field can tune the switching characteristics of the PN junction. This study provides a theoretical basis for the tuning of the electromechanical behavior of the PN junction by thermally induced flexoelectric fields. [ABSTRACT FROM AUTHOR]

Small angle x-ray scattering (SAXS) stands out as a promising solution in semiconductor metrology. The critical issue of SAXS metrology is to solve the SAXS inverse problem. With the increasing complexity of semiconductor devices, traditional strategies will face problems such as long iteration time and multiple solutions. To address these challenges, we develop a physical symmetry enhanced method to speed up the solution of the SAXS inverse problem for complex nanostructures. We incorporate the physical symmetry into a deep learning model, and a combined loss function is proposed to determine the correct structure in each step of training, which can continuously correct errors and make the model converge faster. The results show that the proposed method achieves high accuracy in determining the critical structural parameters of the complex profile gratings. Compared to traditional strategies, our method performs better in accuracy and does not require time-consuming iterations during reconstruction. The physical symmetry enhanced method provides a feasible way for achieving real-time reconstruction of complex profile nanostructures and is expected to promote the development of SAXS metrology. [ABSTRACT FROM AUTHOR]

Understanding the mechanical and thermodynamic properties of transition-metal dichalcogenides (TMDs) and their heterostructures is pivotal for advancing the development of flexible semiconductor devices, and molecular dynamics (MD) simulation is widely applied to study these properties. However, current uncertainties persist regarding the efficacy of empirical potentials in MD simulations to accurately describe the intricate performance of complex interfaces within heterostructures. This study addresses these challenges by developing an interatomic potential based on deep neural networks and first-principles calculations. Specifically focusing on MoS2/WS2 heterostructures, our approach aims to predict Young's modulus and thermal conductivities. The potential's effectiveness is demonstrated through the validation of structural features, mechanical properties, and thermodynamic characteristics, revealing close alignment with values derived from first-principles calculations. A noteworthy finding is the substantial influence of the load direction on Young's modulus of heterostructures. Furthermore, our results highlight that the interfacial thermal conductance of the MoS2/WS2 heterostructures is considerably larger than that of graphene-based interfaces. The potential developed in this work facilitates large-scale material simulations, bridging the gap with first-principles calculations. Notably, it outperforms empirical potentials under interface conditions, establishing its significant competitiveness in simulation computations. Our approach not only contributes to a deeper understanding of TMDs and heterostructures but also presents a robust tool for the simulation of their mechanical and thermal behaviors, paving the way for advancements in flexible semiconductor device manufacturing. [ABSTRACT FROM AUTHOR]

Fast carrier dynamics in organic thin-film transistors (OTFTs) was investigated by time-resolved electrostatic force microscopy (tr-EFM). We found that the carrier diffusion in the OTFTs proceeded in two stages: fast diffusion and slow diffusion. By applying the instantaneous frequency method to EFM, the temporal evolution of the spatial distribution of fast carriers in the channel region of the OTFTs, which took place on the timescale of several hundreds of nanoseconds, was evaluated. The inhomogeneous distribution of the local decay time constant showed that the carrier diffusion of the OTFTs was limited by the grain boundaries between each crystalline region. The quantitative capability of the method was verified by comparing the values of the carrier mobility estimated by the tr-EFM measurement and a numerical simulation. The mobility estimated from the experiment and the simulation showed good agreement, showing the possibility of the tr-EFM to evaluate the time evolution of dynamic phenomena in semiconductor devices. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

This Perspective focuses on experimental and theoretical aspects of positron annihilation spectroscopy. This set of methods is highly suitable for identifying and quantifying vacancy-type defects in semiconductors and also allows for analyzing their physics characteristics. We present selected examples from the past decade, where the methods have been used for obtaining timely and useful insights into the defect-controlled phenomenon in narrow-gap (Ge, GaSb) and wide-gap (III-nitride, oxide) semiconductors. We also discuss possible future developments that may allow more detailed studies in novel semiconductor materials and devices with ever more complex lattice structures. [ABSTRACT FROM AUTHOR]

Vacancies are generated in semiconductor devices while operating in the space radiation environment, impacting semiconductor carrier concentrations and dynamics. Positron annihilation lifetime spectroscopy (PALS) is used to probe these defect concentrations in bulk grown GaN, GaP, InAs, InP, Si, MgO, and ZnO both as-grown and as a function of 2–4 MeV proton irradiation. All samples were irradiated to yield a common initial damage production and characterized identically. In as-grown samples, PALS reveals vacancy concentrations above the saturation limit in the oxides, disabling further analysis. As a function of dose, of the materials in which defect accumulation could be probed, it is observed that GaN is the most resistant to the accumulation of defects (attributed to the Ga vacancies) and Si is the least. GaP (attributed to the Ga vacancy) and InAs exhibit slightly higher rates of vacancy accumulation than GaN. InP exhibits high defect accumulation rates approaching that of Si. This information is key to understanding the operation of a diverse set of semiconductors in the space radiation environment. [ABSTRACT FROM AUTHOR]

We present a setup for fast, low-bias (≤ 1 mV) DC transport measurements with μs time resolution for high ohmic resistance (≈ 20 k Ω) semiconducting samples. We discuss the circuitry and instrumentation for the measurement approach that can be applied to any kind of semiconductor device or (gated) two-dimensional material and demonstrate the main measurement artifacts in typical measurements by means of circuit simulation. Based on the latter, we present a simple two-step protocol for eliminating the measurement artifacts reliably. We demonstrate the technique by measuring the transitions between quantum Hall plateaus in the HgTe quantum wells and resolve plateaus as short-lived as 100 μs. [ABSTRACT FROM AUTHOR]

Charge diffusion from an ion track and its collection by a biased contact in a semiconductor domain is modeled and analyzed within the framework of the so-called diffusion–collection approach. We successively examine the case of charge diffusion from a point source and from a linear distribution, introducing and discussing the concept of collection velocity at the point where the collection current is evaluated. Analytical formulations of the collected charge, collection current, and collection velocity are developed. Implications for the calculation of the soft error rate in complementary metal-oxide-semiconductor circuits exposed to ionizing particles are derived. Finally, our model provides new insights into the correct definition of the charge collection velocity in collection–diffusion models. [ABSTRACT FROM AUTHOR]

The transmission electron microscope (TEM) is a powerful imaging, diffraction and spectroscopy tool that has revolutionized the field of microscopy. It has contributed to numerous breakthroughs in various scientific disciplines. TEM-based techniques can offer atomic resolution as well as elemental analysis, which benefit the study of epitaxial semiconductors and their related optoelectronic devices on the atomic scale. The design and optimization of the device performance depend on three key factors: the control of strain at nanometer scale, control of the formation and propagation of defects as well as the control of local electronic properties. Manipulation and optimization are only possible if the key factors can be characterized precisely. Herein, the TEM techniques for strain analysis, defect characterization and bandgap evaluation are reviewed and discussed. Lately, with the development of in-situ TEM techniques, researchers have been able to observe dynamic processes and study the behaviour of materials and devices under realistic conditions (in gaseous atmosphere or in liquids, at elevated or cryogenic temperatures, under strain, bias or illumination) in real-time with extremely high spatial resolution. This review explores the impact and significance of in-situ TEM in the field of semiconductors. [ABSTRACT FROM AUTHOR]

Atomic layer processing technology has advanced significantly since semiconductor devices have evolved from 2D to 3D stacked structures. Creating a uniform temperature distribution across the entire wafer during repeated heating and cooling cycles is an important aspect of atomic layer processing. Conventional embedded heaters rely on thermal conduction, resulting in slow heating rates. This can delay the cycle time of atomic layer processes, where rapid temperature changes are crucial. To overcome these problems, this study adopted a method to directly heat the wafer using gigahertz band microwaves. While there has been research on the heating mechanisms and effects of microwave irradiation on Si Wafers, studies on uniformity are lacking. Microwave heating depends on the distribution of the field, thus this study presents methods for improving uniformity by optimizing the antennas and controlling the cavity modes. A 2.45 GHz microwave was propagated in the TE10 mode in a WR-340 waveguide and radiated into the chamber through a slot located on a toroidal antenna designed for uniform heating. The radiated microwaves formed cavity modes within the chamber, thereby heating the 300 mm wafer. The wafer temperature was measured using a fiber Bragg grating sensor array; the heating rate at the top and back of the wafer was 6.5 °C/kW/s, and the within-wafer non-uniformity was 11.68% and 10.94%, respectively, after applying 500 W power for 60 s. A comparison of the temperature characteristics of the top and back sides of the wafer indicated no significant differences in uniformity, heating rate, and temperature profile. Based on these findings, it is anticipated that in atomic layer processes, where temperature control is crucial, the proposed method could reduce the process time and increase yield. [ABSTRACT FROM AUTHOR]

The spin field effect transistor (sFET), proposed by Datta and Das (1990 Appl. Phys. Lett. 56 665–7), has long been regarded as a model semiconductor spintronic device, offering potential for new, more energy-efficient functionalities in electronic devices. Here, the overview is given how the pursuit of meeting the requirements for implementing the sFET concept has influenced spintronic research, leading to a greater understanding of spin phenomena in solids and resulting in numerous exciting effects. After looking back, based on the recent developments, the possible future directions of the sFET-related research are described. [ABSTRACT FROM AUTHOR]

Charge transport in materials has an impact on a wide range of devices based on semiconductor, battery, or superconductor technology. Charge transport in sliding charge density waves (CDW) differs from all others in that the atomic lattice is directly involved in the transport process. To obtain an overall picture of the structural changes associated to the collective transport, the large coherent x-ray beam generated by an x-ray free-electron laser (XFEL) source was used. The CDW phase can be retrieved over the entire sample from diffracted intensities using a genetic algorithm. For currents below threshold, increasing shear deformation is observed in the central part of the sample while longitudinal deformation appears above threshold when shear relaxes. Shear thus precedes longitudinal deformation, with relaxation of one leading to the appearance of the other. Moreover, strain accumulates on surface steps in the sliding regime, demonstrating the strong pinning character of these surface discontinuities. The sliding process of nanometric CDW involves macroscopic sample dimensions. [ABSTRACT FROM AUTHOR]

This research paper presents a high-gain DC–DC converter with ultra-step-up voltage gain capability. The proposed converter is synthesized from a two-phase interleaved boost converter (IBC), and its voltage gain is doubled by adopting a voltage lift capacitor. To enhance its voltage gain capability, a floating capacitor-based gain extension cell is adopted subsequently. This cell yields a voltage gain that is cubed times the output voltage obtained from a classical boost converter (CBC). By cascading the two stages, the voltage gain of the proposed converter is enhanced to quartic times (4th power) that of the CBC. The proposed gain extension concept is validated by conducting practical experiments on a 16 V to 400 V, 150 W prototype version. Practically, the prototype converter delivers 150 W to the load and operates at a full-load efficiency of 92.7% when its switches are operated at safe duty ratio values. Under dynamic conditions, the proposed converter regulates the output voltage to 400 V quickly over a wide range of input voltage and load current variations; the overshoots and undershoots are also negligible. The maximum voltage gain of the proposed converter momentarily increases to 37 when the input voltage is drastically reduced to 10.8 V while the switches are still operated at safe duty ratio values. The voltage stress on the semiconductor devices is only a fraction of the output voltage due to the hybrid voltage gain extension technique. The input current is also ripple-free as the switches in the IBC structure are always operated at a duty ratio of 50%, and only the third switch is controlled to meet the required voltage gain. The salient features of the proposed converter are clearly highlighted by comparing it with several converters that possess quadratic, cubic, and quartic voltage gain functions. The common-ground connection between the source and the load in the proposed converter is an added preferable feature for PV applications. [ABSTRACT FROM AUTHOR]

The formation of rolled‐up cylindrical membranes stemming from the strain deformation‐induced delamination of a film‐like nanowires array composed of coalesced GaAs nanowires embedded in AlOx with a buried GaAs/AlAs core‐shell structure is reported. The delamination of the nanowires array film is driven by natural oxidation resulting from prolongated exposure to ambient atmosphere. Investigation of the structural characteristics of the nanowires in the array reveals an analytical description of the oxidation mechanism leading to the formation of the rolled‐up structures. The membrane can easily transfer by simply shaking off the surface membranes of the sample. The cylindrical membranes maintain the optical properties of the core GaAs nanowires surrounded by native oxide. The findings show the prospects for area‐saving and transferable semiconductor devices with advanced nanoscale optical functions. [ABSTRACT FROM AUTHOR]

Metal halide perovskites show promise for next-generation light-emitting diodes, particularly in the near-infrared range, where they outperform organic and quantum-dot counterparts. However, they still fall short of costly III-V semiconductor devices, which achieve external quantum efficiencies above 30% with high brightness. Among several factors, controlling grain growth and nanoscale morphology is crucial for further enhancing device performance. This study presents a grain engineering methodology that combines solvent engineering and heterostructure construction to improve light outcoupling efficiency and defect passivation. Solvent engineering enables precise control over grain size and distribution, increasing light outcoupling to ~40%. Constructing 2D/3D heterostructures with a conjugated cation reduces defect densities and accelerates radiative recombination. The resulting near-infrared perovskite light-emitting diodes achieve a peak external quantum efficiency of 31.4% and demonstrate a maximum brightness of 929 W sr−1 m−2. These findings indicate that perovskite light-emitting diodes have potential as cost-effective, high-performance near-infrared light sources for practical applications. Baek et al. report the formation of a discrete island–convex dome morphology in perovskite by solvent engineering to improve the outcoupling efficiency in NIR LEDs. 2D/3D heterostructures are constructed to further increase the efficiency to 31.4% with a peak radiance of 929 W sr−1 m−2 at 798 nm. [ABSTRACT FROM AUTHOR]

Germanium (Ge) has long been recognized for its superior carrier mobility and narrower band gap compared to silicon, making it a promising candidate in microelectronics and optoelectronics. The recent demonstration of good biocompatibility, combined with the ability to selectively functionalize its surface, establishes the way for its use in biosensing and bioimaging. This review provides a comprehensive analysis of the most recent advancements in the wet chemical functionalization of germanium surfaces. Wet chemical methods, including Grignard reactions, hydrogermylation, self-assembled monolayers (SAMs) formation, and arylation, are discussed in terms of their stability, surface coverage, and potential for preventing reoxidation, one of the main limits for Ge practical use. Special emphasis is placed on the characterization techniques that have advanced our understanding of these functionalized surfaces, which are crucial in the immobilization of molecules/biomolecules for different technological applications. This review emphasizes the dual functionality of surface passivation techniques, demonstrating that, in addition to stabilizing and protecting the active material, surface functionalization can impart new functional properties for germanium-based biosensors and semiconductor devices. [ABSTRACT FROM AUTHOR]

We propose conservative type numerical method to simulate thermoelectrical semiconductor device problem, in which mixed finite element method used for electric potential equation, conservative characteristic finite element method for electron and hole concentration equations, and standard finite element method for heat conduction equation. By temporal-spatial error splitting argument, the optimal error estimates without certain time step restriction are derived, and low order convergence rate of electrostatic potential and electric field intensity will not affect the accuracy of the electron, hole density and temperature. Numerical tests are performed to validate the theoretical results and application performance of the given method. [ABSTRACT FROM AUTHOR]

Over the past decades, metasurfaces have experienced rapid development controlling the propagation of electromagnetic waves. Seamlessly combining metasurfaces with semiconductor devices enhance the device's performance and expand functional diversity. Currently, vertical‐cavity surface‐emitting lasers integrated with metasurfaces (MS‐VCSELs) employed to generate various wavefronts. However, the existing MS‐VCSELs that use only phase modulation still face limitations and challenges in generating customized fields, especially in 3D space. Here, amplitude‐phase metasurfaces are proposed and joint amplitude‐phase modulations are employed to increase the degree of freedom in controlling laser fields. By using electron beam lithography (EBL) and inductively coupled plasma reaction ion etching (ICP‐RIE), metasurfaces are directly fabricated on the back‐emitting surface of VCSELs, enabling samples to realize diverse functions such as multi‐focus multi‐plane generation and intensity control, multi‐plane holographic images, and laser beam deflections with different intensities. Compared to traditional discrete metasurface configurations, the proposed scheme achieves on‐chip integration of amplitude‐phase metasurface with the light source, enhancing the multidimensional laser field modulation capabilities of MS‐VCSELs in the 3D space while further promoting the cross‐integration of metasurfaces with optoelectronic devices. It is believed that MS‐VCSELs with amplitude‐phase modulations hold significant promise for applications in 3D imaging, facial recognition, and laser communications. [ABSTRACT FROM AUTHOR]

Semiconductor devices are constructed from stacks of materials with different electrical properties, making deposition of thin layers central in producing semiconductor chips. The shrinking of electronics has resulted in complex device architectures which require deposition into holes and recessed features. A key parameter for such deposition is the step coverage (SC), which is the ratio of the thickness of material at the bottom and at the top. Here, we show that adding a co-flow of a heavy inert gas affords a higher SC for deposition by chemical vapor deposition (CVD). By adding a co-flow of Xe to a CVD process for boron carbide using a single source precursor with a lower molecular mass than the atomic mass of Xe, the SC increased from 0.71 to 0.97 in a 10:1 aspect ratio feature. The concept was further validated by a longer deposition depth in lateral high aspect ratio structures. We suggest that competitive co-diffusion is a general route to conformal CVD. Chemical vapor deposition is used for forming thin layers of materials of various surfaces when making e.g., electronic devices. Here authors show how addition of a heavy inert gas can increase the thickness uniformity of the films on complex objects. [ABSTRACT FROM AUTHOR]

ABSTRACT The insulated gate bipolar transistor (IGBT) is one of the most important power semiconductor devices in power electronics and is also prone to failure. High junction temperature and junction temperature fluctuation of IGBT are the main causes of IGBT module aging failure. The high‐precision monitoring of the junction temperature of the IGBT module is a prerequisite for IGBT life prediction, which is crucial for reducing maintenance costs and improving equipment reliability. Therefore, an IGBT junction temperature estimation method based on long short‐term memory (LSTM) neural network and sliding window estimation model is proposed and applied in practical industrial scenarios. This method uses the operating data of the motor drive device in the actual industrial application scenario as the training and test data set and uses the external operating parameters of the IGBT module to estimate the junction temperature of the IGBT module. Compared with the internal operating parameters of the IGBT module based on switching transient, the external operating parameters are easier to collect and process, and more suitable for practical application scenes. A sliding window estimation model is proposed to estimate the junction temperature of the IGBT module. Compared with the point‐to‐point estimation method, the sliding window estimation method can capture the influence of historical operation data better and has a higher capability of time series data estimation. The IGBT junction temperature estimation of sliding windows is realized by the LSTM neural network, which is more suitable for time series estimation in real industrial scenarios. The experimental results show that the estimation accuracy of the sliding window estimation method is better than that of the point‐to‐point estimation method, and the accuracy of the sliding window estimation method based on LSTM is better than that of the sliding window estimation method based on other machine learning models. It proves that the proposed method can better capture the dynamic process of the system and has higher estimation accuracy. [ABSTRACT FROM AUTHOR]

The structure and dynamics of ferroelectric domain walls are essential for polarization switching in ferroelectrics, which remains relatively unexplored in two-dimensional ferroelectric α-In2Se3. Interlayer interactions engineering via selecting the stacking order in two-dimensional materials allows modulation of ferroelectric properties. Here, we report stacking-dependent ferroelectric domain walls in 2H and 3R stacked α-In2Se3, elucidating the resistance switching mechanism in ferroelectric semiconductor-metal junction devices. In 3R α-In2Se3, the in-plane movement of out-of-plane ferroelectric domain walls yield a large hysteresis window. Conversely, 2H α-In2Se3 devices favor in-plane domain walls and out-of-plane domain wall motion, producing a small hysteresis window. High electric fields induce a ferro-paraelectric phase transition of In2Se3, where 3R In2Se3 reaches the transition through intralayer atomic gliding, while 2H In2Se3 undergoes a complex process comprising intralayer bond dissociation and interlayer bond reconstruction. Our findings demonstrate tunable ferroelectric properties via stacking configurations, offering an expanded dimension for material engineering in ferroelectric devices. The lack of information on the ferroelectric domain walls motion characteristics in α-In2Se3 hampers the understanding of the ferroelectric semiconductor junction device mechanism. Here, the authors report that the stacking order of van der Waals α-In2Se3 determines its ferroelectric domain wall type and phase transition pathway. [ABSTRACT FROM AUTHOR]

Manufacturing semiconductor devices requires advanced patterning technologies, including reactive ion etching (RIE) based on the synergistic interactions between ions and etch gas. However, these interactions weaken as devices continuously scale down to sub‐nanoscale, primarily attributed to the diminished transport of radicals and ions into the small features. This leads to a significant decrease in etch rate (ER). Here, a novel synergistic interaction involving ions, surface‐adsorbed chemistries, and materials at cryogenic temperatures is found to exhibit a significant increase in the ER of SiO2 using CF4/H2 plasmas. The ER increases twofold when plasma with H2/(CF4 + H2) = 33% is used and the substrate temperature is lowered from 20 to −60 °C. The adsorption of HF and H2O on the SiO2 surface at cryogenic temperatures is confirmed using in situ Fourier transform infrared spectroscopy. The synergistic interactions of the surface‐adsorbed HF/H2O as etching catalysts and plasma species result in the ER enhancement. Therefore, a mechanism called "pseudo‐wet plasma etching" is proposed to explain the cryogenic etching process. This synergy demonstrates that the enhanced etch process is determined by the surface interactions between ions, surface‐adsorbed chemistry, and the material being etched, rather than interactions between ion and gas phase, as observed in the conventional RIE. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a new high‐step‐up DC‐DC converter without any coupled inductors or transformers is introduced. The structure of the introduced converter consists of two boost techniques, namely, switched inductor and switched capacitor, used simultaneously. The drawbacks of each technique are mitigated according to the proposed structure and the introduced control method. Therefore, the main contribution of the introduced converter is its ability to use boost techniques while avoiding high input current ripples and inrush currents in the path of semiconductor devices. Thus, there is no need for an auxiliary inductor. Additionally, the number of required components is low, and it benefits from a common ground, which are advantages of this converter in terms of economy and reliability. Another advantage is the high efficiency of the proposed converter in comparison with recent topologies, making it suitable for renewable energy applications such as photovoltaic (PV) systems and fuel cell applications. The proposed converter has been implemented in a laboratory to verify its performance. It operates at 94.51% efficiency with a 200 W output power, a 40 kHz switching frequency, a 40 V input voltage, and a 240 V output voltage. [ABSTRACT FROM AUTHOR]

Herein, the first-principles calculations of defected monolayer graphene-like gallium nitride (g-GaN) were elucidated. The optimized geometric revealed that the nearest-neighbor distances of N-N (between N atoms) and Ga-Ga (between Ga atoms) were narrowing in most configurations. Interestingly, the VGa has a similar atomic symmetry as the pure g-GaN, which is D3h. Most defected configurations are degraded into C2V symmetries, while the Stone-Wales configuration has the lowest symmetry of CS. The formation energies of VNa systems are lower, which implies better energetic stability. For the divacancies, the VGa system is more stable than the VNa system. Moreover, the Stone-Wales configuration is energetically more stable than the interchange configuration. Furthermore, the reaction coordinates represent the geometric evolution of each defected system. The result revealed that the N-atoms are consistent with moving outward while the Ga-atoms move inward only for monovacancies and divacancies configurations. In contrast, the N-atoms move inward while the Ga-atoms move outward for substitutions, interchanges, and Stone-Wales configurations. We believe that this finding will be beneficial as the groundwork for future 2D g-GaNbased semiconductor devices. [ABSTRACT FROM AUTHOR]

With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physics properties, and are promising to be used in non-volatile memory devices. Various kinds of advanced non-volatile memory devices with semiconductor, insulator, ferroelectric, magnetic, and phase-change two-dimensional materials have been investigated in recent years to promote performance enhancement and functionality extension. In this article, the recent advances in two-dimensional material-based non-volatile memory devices are reviewed. Performance criteria and strategies of high-performance two-dimensional non-volatile memory devices are analyzed. Two-dimensional non-volatile memory array structures and their applications in compute-in-memory architectures are discussed. Finally, a summary of this article and future outlooks of two-dimensional non-volatile memory device developments are given. [ABSTRACT FROM AUTHOR]

Silicone gel, used in the packaging of high-voltage, high-power semiconductor devices, generates bubbles during the packaging process, which accelerates the degradation of its insulation properties. This paper establishes a testing platform for electrical treeing in silicone gel under pulsed electric fields, investigating the effect of pulse voltage amplitude on bubble development and studying the initiation and growth of electrical treeing in a silicone gel with different pulse edge times. The relationship between bubbles and electrical treeing in silicone gel materials is discussed. A two-dimensional plasma simulation model for bubble discharge in silicone gel under pulsed electric fields is developed, analyzing the internal electric field distortion caused by the response times of different ions and electrons. Additionally, the discharge current and its effects on silicone gel under pulsed electric fields are examined. By studying the influence of different pulse edge times, repetition frequencies, and temperatures on discharge current magnitude and ozone generation rates, the impact of electrical breakdown and chemical corrosion on the degradation of organic silicone gel under various operating conditions is analyzed. This study explores the macroscopic and microscopic mechanisms of dielectric performance degradation in organic silicone gel under pulsed electric fields, providing a basis for research on high-performance packaging materials and the development of high-voltage, high-power semiconductor devices. [ABSTRACT FROM AUTHOR]

As a transition metal chalcogenide, tantalum sulfide ( TaS x ) is of interest for semiconductor device applications, for example, as a diffusion barrier in Cu interconnects. For deposition of ultrathin nanolayers in such demanding 3D structures, a synthesis method with optimal control is required, and therefore, an atomic layer deposition (ALD) process for TaS x was developed. ALD using (tert)-butylimidotris(dimethylamido)tantalum (Ta [ N (CH 3) 2 ] 3 [ NC (CH 3) 3 ]) as the precursor and an H 2 S-based plasma as the coreactant results in linear growth of TaS x films as a function of the number of cycles for all temperatures in the range 150–400 ° C with growth per cycle values between 1.17 ± 0.03 Å and 0.87 ± 0.08 Å. Saturation of the precursor and plasma dose times, established at 300 ° C, was reached after 20 and 10 s, respectively. Variation of the table temperature or the plasma composition offers the possibility to tune the film properties. At 300 ° C, amorphous TaS 3 films were grown, while addition of H 2 to the plasma led to polycrystalline TaS 2 films. The difference in sulfur content in the films correlates to a change in resistivity, where the least resistive film had the lowest S content. [ABSTRACT FROM AUTHOR]

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Insulated gate bipolar transistors (IGBTs), as an important power semiconductor device, are susceptible to thermal stress, thermal fatigue, and mechanical stresses under high-voltage, high-current, and high-power conditions. Elevated heat dissipation within the module leads to fluctuating rises in temperature that accelerate its own degradation and failure, ultimately causing damage to the module as a whole and posing a threat to operator safety. Through ANSYS Workbench simulation analysis, it is possible to accurately predict the temperature distribution, equivalent stress, and equivalent strain of solder materials under actual working conditions, thus revealing the changing laws of the heat–mechanical interaction in solder materials. Simulation analysis results show that, under steady-state operating conditions, the highest point of the IGBT module's overall junction temperature occurs in the center of the chip. Nanogold exhibited the best performance in terms of temperature and equivalent stress-strain among the five solders studied in this paper; defects near the edges caused greater harm to the module compared to those closer to the solder layer's center. In terms of stress, defects located near the edge corners produced larger strains. Crazing damage in joints allows for a faster transfer of heat sources away from the center; in terms of stress, crazing has fewer detrimental effects on the integrity of the module as compared to through cracks. Simulation analysis can model the interaction of heat and equipment under realistic work conditions, comparing and evaluating different types of solder materials to select the most suitable solder material for product design and material selection. This aids in enhancing design precision and reliability. [ABSTRACT FROM AUTHOR]

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells. [ABSTRACT FROM AUTHOR]

The editorial in Micromachines discusses the latest advancements in semiconductor materials, devices, and systems, emphasizing the importance of both traditional semiconductors like silicon and germanium, as well as next-generation materials such as wide-bandgap semiconductors. The editorial highlights the significant improvements in power electronics achieved through the creation of wide- and ultrawide-bandgap semiconductor materials like silicon carbide and gallium nitride. It also covers topics such as the optimization of GaN-based transistors, advanced modeling methods, trap characterization techniques, and innovations in circuits and systems, showcasing the diverse and pivotal role of semiconductor research in technological progress. [Extracted from the article]

Uncontrolled ion migration is well‐known in perovskite‐based semiconductor devices. Here, it is shown that instead of being detrimental, ion migration can be used to enhance the performance of perovskite CsPbBr3 semiconductor gamma‐ray detectors. Through the deliberate application of electrical biasing, ion migration is actively controlled to modify the metal‐CsPbBr3 interface barrier height in devices with asymmetric electrodes. Ion migration plays a pivotal role in reducing bulk defects, as evidenced by the contact potential difference measurement, thermally stimulated current spectroscopy and photoluminescence measurements. The evidence suggests that biasing‐induced ion migration in CsPbBr3 results in a reduction in electron traps and significant detector improvement. As biasing at elevated temperatures expedites ion migration, preconditioning the CsPbBr3 crystals through reverse biasing is a promising strategy for enhancing their energy‐resolving performance. [ABSTRACT FROM AUTHOR]

Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages. [ABSTRACT FROM AUTHOR]

An improved 4H‐SiC SBD‐wall‐integrated trench metal‐oxide‐semiconductor (SWITCH‐MOS) with n‐bury and split‐gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n‐bury layer can smooth the path to current conduction, which reduces the specific on‐resistance (RON, SP) and improves static characteristics. Besides, the split‐gate is able to transform the gate‐drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH‐MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH‐MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only −1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 mΩ·nC, which is attractive for the application in power inverters. [ABSTRACT FROM AUTHOR]

The lack of an MMC reliability evaluation approach that incorporates data on essential components' health monitoring in the already related research prevents reliability from being further improved. Therefore, this article proposes a real‐time reliability evaluation method of the multi‐state IGBT module in MMC through iterative calculation of the Markov chain model. The degradation process of the IGBT module is divided into multiple states based on the monitored bond wire failure, and the failure rate of the IGBT module is updated in real time using the accumulated monitoring data of junction temperature. The proposed method can more accurately reflect the real state of MMC compared with the binary state evaluation method. Besides, a multi‐channel high‐speed data acquisition board is designed to measuring the gate voltage and collector voltage of the IGBT for the health evaluation of IGBT modules in MMC; the typically measured results validate the effectiveness of the data acquisition board. [ABSTRACT FROM AUTHOR]

The rapid advancement of main group III–V nanomaterials endows photodetectors (PDs) with enhanced performance. At present, various III–V nanomaterials are systematically investigated, whereof III–V semiconductors have attracted a successively increased attention that calls for a comprehensive summary which also can define the state‐of‐art for their further development. Herein, this work systematically introduces and discusses key aspects of the field. First, the advanced strategies for the preparation of III–V semiconductor materials and the device structures of the subsequent PDs based on these materials, pristine and doped, are addressed. The focus is then turned to their performance under the irradiation of various wavelengths, separately summarizing and comparing the photodetection properties under infrared, UV and visible light. Finally, challenges and future perspectives of III–V semiconductor‐based PDs are highlighted. This review enlightens the development of III–V semiconductor‐based PDs, and their extended applications for optoelectronic devices in general. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) characteristics of semiconductor devices pose a significant importance for understanding their working principle, particularly concerning material imperfections. Accordingly, substantial research endeavors have focused on characterizing the LFN of devices. However, the LFN characteristics of the ambipolar transistors have been rarely demonstrated. Herein, we investigate the effects of ambipolar carrier transport and CYTOP-induced p-type doping on low-frequency noise characteristics of MoTe2 transistors. The source of the 1/f noise differs between the n-type (electron transport) and p-type (hole transport) modes. Notably, the influence of contact resistance is more pronounced in the n-type mode. CYTOP doping suppresses the n-type mode by introducing hole doping effects. Furthermore, CYTOP doping mitigates the impact of contact resistance on excess noise. [ABSTRACT FROM AUTHOR]

Nanotwinned Cu (NT-Cu) is a promising candidate for Cu redistribution lines (RDLs). However, oxidation in NT-Cu lines is of concern because it increases electrical resistance and endangers the reliabilities of semiconductor devices such as temperature cycling tests (TCTs). In order to enhance the reliabilities, the passivation of NT-Cu lines is needed. In this study, immersion Ag/Sn and plasma-enhanced chemical vapor deposition (PECVD) SiCN were used to passivate the surfaces of NT-Cu RDLs at low operating temperatures (60 °C for immersion and 150 °C for PECVD). We found that Ag- and SiCN-capped NT-Cu lines showed negligible changes in microstructures and resistance after TCTs. As for Sn-coated NT-Cu lines, the resistance remained stable after 250 cycles of TCTs, with low oxygen signals detected. These three coating layers can block oxygen and moisture, effectively preventing oxidation and maintaining the resistance of NT-Cu RDLs during the TCT. The findings demonstrate the effectiveness of Ag, Sn, and SiCN coatings in enhancing reliability, providing options for passivation layers of NT-Cu RDLs. [ABSTRACT FROM AUTHOR]

In this paper, a mathematical model of semiconductor device with two important factors is discussed. Heat and magnetic influences are considered together. Its numerical approximation is important in information science and other technological innovation fields. The major physical unknowns (the potential, electron concentration, hole concentration, and the heat) are defined by four nonlinear PDEs: an elliptic equation, two convection-diffusion equations and a heat conductor equation. A conservative block-centered method is used to approximate the elliptic equation. The derivatives to time t , ∂ ∂ t (⋅) , are discretized by multistep differences for improving the computational accuracy. The diffusions and convection terms are treated by block-centered differences and upwind approximations, respectively. This composite numerical method is suitable for this nonlinear system. Firstly, numerical dispersion and nonphysical oscillations are avoided. Secondly, the unknowns and their adjoint vectors are obtained simultaneously. Thirdly, the law of conservation is preserved. An error estimates is derived. Finally, simple examples are given for showing the efficiency and accuracy. [ABSTRACT FROM AUTHOR]

In this paper, a novel structure of self-voltage balanced switched-capacitor-based seven-level inverter (SVB-SCSLI) is proposed for asymmetrical input energy source applications. SVB-SCSLI develops a seven-level staircase waveform with a minimum number of semiconductor devices compared to existing multilevel inverters (MLIs). The proposed converter is more suitable for the solar PV system where unequal DC voltage sources are available. The SVB-SCSLI also resolves the main difficulty of connecting many inverters in parallel to achieve staircase voltage. Besides, it attains voltage balancing capability at DC-link by holding constant capacitor voltage at every cycle. The detailed loss and steady-state analysis of the SVB-SCSLI are examined. Furthermore, the proposed converter's efficiency improves with better power quality than other topologies reported in the literature. Finally, a prototype is fabricated, and experimental results are presented to validate the feasibility of SVB-SCSLI. [ABSTRACT FROM AUTHOR]

Nonradiative recombination at the front contact interface of kesterite solar cells hinders the extraction of photo‐generated carriers, significantly restricting the efficiency enhancement. However, identifying the recombination centers and proposing effective passivation strategies remain open questions. First‐principles calculations combining with nonadiabatic molecular dynamics (NAMD) simulations unveil that the interfacial translational symmetry breaking in elemental valence states leads to a detrimental donor‐like Cu2ZnSnS4/CdS interface with deep states originating from the interfacial Sn‐5s orbital, which serve as significant nonradiative recombination centers. Here, two mechanisms are proposed for eliminating the deep interface states: 1) directly replacing Sn‐5s with higher outer orbital levels by substituting group IIIA elements (In and Ga) for the interfacial Sn atom; 2) introducing an extra defect‐level coupling with Sn‐5s by substituting group VA elements (N, P, and As) for the S atoms bonded with the interfacial Sn atom. The representative InSn and PS acceptor defects, which are energetically favorable at the detrimental donor‐like interface, effectively passivate the deep interface states, markedly improving the carrier lifetimes by weakening nonadiabatic coupling between the band edge and the interfacial states. This study reveals the origin of the interfacial nonradiative recombination of kesterite solar cells and offers insights into interfacial passivation in semiconductor devices. [ABSTRACT FROM AUTHOR]

In this study, a 13‐level switched‐capacitor inverter with triple voltage gain is proposed. The proposed structure generates 13‐level output voltage using only one DC source, eleven switches, and three capacitors. The capacitors have the capability of self‐balancing without the use of additional circuits or complex control methods. Additionally, the inrush current of the capacitors has been reduced using a soft charging method. The proposed structure has been compared with different 13‐level structures presented in recent studies in terms of various parameters such as the number of semiconductor devices, the number of DC sources, voltage gain, Maximum Blocking Voltage (MBV), and Total standing Voltage (TSV). Another advantage of the proposed structure is the non‐use of any diode and its cost‐effectiveness. In addition, the power losses of the proposed structure have been evaluated, and its efficiency has been calculated for various output powers. Finally, the performance of the proposed structure has been verified through simulation and laboratory implementation under both stable and various dynamic conditions. [ABSTRACT FROM AUTHOR]

Fast and non-destructive analysis of material defect is a crucial demand for semiconductor devices. Herein, we are devoted to exploring a solar-cell defect analysis method based on machine learning of the modulated transient photovoltage (m-TPV) measurement. The perturbation photovoltage generation and decay mechanism of the solar cell is firstly clarified for this study. High-throughput electrical transient simulations are further carried out to establish a database containing millions of m-TPV curves. This database is subsequently used to train an artificial neural network to correlate the m-TPV and defect properties of the perovskite solar cell. A Back Propagation neural network has been screened out and applied to provide a multiple parameter defect analysis of the cell. This analysis reveals that in a practical solar cell, compared to the defect density, the charge capturing cross-section plays a more critical role in influencing the charge recombination properties. We believe this defect analysis approach will play a more important and diverse role for solar cell studies. [ABSTRACT FROM AUTHOR]

This work presents the effect of temperature change on the capacitance of silicon PIN diodes and the resulting change in performance of RF limiters at very high frequency (VHF). Device temperatures were varied between −25 ºC and 100 ºC, with small‐signal parameters (including device capacitance) extracted at regular temperature increments and bias voltages from −20 Vdc to +3 Vdc using a multi‐bias parameter extraction method. It was found that the junction capacitance of the four PIN diodes under investigation increases with temperature, as expected from carrier lifetime behaviour, while results also confirmed prior observations of an inverse relationship between forward‐biased series resistance and temperature. Devices were subsequently tested in two different limiter topologies through high‐power transient measurements. It was found that the combination of increased capacitance and decreased resistance with increasing temperature increases the transient spike leakage and decreases the flat leakage of a limiter. It was also concluded that, for VHF, an anti‐parallel topology provides the best performance over a wide range of temperatures. [ABSTRACT FROM AUTHOR]