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Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

In this letter, we develop a compact thermal model that can predict changes in the threshold voltage and drain current because of the junction temperature, Δ $T_{J}$ , and its effect on a circuit performance by using circuit simulators. In addition, we propose a thermally aware layout methodology for FinFET-based digital circuits. Although heat sinks (called “via pillars”) are generally used for heat dissipation in FinFETs, these features increase the parasitic capacitance and power consumption. Therefore, we propose an optimized heat sink that is only on the critical node (showing high activity and drain–source voltage, $V_{DS}$ ) and uses high metal stacks up to metal 5. With the optimization of this heat sink, we observe that the $T_{J}$ of a 4-input NAND gate can be reduced about 3.2% while the oscillation frequency of an 11-stage ring oscillator can be increased about 12%, compared to conventional heat sinks.

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

Since cache side-channel attacks have been serious security threats to multi-tenant systems, there have been several studies to protect systems against the attacks. However, the prior studies have limitations in determining only the existence of the attack and/or occupying too many computing resources in runtime. We propose a low-overhead pinpointing solution, called RT-Sniper, to overcome such limitations. RT-Sniper employs a two-level filtering mechanism to minimize performance overhead. It first monitors hardware events per core and isolates a suspected core to run a malicious process. Then among the processes running on the selected core, RT-Sniper pinpoints a malicious process through a per-process monitoring approach. With the core-level filtering, RT-Sniper has an advantage in overhead compared to the previous works. We evaluate RT-Sniper against Flush+Reload and Prime+Probe attacks running SPEC2017, LMBench, and PARSEC benchmarks on multi-core systems. Our evaluation demonstrates that the performance overhead by RT-Sniper is negligible (0.3% for single-threaded applications and 2.05% for multi-threaded applications). Compared to the previous defense solutions against cache side-channel attacks, RT-Sniper exhibits better detection performance with lower performance overhead.

Recently, many kinds of tremendous requirements are needed for smart Internet of Things (IoT). Among them, an intelligent and self-working CMOS image sensor (CIS) is a key component to satisfy the specifications of smart IoT. In this paper, therefore, an intelligent CIS with a deep learning algorithm is discussed. With a deep learning and a variable pixel recognition algorithm, an intelligent CIS has been implemented. Even though a low resolution image is obtained, a high resolution image can be taken by the proposed deep learning algorithm. As well as the intelligent CIS chip has been fabricated with a 90nm Samsung CIS technology, the power consumption is extremely low by about 1.0mW with a VGA graphic mode.

Lithium metal is one of the most promising next generation anode materials to make a leap of the energy density of conventional lithium-ion batteries. However, lithium metal has fatal problems to overcome in cycling stability and safety. In this study, lithium metal is pre-treated to form a lithium borate layer (LBL) on the surface to suppress dendritic growth of lithium and stabilize the interface between the carbonate-based electrolyte and anode. The pre-treated lithium metal greatly enhances the cycling stability of the cells (Li || Li symmetric and LiMn2O4 (LMO) || Li cells). Especially, cycling test with the LMO || Li cell reveals the pre-treatment with boric acid is more effective approach than addition of boric acid in the electrolyte because water is continuously generated during charge/discharge in the latter case and it causes side reactions and degrades the cycling performance. The LBL along with LiF stabilizes the solid electrolyte interface (SEI) layer and suppresses the dendritic growth of lithium. Due to the lithium-ion conducting ability of lithium borate, the pre-treated lithium anode also shows lower interfacial resistance than the pristine lithium and enhances rate capability.

In this paper, a hybrid column segmented CMOS image sensor (CIS) with an artificial intelligence (AI) core and a novel SRAM readout circuit is presented. To obtain a high performance and high speed column parallel CIS, each column is segmented into two parts: the first one is a DC reference voltage generator with a bandgap reference circuit, and the second one is a fine ramp generator with an AI core and a digital-to-analog converter (DAC). Further, a novel SRAM readout circuit to improve the speed of digital block is also discussed. Based on this hybrid column segmented technique, excellent measured results are reported. With a 90nm backside illumination (BSI) technology, a 12-bit resolution image quality and 407uW power consumption per column are satisfied.

In this paper, we propose a nano-ampere current sensing technique for organic light-emitting diode (OLED) mobile displays. The nano-ampere current sensing system consists of a current integrator and an 8-bit single-slop analog to digital converter (SS-ADC). In order to reduce area and power consumption, the current integrator and a comparator of the SS-ADC share an amplifier, called differential difference amplifier (DDA). From the experimental results, we obtain 399.21 pA of accuracy with 8-bit current sensing resolution ranged from 0 to 102.2 nA. The proposed current sensing circuit was fabricated with a 90 nm CMOS technology and chip size is about 600 μm × 3000 μm.

A smart image sensor system with a current-steering digital-to-analog converter (DAC) for autofocusing micro-lens driver is presented. Recently, most of smart image sensor systems want to extend the lens focusing distance with high speed motor drive. Thus they need a high-performance current-steering DAC to drive the lens focusing linear motor. In order to satisfy the specifications, DAC needs small chip area, low power consumption, and high speed operation. In this paper, a brick current cell layout technique and a novel digital logic are proposed. The measured results are within ±0.6LSB for INL, and within ±0.5LSB for DNL. Further, the measured SFDR is 79dB at 1.2MHz output frequency with 250MHz clock frequency. It has 45.6mW power dissipation at 3.3V power supply.

A novel priority encoding technique with an address-encoder and reset-decoder(AERD) for a hierarchical asynchronous detector is discussed. Conventionally, an asynchronous detector has a slow operating speed, because it checks and takes the only activated cells. In order to enhance the data transfer rates, an improved hierarchical asynchronous detector is proposed. Further, a low power priority encoding technique with an AERD is also described. A test chip to verify the proposed technique has been fabricated with a Hynix 0.18um CMOS technology. The power consumption is about 7.5mW, which is much smaller than the conventional ones at the same patterns.

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/?2.0 LSB and DNL is within +1.0 LSB/?1.0 LSB.

This brief describes a CMOS current-steering digital-to-analog converter (D/A converter, DAC) with a full-swing output signal. Generally, a normal current-steering DAC cannot have a full-swing output signal because conventional DACs have an inevitable voltage drop at the output current cell. In order to improve the drawbacks, we propose a new scheme of quaternary driver and an output current cell composed of both nMOS and pMOS. First, the nMOS operates from the power supply to the half of the power supply. Second, the pMOS operates independently from the half of the power supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. A 6-bit 1-GS/s current-steering DAC has been fabricated with Dongbu 0.11-μm 1-poly 6-metal (1P6M) CMOS technology to verify the performance of the proposed full-swing DAC. The effective chip area is 0.46 mm2, and power consumption is about 19.1 mW. The measured results reveal that the DAC has a full-swing output signal.

In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 mu m CIS technology and it has the VGA resolution of 640 x 480. The measured conversion time is 16 mu s, and a high frame rate of 131 fps is achieved at the VGA resolution.

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 × 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).

Design of a configurable bit-resolution CMOS image sensor(CIS) is described. Recently, CIS pixel matrixes composed of both RGB and Infrared(IR) color filters are used for the implementation of an image depth extraction. However, in order to compensate the light density between RGB and IR, the single-slope ADC inside of CIS must have a configurable bit-resolution. For example, RGB signal has a 8-bit resolution, while IR signal has an 12-bit resolution. The proposed CIS has 4 different bit resolutions for RGB pixel, such as 8-bit, 6-bit, 4-bit and 2-bit. The proposed ADC has a maximum resolution of 12-bit for IR pixels with the architecture of two-step single-slope(TS SS) type. The proposed CIS has a 100MHz clock, and it has been designed with 0.18μm CIS technology.

Recently, CMOS Image Sensor (CIS) is now widely used in the field of security system. Normally, in an emergency state, a security system must record a picture in a high resolution mode. On the contrary, in a normal state without any events or accidents, it can take a picture in a low resolution mode. In this paper, a variable resolution CIS is described to implement a smart security system. A variable resolution CIS chip has been fabricated with a Samsung 0.13µm CMOS technology and it satisfied a QVGA resolution (320×240) with a pitch of 5.0 µm and a 4-Tr active-pixel sensor structure. The measured frame rate is 60 frame/s with a power consumption of 9.8mW at 2.8V(Analog)/1.5 V(Digital) power supply. When the variable resolution technique is adopted, the power consumption is about 2.7mW at the low resolution mode. Further, the chip area is about 19mm2.

An 8-bit 2GS/s 250mW low power folding A/D converter(ADC) with a 45nm CMOS technology is described. In order to reduce the power consumption, a new folding block with a shut-down circuit is proposed. The role of shut-down circuit selectively cuts off the power supply of folding amplifiers, according to the input analog voltage. Further, an adaptive digital error correction technique is discussed to reduce the code errors. The proposed ADC has been fabricated with a 1.2V 45nm 1-poly 8-metal CMOS process. The effective chip area is 1.98mm2 (ADC core : 1.1mm2, Calibration : 0.88mm2) and the power consumption is about 250mW. The measured SNDR is 46dB at the conversion rate of 2GS/s. The measured values of INL and DNL are within 2.5LSB and 1.0 LSB, respectively.

A CMOS Image Sensor (CIS) mounted on a surveillance system does not always record a picture in a high resolution mode. In a normal state without any events or accidents, it is possible to take a picture in a low resolution mode to reduce power consumption. In this paper, a novel low power CIS which has two kinds of resolution mode is discussed to implement an intelligent surveillance system. Further, a pixel sub-sampling and a column shut-down technique are proposed. The prototype CIS chip is based on a 0.1μm CMOS process and satisfies a QVGA resolution (320×240) with a pitch of 5.0 μm and a 4-Tr active-pixel sensor structure. The fabricated CIS is composed of an analog correlated double sampling (CDS), an 8-bit single-slope ADC, and a digital counter. The operating speed of the CIS is 50 frame/s with a power consumption of 9.8mW at 2.8V(Analog)/1.5 V(Digital) power supply. When the pixel-configurable technique is used, the power consumption is about 2.7mW in a 1/4 low resolution mode. Therefore, the power consumption is drastically reduced, when the proposed technique is adopted.

This paper describes a CMOS current steering digital-to-analog converter (DAC) with a full-swing output signal. Generally, a normal current steering DAC cannot have a full swing output signal, because conventional DACs have an inevitable voltage drop at the output current cell. In order to improve the drawbacks, we propose a new scheme of quaternary driver and an adaptive output current cell composed of both nMOS and pMOS. As well as the nMOS operates from the power supply to the half of the power supply, the pMOS operates independently from the half of the power supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver which selects the optimized current cell. A 6-bit 1GS/s current steering DAC has been fabricated with Dongbu 0.11um 1-poly 6-metal CMOS technology to verify the performance of the proposed full-swing DAC. The effective chip area is 0.46mm2 and power consumption is about 19.1mW. The measured results reveal that the DAC has a full swing output signal.

In order to raise the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, a fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a one-shot digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13μm CIS technology and it has the VGA resolution of 640×480. The measured conversion time is 16 μs, and a high frame rate of 131fps is achieved at the VGA resolution.