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In this article we will approach the soft-decision decoding for the linear block codes, is a kind of decoding algorithms used to decode data to form better original estimated received message, it is considered as a NP-hard problem. In this article we present a new decoder using memetic algorithm such metaheuristic technic operates on the dual code rather than the code itself that aims to find the error caused when sending a codeword calculated from a message of k bits of information, the resulting codeword contains n bits, including the redundancy bits, the efficiency of an error-correcting code is equivalent to the ratio k/n, the rate is belong the interval [0,1]. Hence a good code is the one that ensures a certain error correcting capability at minimum ratio. The results proved that this approach using a combination of genetic algorithm and local search algorithm provides a sufficiently good solution to an optimization problem; the new decoder is applied on linear codes where the structure is given by a parity check matrix. [ABSTRACT FROM AUTHOR]

This study provides necessary condition (lower bound) and sufficient condition (upper bound) for the existence of Solid Burst (SB) errors locating PCD’s codes within a sub-block where the length of the code is assumed that it is split up into a fix number of identically sized sub-blocks. An example of such a code is also provided. The codes obtained here have been compared with the previously existing codes that are capable to detect and locate the repeated burst errors. [ABSTRACT FROM AUTHOR]

SRAM memory systems are suffering from an increase in data due to the aggressive CMOS integration density. The frequency of Multiple Cell Upsets (MCUs) on SRAM memory is increasing, which is resulting in the increasing use of ECCs.Speed is slowed down by ECCs due to their overhead, both in memory bits and decoding times. In this research, Continuous Adjacent Multiple Bit Upset Correction (CAMBUC)has been proposed to greatly reduce the redundancy and improve correction coverage.In addition, the Interleaved Counter Matrix Code (ICMC) is proposed to simplify the Encoder and decoder circuits which reduces the delay. The proposed method predicts MBU before decoding and maximum parallel 8 error bits are corrected using the proposed method. Using this method, the error correction code's parity check matrix is automatically and effectively constructed, simply stating its error detection and/or correction capabilities. Combinatorial counting operations introduce error detection and error prediction. The proposed ICMC makes use of the decimal and hamming algorithms to achieve the highest level of error detection. In comparison to the conventional decoder, which can rectify double and 8-adjacent errors, the assessment results utilizing the proposed CAMBUC approach demonstrate significant reductions in area, power, and delay. The obtained findings demonstrate that the proposed method has a comparatively long mean time to failure (MTTF) when compared to existing approaches. At the same time, the suggested scheme's delay overhead is, respectively, 20.5%, 14.6%, 11.2%, 8.5%, and 3.5% less than that of the existing Hamming, CMC, ECC for 5-bit adjacent error, eMRSC, and DICE-7-bit ECCmethods. [ABSTRACT FROM AUTHOR]

Quantum error correction lies at the heart of building reliable quantum information processing systems. Stabilizer codes, a fundamental class of quantum errorcorrecting codes, play a pivotal role in mitigating the adverse effects of noise and decoherence in quantum systems. This paper introduces a novel construction of quantum stabilizer codes using Hadamard difference sets, an elegant mathematical concept derived from combinatorial design theory. In this paper, the construction of the quantum stabilizer codes over non- cyclic Hadamard difference sets with parameters (4m²,2m²-m, m²-m), where m is a positive integer is discussed. Firstly, the parity check matrices are constructed from the Circulant permutation matrices with the help of Hadamard difference sets and then, the Symplectic inner product condition for Hadamard difference sets over binary operation for parity check matrices are obtained to affirm the commutative condition for Stabilizer operators which is vital for the error detection. For application, we constructed a Hadamard difference sets with parameters (16,6,2) for m = 2 of ordered pair of the group Z2 Z8 × (non-cyclic group) and quantum stabilizer codes are obtained by parity-check matrix. [ABSTRACT FROM AUTHOR]

A column‐weight k$k$ LDPC code with the parity‐check matrix H$H$ is called decomposable if there exists a permutation π$\pi$ on the rows of H$H$, such that π(H)${\pi }(H)$ can be decomposed into k$k$ column‐weight one matrix. In this paper, some variations of edge coloring of graphs are used to construct some column‐weight three decomposable LDPC codes with girths at least six and eight. Applying the presented method on several known classes of bipartite graphs, some classes of column‐weight three decomposable LDPC codes are derived having flexibility in length and rate. Interestingly, the constructed parity‐check matrices based on the proper edge coloring of graphs can be considered as the base matrix of some high rate column‐weight three quasi‐cyclic (QC) LDPC codes with maximum‐achievable girth 20. The paper also leads to a simple characterization of elementary trapping sets of the decomposable codes based on the chromatic index of the corresponding normal graphs. This characterization corresponds to a simple search algorithm finds all possible existing elementary trapping sets in a girth‐6 or girth‐8 column‐weight 3 LDPC code which are layered super set of a short cycle in the Tanner graph of the code. Simulation results indicate that the QC‐LDPC codes with large girths lifted from the constructed base matrices have good performances over AWGN channel. [ABSTRACT FROM AUTHOR]

In this paper, we construct new types of codes, called Weighted Block-wise Burst Error Correcting Codes (Weighted BBEC Codes), which are an improvement on the previously known block wise burst error correcting codes in the sense of their weight, i.e., (n = n1 + n2, k) linear codes that correct all the bursts of length b1 (fixed) with the weight w1(w1 ≤ b1) or more (less) in the first sub-block of length n1 and all the bursts of length b2 (fixed) with the weight w2 or more (less) in the next sub-block of length n2. [ABSTRACT FROM AUTHOR]

A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication. [ABSTRACT FROM AUTHOR]

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]

Copyright of Informatics Control Measurement in Economy & Environment Protection / Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska is the property of Lublin University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a joint source–channel image transmission model based on a modified trellis construction using variable-length and fixed-length codes. The model employs linear block trellis codes and a modified Bahl–Cocke–Jelinek–Raviv algorithm for decoding in the source channel. Additionally, this model utilizes a hierarchical tree and a parity-check matrix to combine the source and channel codes, reducing errors in the decoding process and enabling the decoding of longer sequences without substantial loss of quality. [ABSTRACT FROM AUTHOR]

...-ispotty-byte error correcting codes over Zq [7] are non-binary codes generalizing the binary irregular-spotty-byte codes [3] suitable for semiconductor memories in which a word is divided into irregular bytes not necessarily of the same length. The distance between distinct words is measured in terms of newly defined ... - metric function [7]. In this paper, we present the code construction methods of ...-ispotty-byte error correcting codes in terms of their parity check matrix. [ABSTRACT FROM AUTHOR]

In modern large-scale storage systems, locally repairable codes(LRCs) improve the repair efficiency when node failure occurs. This work discusses several new methods for constructing LRCs with small localities using the generator and parity-check matrices approach. Many new LRCs have been found, all distance-optimal (d-optimal) or best-known (BK). Based on the newly obtained LRCs and known results, a database presenting all d-optimal (or BK) binary LRCs with a relatively small locality where n ≤ 40 is given. The majority of them are r-optimal or near r-optimal. [ABSTRACT FROM AUTHOR]

Reed Solomon codes were standardized for numerous wireless communication systems. Most practical Reed Solomon codes belong to non-binary linear block codes defined over finite fields with characteristic two. Each linear block code contains one codeword composed of all zeros. The concatenation of this and also other codewords can lead to long, theoretically even infinite, runs of equal symbols. Such long runs do not support synchronization in wireless receivers and therefore are unwanted. In this paper it is shown that extended and some appropriately shortened Reed Solomon codes constructed over finite fields with characteristic two can be transformed into Run Length Limited Reed Solomon codes. The presented method, if applicable, allows for doing it without inserting additional redundancy. Another advantage is that after the transformation, if some round conditions are fulfilled, the decoding does not have to be rebuilt. [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10-10 at 3.5 dB Eb/N0 than conventional LDPC codes, which showed a BER of 10-7 at 3 dB Eb/N0. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10-6 at 4.2 Eb/N0 was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

In this work, we determine new linear equations for the weight distribution of linear codes over finite chain rings. The identities are determined by counting the number of some special submatrices of the parity-check matrix of the code. Thanks to these relations we are able to compute the full weight distribution of codes with small Singleton defects, such as MDS, MDR and AMDR codes. [ABSTRACT FROM AUTHOR]

Nested linear coding is a widely used technique in wireless communication systems for improving both security and reliability. Some parameters, such as the relative generalized Hamming weight and the relative dimension/length profile, can be used to characterize the performance of nested linear codes. In addition, the rank properties of generator and parity-check matrices can also precisely characterize their security performance. Despite this, finding optimal nested linear secrecy codes remains a challenge in the finite-blocklength regime, often requiring brute-force search methods. This paper investigates the properties of nested linear codes, introduces a new representation of the relative generalized Hamming weight, and proposes a novel method for finding the best nested linear secrecy code for the binary erasure wiretap channel by working from the worst nested linear secrecy code in the dual space. We demonstrate that our algorithm significantly outperforms the brute-force technique in terms of speed and efficiency. [ABSTRACT FROM AUTHOR]

Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication. As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs). Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data. This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms. The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology. From the outcomes of this study, the MinSum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations. The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem. The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications. Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems. The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations. This positions it as a promising candidate for optimizing data communication systems. The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem. [ABSTRACT FROM AUTHOR]

In this paper, new spectral optical codes based on the construction parity check matrix of LDPC codes were designed and implemented in an optical code-division multiple access communication system. Two types optical family codes can be obtained with respectively a cross correlation of λ c = 0 and λ c = 1. In each case, the codes can either be decoded using the direct detection or the balanced detection. Performance was evaluated by referring to the Q factor, the bit error rate and the eye pattern diagrams using Optisystem 9.0. [ABSTRACT FROM AUTHOR]

The traditional LDPC encoding and decoding system is characterized by low throughput and high resource consumption, making it unsuitable for use in cost-efficient, energy-saving sensor networks. Aiming to optimize coding complexity and throughput, this paper proposes a combined design of a novel LDPC code structure and the corresponding overlapping decoding strategies. With regard to structure of LDPC code, a CCSDS-like quasi-cyclic parity check matrix (PCM) with uniform distribution of submatrices is constructed to maximize overlap depth and adapt the parallel decoding. In terms of reception decoding strategies, we use a modified 2-bit Min-Sum algorithm (MSA) that achieves a coding gain of 5 dB at a bit error rate of 10 − 6 compared to an uncoded BPSK, further mitigating resource consumption, and which only incurs a slight loss compared to the standard MSA. Moreover, a shift-register-based memory scheduling strategy is presented to fully utilize the quasi-cyclic characteristic and shorten the read/write latency. With proper overlap scheduling, the time consumption can be reduced by one third per iteration compared to the non-overlap algorithm. Simulation and implementation results demonstrate that our decoder can achieve a throughput up to 7.76 Gbps at a frequency of 156.25 MHz operating eight iterations, with a two-thirds resource consumption saving. [ABSTRACT FROM AUTHOR]

In this article, a graph-theoretic method (taking advantage of constraints among sets associated with the corresponding parity-check matrices) is applied for the construction of a double low-density parity-check (D-LDPC) code (also known as LDPC code pair) in a joint source-channel coding (JSCC) system. Specifically, we pre-set the girth of the parity-check matrix for the LDPC code pair when jointly designing the two LDPC codes, which are constructed by following the set constraints. The constructed parity-check matrices for channel codes comprise an identity submatrix and an additional submatrix, whose column weights can be pre-set to be any positive integer numbers. Simulation results illustrate that the constructed D-LDPC codes exhibit significant performance improvement and enhanced flexible frame length (i.e., adaptability under various channel conditions) compared with the benchmark code pair. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of a low-complex iterative symbol-level decoding scheme for Reed-Solomon codes. Most soft-decision iterative decoders for Reed-Solomon codes work on a bit level due to the efficient passing of soft information due to the sparsity of the binary parity check matrix. These decoders yield a good error correction performance, but this comes at the cost of an increased computational complexity resulting from working at a bit-level. This study aims to lower the computational complexity of iterative decoding of Reed-Solomon codes by introducing a high-performance soft-decision iterative Reed-Solomon decoder that works on a symbol-level, in contrast to the bit-level implementation used in most iterative Reed-Solomon decoders. The proposed algorithm utilises soft information to decode while applying information set decoding techniques to an extended parity check matrix. The use of the extended parity check matrix provides additional parity check equations which assist the algorithm in determining the correct information set of symbols used in the decoding process. For a given (n , k) Reed-Solomon code, the algorithm converges to a valid codeword by correctly decoding a specified information set of k symbols from the received vector. Simulations run show the proposed algorithm performs favourably when compared to other symbol-level iterative decoders while working at a relatively lower complexity. [ABSTRACT FROM AUTHOR]

In this paper, two polar code-based identification schemes are proposed in which the polar codes are used instead of random codes. The security of the proposed identification schemes is based on the hardness of coding problems such as general decoding problem (GDP) and syndrome decoding problem (SDP). By exploiting the properties of polar codes in the proposed identification schemes, it does not need to save the parity check or generator matrix of polar codes completely as a public data. Therefore, the public data size of the proposed identification schemes is reduced up to 90% in comparison with the Stern and Veron identification schemes. Also, by using the efficient techniques of seed generation and compression, it is shown that the communication costs of the proposed identification schemes are reduced up to 53% compared to the Stern and Veron identification schemes. Moreover, security analyses show that the proposed identification schemes have low cheating probability and also have proper resistance against information set decoding attack. [ABSTRACT FROM AUTHOR]

The large number of inexpensive and energy-efficient terminals in IoT systems is one of the emerging elements of the recent landscape of information and communication technologies. IoT nodes are usually embedded systems with limited processing power devices and strict requirements on energy consumption. In this paper, we consider the design and implementation of a part of the IoT communication uplink stack, namely the error correction coding scheme, for energy-efficient operation. We examine how an efficient rate-adaptive coding scheme, namely the Raptor-like (RL) quasi-cyclic (QC) subclass of low-density parity check (LDPC) codes, can be applied. We present an encoding algorithm designed for an embedded CPU; a respective QC-RL-LDPC decoding scheme, based on typical LDPC iterative decoding; and a combined design procedure for construction of the QC-RL-LDPC parity check matrices. Next, we conduct experiments to explore the time intervals for implemented encoding and the goodput of the coding system with incremental redundancy. We provide the statistical results by combining the measured energy consumption of the encoder and the simulated radio transmitter energy consumption. We demonstrate the comparison of normalized energy consumption statistics with the fixed-rate LDPC coding case. As conclusion, we note that under an unknown channel corruption level, the short block QC-RL-LDPC code implemented in the CPU can achieve higher energy efficiency per information bit compared to a fixed-rate LDPC code. Future work will include an extension of the work to nonbinary QC-RL-LDPC coding design. [ABSTRACT FROM AUTHOR]

Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively. [ABSTRACT FROM AUTHOR]

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance t -bit Burst Error Correcting (BEC) codes. Parity check matrices (H) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting t -bit burst errors caused by MCUs. [ABSTRACT FROM AUTHOR]

The goal of this paper is to construct the linear code, and its dual which corresponding to classification of projective line PG(1,31), we will present Some important results of coding theory, the generator matrix of every linear code in PG(1,31) is found, A parity check matrix is also found . The mathematical programming language GAP was a main computing tool . [ABSTRACT FROM AUTHOR]

This paper proposed a novel method for constructing quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC‐LDPC codes. Investigations revealed that the proposed large‐sized QC‐LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10−10 at 3.5 dB Eb/N0 than conventional LDPC codes, which showed a BER of 10−7 at 3 dB Eb/N0. Subsequently, implementation of the proposed QC‐LDPC code in a software‐defined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10−6 at 4.2 dB Eb/N0 was achieved. Then, the performance of the proposed codes based on their encoding–decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed–Solomon codes. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Chongqing University of Posts & Telecommunications (Natural Science Edition) is the property of Chongqing University of Posts & Telecommunications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Since their rediscovery in the early 1990s, low-density parity-check (LDPC) codes have become the most popular error-correcting codes owing to their excellent performance. An LDPC code is a linear block code that has a sparse parity-check matrix. Cycles in this matrix, particularly short cycles, degrade the performance of such a code. Hence, several methods for counting short cycles in LDPC codes have been proposed, such as Fan’s method to detect 4-cycles, 6- cycles, 8-cycles, and 10-cycles. Unfortunately, this method fails to count all 6- cycles, i.e., ignores numerous 6-cycles, in some given parity-check matrices. In this paper, an improvement of this algorithm is presented that detects all 6-cycles in LDPC codes, as well as in general bipartite graphs. Simulations confirm that the improved method offers the exact number of 6-cycles, and it succeeds in detecting those ignored by Fan’s method.

Abstract The problem of blind phase offset recovery of low density parity-check (LDPC)-coded systems is considered in this paper. We propose a new algorithm of phase offset estimation that involves the computation and maximization of a likelihood difference (LD)-based cost function calculated from the parity-check matrix of the code. We show in this paper that the new cost function has a simplified form compared to another algorithm proposed in the literature and presents similar estimation performance. Mean squared error (MSE) curves show very good performance of the proposed phase offset estimation algorithm, even at low signal-to-noise ratios.

During the digital transmission of information, errors are bound to occur. The errors may be random or burst errors. In this paper, we have obtained necessary and sufficient conditions for the existence of linear codes over that are capable of correcting -repeated burst errors of length(fixed) and -repeated burst errors of length (fixed) within sub-blocks of unequal lengths. We have also constructed a parity-check matrix for such a code.

Locally recoverable codes (LRCs) have been introduced as a family of erasure codes that support the repair of a failed storage node by contacting a small number of other nodes in the cluster. Boosted by their applications in distributed storage, LRCs have attracted a lot of attention in recent literature since the concept of codes with locality r was introduced by Gopalan et al. in 2012. Aiming to recover the data from several concurrent node failures, the concept of r-locality was later generalized as (r , δ) -locality by Prakash et al. An (r , δ) -LRCs in which every code symbol has (r , δ) -locality is said to be optimal if it achieves the Singleton-like bound with equality. In present paper, we are interested in optimal (r , δ) -LRCs over small fields, more precisely, over quaternary field. We study their parity-check matrices or generator matrices, using the properties of projective space. The classification of optimal quaternary (r , δ) -LRCs and their explicit code constructions are proposed by examining all possible parameters. [ABSTRACT FROM AUTHOR]

A linear code is called a locally repairable code (LRC) with locality r if one can recover an erased code symbol by accessing at most r other code symbols. Constructions of LRCs have been widely investigated in recent years. In this paper, we give a step forward in this direction. Firstly, we propose a novel concept of perfect LRCs whose size exactly achieves the Hamming-type bound, similar to the perfect codes that achieving the Hamming bound in classical coding theory. By the parity-check matrix approach, we establish some important connections between the existence of LRCs and the existence of some subsets of finite geometry and finite fields with certain properties, respectively. By employing q-Steiner systems and sunflowers in projective geometry and difference sets in finite fields, we obtain two new constructions of perfect LRCs with flexible parameters and present several new constructions of k-optimal LRCs achieving another Hamming-type bound under the integers restriction. Moreover, for fixed q and r, the code lengths of all the q-ary r-LRCs constructed in this paper can be arbitrarily large and the code rates can asymptotically achieve the upper bound r r + 1 . [ABSTRACT FROM AUTHOR]

This paper studies the blind recognition method of the sparse parity‐check matrices of low‐density parity‐check codes in noncooperative communication, which is critical to the reverse analysis of communication protocols using LDPC codes. In this paper, two improvements are made to the algorithm of Liu Qian et al. (2021) for this problem. Firstly, a Gaussian elimination method based on random column exchange and soft information is proposed to enhance the fault tolerance of the elimination process. Secondly, according to the sparse property of the parity‐check matrices of LDPC codes, a random extraction method is proposed to further improve the fault tolerance of the algorithm, and it is verified theoretically. Finally, simulations verify the superior performance of the algorithm proposed in this paper. [ABSTRACT FROM AUTHOR]

In this paper, codes over the direct product of two finite commutative chain rings are studied. The standard form of the parity-check matrix is determined. The structure of self-dual codes is described. A distance preserving Gray map from the direct product of chain rings to a finite field is defined. Two upper bounds on minimum distance are obtained. [ABSTRACT FROM AUTHOR]

The problem of blind phase offset recovery of low density parity-check (LDPC)-coded systems is considered in this paper. We propose a new algorithm of phase offset estimation that involves the computation and maximization of a likelihood difference (LD)-based cost function calculated from the parity-check matrix of the code. We show in this paper that the new cost function has a simplified form compared to another algorithm proposed in the literature and presents similar estimation performance. Mean squared error (MSE) curves show very good performance of the proposed phase offset estimation algorithm, even at low signal-to-noise ratios. [ABSTRACT FROM AUTHOR]

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s. [ABSTRACT FROM AUTHOR]

For the identification of Reed‐Solomon (RS) codes, the existing methods need to test the possible codeword length and the primitive polynomials exhaustively. Exhaustive search leads to high computational complexity. To overcome this limitation and fulfill the requirement in practice, a fast blind identification method is proposed. Different with most methods, our identification method is discussed in Galois Field of 2. First, by using Gaussian elimination, the bit matrix is transformed to the simplest upper triangular form. If the assumed codeword length is right, the matrix is of deficient rank, and the parameters of an RS code can be estimated according to the rank. The null space of the matrix, defined as the equivalent binary parity check matrix, can also be obtained from the simplification result. Then, a candidate set of primitive polynomials is constructed according to the estimated codeword length. By using the matrix null space, the correctness of a candidate primitive polynomial is tested through matrix analysis. Finally, by combining the estimated parameters, the generator polynomial of an RS code is identified. To decrease the bit errors in the matrix, soft‐decision data is used to select reliable bits. Experimental results show the effectiveness and robustness of our method. [ABSTRACT FROM AUTHOR]

New constructions for moderate-density parity-check (MDPC) codes using finite geometry are proposed. We design a parity-check matrix for the main family of binary codes as the concatenation of two matrices: the incidence matrix between points and lines of the Desarguesian projective plane and the incidence matrix between points and ovals of a projective bundle. A projective bundle is a special collection of ovals which pairwise meet in a unique point. We determine the minimum distance and the dimension of these codes, and we show that they have a natural quasi-cyclic structure. We consider alternative constructions based on an incidence matrix of a Desarguesian projective plane and compare their error-correction performance with regards to a modification of Gallager's bit-flipping decoding algorithm. In this setting, our codes have the best possible error-correction performance after one round of bit-flipping decoding given the parameters of the code's parity-check matrix. [ABSTRACT FROM AUTHOR]

Considering the high compression requirements of transmission, lossy block codes are particularly concerned due to their good compression performance and simple implementation. This paper investigates and analyzes the distortion rate performance of protograph LDPC (P-LDPC) codes for Bernoulli sources over AWGN channels. We first analytically establish the connection between the parity check matrix of a P-LDPC code and the extra distortion caused by the noisy channels. It was found that the additional distortion related to channel noise increases with the rising total degree of a parity check matrix. Further, two design algorithms are proposed for optimizing lossy multirate P-LDPC codes, considering the effect of noisy channels. Finally, simulation results demonstrate the robustness of the optimized P-LDPC codes over noisy channels. [ABSTRACT FROM AUTHOR]

We present two lower bounds on sub-packetization level $\alpha $ of MSR codes with parameters $(n, k, d=n-1, \alpha)$ where $n$ is the block length, $d$ is the number of helper nodes contacted during single-node repair, $\alpha $ the sub-packetization level and $k\alpha $ the scalar dimension. The first bound we present is for any MSR code and is given by $\alpha \ge e^{\frac {(k-1)(r-1)}{2r^{2}}}$. The second bound we present is for the case of optimal-access MSR codes and the bound is given by $\alpha \ge \min \left\{{ r^{\frac {n-1}{r}}, r^{k-1} }\right\}$. There exist optimal-access MSR constructions that achieve the second sub-packetization level bound with an equality making this bound tight. We also prove that for an optimal-access MSR code to have optimal sub-packetization level under the constraint that the $\beta $ scalar symbol indices we access from a given helper node is dependent only on the index of the failed node, it is necessary that the support of the parity-check matrix be the same as the support structure of the existing MSR constructions in literature such as the Clay code. [ABSTRACT FROM AUTHOR]

The decoding algorithm for the correction of errors of arbitrary Mannheim weight has discussed for Lattice constellations and codes from quadratic number fields. Following these lines, the decoding algorithms for the correction of errors of n = p-1 2 length cyclic codes (C) over quaternion integers of Quaternion Mannheim (QM) weight one up to two coordinates have considered. In continuation, the case of cyclic codes of lengths n = p-1 2 and 2n - 1 = p - 2 has studied to improve the error correction efficiency. In this study, we present the decoding of cyclic codes of length n = ϕ (p) = p - 1 and length 2n - 1 = 2ϕ (p) - 1 = 2p - 3 (where p is prime integer and ϕ is Euler phi function) over Hamilton Quaternion integers of Quaternion Mannheim weight for the correction of errors. Furthermore, the error correction capability and code rate tradeoff of these codes are also discussed. Thus, an increase in the length of the cyclic code is achieved along with its better code rate and an adequate error correction capability. [ABSTRACT FROM AUTHOR]

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This paper presents a unifying framework to construct low-density parity-check (LDPC) codes with associated Tanner graphs of desired girth. Towards this goal, we highlight the role that a certain square matrix that appears in the product of the parity-check matrix with its transpose has in the construction of codes with graphs of desired girth and further explore it in order to generate the set of necessary and sufficient conditions for a Tanner graph to have a given girth between 6 and 12. For each such girth, we present algorithms to construct codes of the desired girth and we show how to use them to compute the minimum necessary value of the lifting factor. For girth larger than 12, we show how to use multi-step graph lifting methods to deterministically modify codes in order to increase their girth. We also give a new perspective on LDPC protograph-based parity-check matrices by viewing them as rows of a parity-check matrix equal to the sum of certain permutation matrices and obtain an important connection between all protographs and those with variable nodes of degree 2. We also show that the results and methodology that we develop for the all-one protograph can be used and adapted to analyze the girth of the Tanner graph of any parity-check matrix and demonstrate how this can be done using a well-known irregular, multi-edge protograph specified by the NASA Consultative Committee for Space Data Systems (CCSDS). Throughout the paper, we exemplify our theoretical results with constructions of LDPC codes with Tanner graphs of any girth between 6 and 14 and give sufficient conditions for a multi-step lifted parity-check matrix to have girth between 14 and 22. [ABSTRACT FROM AUTHOR]

The bit error rate (BER) performance of spatial modulation (SM) can be further improved by applying quasi-cyclic low-density parity-check (QC-LDPC) codes recommended in 5G to SM. It motivates us to propose a QC-LDPC coded SM (QC-LDPCC-SM) scheme, where SM signals are protected by QC-LDPC codes. To estimate the channel state information at the receiver, a novel iterative joint channel estimation and data detection based on variable block length (IJCEDD-VBL) for SM is presented. In standard 5G LDPC codes, the parity-check matrix contains multiple submatrices, and then we can construct two different QC-LDPC codes by suitably selecting the submatrices. Thus, the QC-LDPCC-SM scheme can be effectively extended to cooperative scenarios when deploying the generated LDPC codes at the source and relay, respectively. We develop an analytical approach for the BER performance of the proposed schemes. The simulation and theoretical results are in good agreement at high signal-to-noise ratio (SNR). Furthermore, the proposed coded cooperative scheme outperforms its corresponding non-cooperative counterpart and the existing scheme. The numerical results also validate the effectiveness of the proposed channel estimation scheme. [ABSTRACT FROM AUTHOR]