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This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]

Summary: Cache coherence in modern computer architectures enables easier programming by sharing data across multiple processors. Unfortunately, it can also limit scalability due to cache coherency traffic initiated by competing memory accesses. Rack‐scale systems introduce shared memory across a whole rack, but without inter‐node cache coherence. This poses memory management and concurrency control challenges for applications that must explicitly manage cache‐lines. To fully utilize rack‐scale systems for low‐latency and scalable computation, applications need to maintain cached memory accesses in spite of non‐coherency. This paper introduces Bounded Incoherence, a memory consistency model that enables cached access to shared data‐structures in non‐cache‐coherency memory. It ensures that updates to memory on one node are visible within at most a bounded amount of time on all other nodes. We evaluate this memory model on modified PowerGraph graph processing framework, and boost its performance by 30% with eight sockets by enabling cached‐access to data‐structures. [ABSTRACT FROM AUTHOR]

They evaluate these optimizations in different multicore and GPU architectures, investigating the impact of different APIs on the performance, energy efficiency, and portability of the code. In the fifth contribution, entitled "Energy efficiency and portability of oil and gas simulations on multicore and graphics processing unit architectures", Serpa et al.5 propose three optimizations for an oil and gas application, reverse time migration (RTM), which reduce the floating-point operations by changing the equation derivatives. Moreover, the Brute Force algorithm running on CPU + GPU architecture has greater energy efficiency, reaching at least 1.79× more operations per energy consumption than other algorithms on different architectures explored in the work. [Extracted from the article]

Value locality (VL) refers to recurrence of values in a memory structure, and value prediction (VP) refers to predicting VL and leveraging it for diverse optimizations. VP holds the promise of exceeding true-data dependencies and provide performance and bandwidth advantages in both single- and multi-threaded applications. Fully exploiting the potential of VL, however, requires addressing several challenges, such as achieving high accuracy and coverage, reducing hardware and latency overheads, etc. In this paper, we present a survey of techniques for leveraging value locality. We categorize the research works based on key parameters to provide insights and highlight similarities and differences. This paper is expected to be useful for researchers, processor architects, and chip-designers. [ABSTRACT FROM AUTHOR]

The literature on the challenges of and potential solutions to architecting cloud-based systems is rapidly growing but is scattered. It is important to systematically analyze and synthesize the existing research on architecting cloud-based software systems in order to build a cohesive body of knowledge of the reported challenges and solutions. We have systematically identified and reviewed 133 papers that report architecture-related challenges and solutions for cloud-based software systems. This paper reports the methodological details, findings, and implications of a systematic review that has enabled us to identify 44 unique categories of challenges and associated solutions for architecting cloud-based software systems. We assert that the identified challenges and solutions classified into the categories form a body of knowledge that can be leveraged for designing or evaluating software architectures for cloud-based systems. Our key conclusions are that a large number of primary studies focus on middleware services aimed at achieving scalability, performance, response time, and efficient resource optimization. Architecting cloud-based systems presents unique challenges as the systems to be designed range from pervasive embedded systems and enterprise applications to smart devices with Internet of Things. We also conclude that there is a huge potential of research on architecting cloud-based systems in areas related to green computing, energy efficient systems, mobile cloud computing, and Internet of Things. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Summary: With the end of Moore's law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power‐ and time‐consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre‐decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs. [ABSTRACT FROM AUTHOR]

Summary: In order to take advantage of the processing power of current computing platforms, programmers typically need to develop software versions for different target devices. This task is time‐consuming and requires significant programming and computer architecture expertise. A possible and more convenient alternative is to start with a single high‐level description of a program with minimum implementation details, and generate custom implementations according to the target platform. In this paper, we use MATLAB as a high‐level programming language and propose a compiler that targets CPU/GPU computing platforms by generating customized implementations in C and OpenCL. We propose a number of compiler techniques to automatically generate efficient C and OpenCL code from MATLAB programs. One of such compiler techniques relies on heuristics to decide when and how to use Shared Virtual Memory (SVM). The experimental results show that our approach is able to generate code that provides significant speedups (eg, geometric mean speedup of 11× for a set of simple benchmarks) using a discrete GPU over equivalent sequential C code executing on a CPU. With more complex benchmarks, for which only some code regions can be parallelized, and are thus offloaded, the generated code achieved speedups of up to 2.2×. We also show the impact of using SVM, specifically fine‐grained buffers, and the results show that the compiler is able to achieve significant speedups, both over the versions without SVM and with naïve aggressive SVM use, across three CPU/GPU platforms. [ABSTRACT FROM AUTHOR]

Summary: This paper discusses the implementation, architecture, and use of a graphical web‐based application called ReliaCloud‐NS that allows users to (1) evaluate the reliability of a cloud computing system (CCS) and (2) design a CCS to a specified reliability level for both public and private clouds. The software was designed with a RESTful application programming interface for performing nonsequential Monte Carlo simulations to perform reliability evaluations of a CCS. Simulation results are stored and presented to the user in the form of interactive charts and graphs from within a web browser. The software contains multiple types of CCS components, simulations, and virtual machine allocation schemes. ReliaCloud‐NS also contains a novel feature that evaluates CCS reliability across a range of varying virtual machine allocations and establishes and graphs a CCS reliability curve. This paper discusses the software architecture, the interactive web‐based interface, and the different types of simulations available in ReliaCloud‐NS and presents an overview of the results generated from a simulation. [ABSTRACT FROM AUTHOR]

In the last decades, we have witnessed a growing interest toward touchless gestural user interfaces. Among other reasons, this is due to the large availability of different low-cost gesture acquisition hardware (the so-called 'Kinect-like devices'). As a consequence, there is a growing need for solutions that allow to easily integrate such devices within actual systems. In this paper, we present KIND-DAMA, an open and modular middleware that helps in the development of interactive applications based on gestural input. We first review the existing middlewares for gestural data management. Then, we describe the proposed architecture and compare its features against the existing similar solutions we found in the literature. Finally, we present a set of studies and use cases that show the effectiveness of our proposal in some possible real-world scenarios. [ABSTRACT FROM AUTHOR]

In this paper, we conduct a comparative study of relatively simple yet effective scheduling policies for many-task applications where multiple users with varying numbers of tasks are actively sharing a common system infrastructure. We have implemented three different scheduling mechanisms that can address fairness and user response time respectively in a common middleware stack called HTCaaS, which is a pilot-job-based multi-level scheduling system running on top of production-level clusters. As a representative case of our many-task applications, we have leveraged the virtual screening application, which is a computational technique used in drug discovery process to select the most promising candidate drugs for in vitro testing from millions of chemical compounds, which typically requires a substantial amount of computing resources and efficient processing of docking simulations. Our comparative experimental results of different scheduling policies show how we can effectively support multiple users in a shared resource environment by balancing between user satisfaction and overall system performance, provide guidelines to improve system utilization, and address additional technical challenges to support various many-task applications. [ABSTRACT FROM AUTHOR]

This paper presents a new approach which uses the tools within artificial intelligence (AI) software libraries as an alternative way of solving partial differential equations (PDEs) that have been discretised using standard numerical methods. In particular, we describe how to represent numerical discretisations arising from the finite volume and finite element methods by pre‐determining the weights of convolutional layers within a neural network. As the weights are defined by the discretisation scheme, no training of the network is required and the solutions obtained are identical (accounting for solver tolerances) to those obtained with standard codes often written in Fortran or C++. We also explain how to implement the Jacobi method and a multigrid solver using the functions available in AI libraries. For the latter, we use a U‐Net architecture which is able to represent a sawtooth multigrid method. A benefit of using AI libraries in this way is that one can exploit their built‐in technologies to enable the same code to run on different computer architectures (such as central processing units, graphics processing units or new‐generation AI processors) without any modification. In this article, we apply the proposed approach to eigenvalue problems in reactor physics where neutron transport is described by diffusion theory. For a fuel assembly benchmark, we demonstrate that the solution obtained from our new approach is the same (accounting for solver tolerances) as that obtained from the same discretisation coded in a standard way using Fortran. We then proceed to solve a reactor core benchmark using the new approach. For both benchmarks we give timings for the neural network implementation run on a CPU and a GPU, and a serial Fortran code run on a CPU. [ABSTRACT FROM AUTHOR]

Memory prefetcher algorithms are widely used in processors to mitigate the performance gap between the processors and the memory subsystem. The complexities behind the architectures and prefetcher algorithms, however, not only hinder the development of accurate architecture simulators, but also hinder understanding the prefetcher's contribution to performance, on both a real hardware and in a simulated environment. In this paper, we contribute to shed light on the memory prefetcher's role in the performance of parallel High‐Performance Computing applications, considering the prefetcher algorithms offered by both the real hardware and the simulators. We performed a careful experimental investigation, executing the NAS parallel benchmark (NPB) on a real Skylake machine, and as well in a simulated environment with the ZSim and Sniper simulators, taking into account the prefetcher algorithms offered by both Skylake and the simulators. Our experimental results show that: (i) prefetching from the L3 to L2 cache presents better performance gains, (ii) the memory contention in the parallel execution constrains the prefetcher's effect, (iii) Skylake's parallel memory contention is poorly simulated by ZSim and Sniper, and (iv) Skylake's noninclusive L3 cache hinders the accurate simulation of NPB with the Sniper's prefetchers. [ABSTRACT FROM AUTHOR]

SUMMARY The paper proposes a dynamic and hierarchical IPv6 address configuration scheme for a mobile ad hoc network (MANET). The scheme proposes the hierarchical architecture and combines the distributed and centralized address configuration approaches. In the architecture, a central node assigns IPv6 addresses for cluster heads that are distributed around a MANET, and distributed cluster heads assign IPv6 addresses for cluster members. The generation algorithm of a cluster is proposed, and it uses the number of potential cluster members as a measurement unit and minimizes the number of cluster heads. Therefore, the address configuration cost for cluster heads is reduced. A central node/cluster head uses the unicast communication mode to achieve the real-time address recovery in order to ensure that it has enough address resources for assignment. The paper also proposes the low-cost MANET merging/partitioning algorithm that guarantees that no address collision happens during the MANET merging/partitioning process. This paper analyzes the performance parameters of the proposed scheme, including the address configuration cost, the address configuration delay, and the number of MANET merging. The analytical results show that the proposed scheme effectively reduces the address configuration cost, shortens the address configuration delay, and decreases the number of MANET merging. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Within the Fifth Generation framework of dynamic network topology and moving cells, the nomadic node (NN) concept is seen as a promising paradigm to provide coverage extension and capacity improvement on demand as well as to attain reduced capital expenditure and operational expenditure when compared with fixed-node deployment, such as microcells. This paper proposes an enabling architecture for the NN operation in the framework of a wireless network, and then analyzes the physical layer aspects of the problem and investigates the performance of NN operation in the context of a realistic multi-cellular wireless network, with the help of site-specific propagation modeling and real geographical databases. The produced results provide useful insights into the performance of the NN operation; the results show that the NN operation is beneficial both in line-of-sight and non-line-of-sight scenarios and demonstrate that the NN selection strategy, which is based on the backhaul signal-to-interference-plus-noise ratio with a 10 dB power window, offers almost identical performance with the optimum end-to-end throughput algorithm. [ABSTRACT FROM AUTHOR]

Translation lookaside buffer (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Because TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects, and system engineers. [ABSTRACT FROM AUTHOR]

Recently, the mainstream hardware vendors such as Intel and AMD have made significant efforts to integrate the central processing unit (CPU) and the graphics processing unit (GPU) into a single chip, which forms a coupled CPU-GPU architecture. Data transfer between the CPU and the GPU through a Peripheral Component Interconnect Express bus is eliminated on this architecture, which provides new opportunities for database community to optimize query processing. Because of the lack of comprehensive evaluation of database systems on coupled CPU-GPU platforms, it is difficult for academic and industry researchers to make appropriate decisions on improvement and optimization directions. In this paper, we conduct an extensive experimental study to evaluate an online analytical processing system on Intel and AMD machines. The performance difference is measured and analyzed when executing queries on integrated GPUs and multicore CPUs. The impacts of various parameters, data sizes, and optimization techniques on performance are also investigated. The results provide preliminary insights into database query and operator behaviors on state-of-the-art coupled CPU-GPU architectures. [ABSTRACT FROM AUTHOR]

Concurrent programs are replacing the sequential programs as they utilize the true capabilities of multicore architecture. The extensive use of multicore systems and multithreaded paradigms warrants more attention to the testing of the concurrent programs. The testing concurrent program is not a new field as it has been more than 40 years because the first problem related to the testing concurrent program was addressed by the researchers. The field covers various domains, which include concurrency problems, testing approaches, techniques, graphical representations, tools, and subject systems. This paper aims at providing an overview of research in the domain of testing concurrent programs by classifying it into eight categories: (a) reachability testing, (b) structural testing, (c) model-based testing, (d) mutation-based testing, (e) slicing-based testing, (f) formal methods, (g) random testing, and (h) search-based testing. The survey is focused on the techniques applied, methodologies followed, and tools used in these aforementioned approaches. Furthermore, the gaps are also identified in different approaches. The paper concludes with the consolidation of various testing parameters along with the future directions. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Monitoring an individual's performance in a task, especially in the workplace context, is becoming an increasingly interesting and controversial topic in a time in which workers are expected to produce more, better and faster. The tension caused by this competitiveness, together with the pressure of monitoring, may not work in favour of the organization's objectives. In this paper, we present an innovative approach on the problem of performance management. We build on the fact that computers are nowadays used as major work tools in many workplaces to devise a non-invasive method for distributed performance monitoring based on the observation of the worker's interaction with the computer. We then look at musical selection both as a pleasant and as an effective method for improving performance in the workplace. The proposed approach will allow team coordinators to assess and manage their co-workers' performance continuously and in real-time, using a distributed service-based architecture. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, we start by looking at the algorithms and the numerical methods of pricing one exotic option, the strong path dependent Asian option using the Black-Scholes pricing model. We cover both geometric average and arithmetic average schemes that lead us to two different numerical solutions. Next, we discuss how to implement these algorithms on the leading many-core architectures with contrasting programming models and still achieve the comparable performance results. As an example, we will show that a 2-year contract with 252 times steps and 1,000,000 samples can be priced in approximately one fifth of a second on two leading many-core architectures. The purpose of this paper is to understand what is required to accelerate the numerical-intensive algorithms such as the Asian option pricing algorithm in quantitative and how to take advantage of the parallel programming features on many-core architecture and express parallelism inherent in the similar algorithms in quantitative finance. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Transmission based on flows becomes more and more popular in teleinformatics networks. To guarantee proper quality of service, to enable multipath transmissions, or just to increase transmission effectiveness in a network, traffic should be sent as flows. Flow-aware networking architecture is one of the possible concepts to realize flow-based transmissions. In this paper, the efficient congestion control mechanism (ECCM) is proposed to improve transmission in flow-aware networks (FAN). The mechanism makes it possible to minimize acceptance delay of streaming flows (served with high priority) without deteriorating other transmissions in the network. It is confirmed by simulation experiments that the implementation of FAN with the ECCM mechanism is a promising solution for the Future Internet. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

SUMMARY This paper describes PENNANT, a mini-app that operates on general unstructured meshes (meshes with arbitrary polygons), and is designed for advanced architecture research. It contains mesh data structures and physics algorithms adapted from the Los Alamos National Laboratory radiation-hydrodynamics code FLAG and gives a sample of the typical memory access patterns of FLAG. The basic capabilities and optimization approaches of PENNANT are presented. Results are shown from sample performance experiments run on serial, multicore, and graphics processing unit implementations, giving an indication of how PENNANT can be a useful tool for studies of new architectures and programming models. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

An optimized parallel algorithm is proposed to solve the problem occurred in the process of complicated backward substitution of cyclic reduction during solving tridiagonal linear systems. Adopting a hybrid parallel model, this algorithm combines the cyclic reduction method and the partition method. This hybrid algorithm has simple backward substitution on parallel computers comparing with the cyclic reduction method. In this paper, the operation count and execution time are obtained to evaluate and make comparison for these methods. On the basis of results of these measured parameters, the hybrid algorithm using the hybrid approach with a multi-threading implementation achieves better efficiency than the other parallel methods, that is, the cyclic reduction and the partition methods. In particular, the approach involved in this paper has the least scalar operation count and the shortest execution time on a multi-core computer when the size of equations meets some dimension threshold. The hybrid parallel algorithm improves the performance of the cyclic reduction and partition methods by 19.2% and 13.2%, respectively. In addition, by comparing the single-iteration and multi-iteration hybrid parallel algorithms, it is found that increasing iteration steps of the cyclic reduction method does not affect the performance of the hybrid parallel algorithm very much. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In the past few years, many publish/subscribe-based information-centric network (PS-ICN) architectures have been proposed and investigated to efficiently deliver information from content publishers to subscribers. However, most existing studies on PS-ICN have not considered how to utilize in-network caches, which is a common but important feature in ICN. To address this issue, in this paper, we propose a novel cache-aware K-anycast routing scheme, namely, CAKA, that can significantly improve the performance of content delivery. Specifically, we choose PURSUIT, which is one of the most important PS-ICN architectures, and leverage its bidirectional communication procedure to do the following: (1) enable multiple publishers to send probing messages to the same subscriber; and (2) allow the subscriber to retrieve content objects using K-anycast routing and network coding. In this study, we extend the PURSUIT protocol to support cache-aware K-anycast routing and design the algorithms to choose multiple partially disjointed paths for probing, and to select paths for content retrieval. To evaluate the performance of the proposed scheme, we develop not only a simulation testbed, but also a prototype running in a realistic network environment. Our studies show that the proposed scheme can significantly reduce the average hops to retrieve content objects, with very small overheads. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

As the current Internet architecture is suffering from scalability issues, the network research community has proposed alternative designs for the Internet architecture. Among those solutions that adopt the idea of locator/identifier split paradigm, the locator/identifier separation protocol (LISP) has been considered as the most promising solution because of its incrementally deployable feature. Despite various advantages provided by LISP, many ISPs are still conservative to adopt LISP into their production network because the standard LISP does not fully satisfy ISP's requirements on LISP-enabled services. In this paper, we define ISP's requirements on LISP-enabled commercial services and describe limitations of the standard LISP from an ISP's perspective. Also, we propose LISP controller, a centralized LISP management system. By using LISP controller, we evaluate three ISP's representative LISP use cases: traffic engineering, virtual machine live migration, and vertical handover. The results show that the proposed LISP controller provides centralized management, controllability, and fast map entry update, without any modifications on the standard LISP. LISP controller allows an ISP to control and manage its LISP-enabled services while satisfying ISP's requirements. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Adversarial training suffers from poor effectiveness due to the challenging optimisation of loss with hard labels. To address this issue, adversarial distillation has emerged as a potential solution, encouraging target models to mimic the output of the teachers. However, reliance on pre‐training teachers leads to additional training costs and raises concerns about the reliability of their knowledge. Furthermore, existing methods fail to consider the significant differences in unconfident samples between early and late stages, potentially resulting in robust overfitting. An adversarial defence method named Clean, Performance‐robust, and Performance‐sensitive Historical Information based Adversarial Self‐Distillation (CPr & PsHI‐ASD) is presented. Firstly, an adversarial self‐distillation replacement method based on clean, performance‐robust, and performance‐sensitive historical information is developed to eliminate pre‐training costs and enhance guidance reliability for the target model. Secondly, adversarial self‐distillation algorithms that leverage knowledge distilled from the previous iteration are introduced to facilitate the self‐distillation of adversarial knowledge and mitigate the problem of robust overfitting. Experiments are conducted to evaluate the performance of the proposed method on CIFAR‐10, CIFAR‐100, and Tiny‐ImageNet datasets. The results demonstrate that the CPr&PsHI‐ASD method is more effective than existing adversarial distillation methods in enhancing adversarial robustness and mitigating robust overfitting issues against various adversarial attacks. [ABSTRACT FROM AUTHOR]

With the advancement of new processor and memory architectures, supercomputers of multicore and multinode architectures have become general tools for large-scale engineering and scientific simulations. However, the nonuniform latencies between intranode and internode communications on these machines introduce new challenges that need to be addressed in order to achieve optimal performance. In this paper, a novel hybrid solver that is especially designed for supercomputers of multicore and multinode architectures is proposed. The new hybrid solver is characterized by its two-level parallel computing approach on the basis of the strategies of two-level partitioning and two-level condensation. It distinguishes intranode and internode communications to minimize the communication overheads. Moreover, it further reduces the size of interface equation system to improve its convergence rate. Three numerical experiments of structural linear static analysis were conducted on DAWNING-5000A supercomputer to demonstrate the validity and efficiency of the proposed method. Test results show that the proposed approach was superior in performance compared with the conventional Schur complement method. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper describes the GridWay metascheduler and exposes its latest and future developments, mainly related to interoperability and interoperation. GridWay enables large-scale, reliable, and efficient sharing of computing resources over grid middleware. To favor interoperability, it shows a modular architecture based on drivers, which access middleware services for resource discovery and monitoring, job execution and management, and file transfer. This paper presents two new execution drivers for Basic Execution Service (BES) and Computing Resource Execution and Management (CREAM) services and introduces a remote BES interface for GridWay. This interface allows users to access GridWay's job metascheduling capabilities, using the BES implementation of GridSAM. Thus, GridWay now provides to end users more possibilities of interoperability and interoperation.Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The theoretical teaching of Computer Architecture is not suitable longer. In the present time, students claim for a learning-by-doing according to their dynamic and active character. Nowadays, interactive teaching is possible thanks to the decrease in the prices of the Field Programmable Gate Arrays. This paper proposes a learning-by-doing methodology to teach Computer Architecture to first-year student who belong to a digital-native generation. The method consists in developing a whole computer from scratch while they are introduced to hardware description languages (HDL) and programmable logic devices. Firstly, students design each and every element of the computer by VHDL language. Later on, they interconnect the verified elements and test the complete computer. A FPGA-based board is needed to implement and check the correct performance of the designed computer. This educational approach is intended to be used with first-year students from Computer Engineering Degree, thus, it is the first experience of the students with the basics of Computer Architecture. Students have a computer and a FPGA-based board in anytime. In the final exam, a design of a different computer is propounded. Computer testing and programming is a requirement to pass. The high percentage of passed students corroborated the success of the methodology. Thus, computer functioning and construction is understood by a hands-on methodology at the same time as VHDL language and FPGA technology are introduced. Lack attention is avoided since students keep a dynamic role working with their personal computer and FPGA at all times. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient uplink low-density parity-check (LDPC)-coded multirelay cooperation architecture based on virtual Vertical-Bell Labs Layered Space-Time (V-BLAST) processing over a Rayleigh fading channel, where minimum mean square error in combination with a successive interference canceller and belief propagation-based joint iterative decoder based on the introduced multilayer Tanner graph are effectively designed to detect and decode the corrupted received sequence at the destination. By introducing V-BLAST transmission to coded multirelay cooperation, relays send their symbol streams simultaneously, which significantly reduce the transmission delay and provide higher transmission efficiency. The theoretical analysis and numerical results show that the proposed LDPC-coded cooperation scheme outperforms the coded noncooperation under the same code rate and achieves a better compromise, with respect to the performance, signal delay, and encoding complexity associated to the number of relays, than the conventional LDPC-coded cooperations without V-BLAST transmission. This performance gain can be credited to the proposed V-BLAST processing architecture and belief propagation-based joint iterative decoding by the introduced multilayer Tanner graph at a receiver side. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

ABSTRACT Most current generation avionics systems are based on a federated architecture, where an electronic device runs a single software module or application that collaborates with other devices through a network. This architecture makes the software development process very simple, but the hardware system becomes very complicated and it is difficult to resolve issues of size, weight, and power efficiently. An integrated architecture can address the size, weight, and power issues and provide better software reusability, testability, and reliability by means of partitioning. Partitioning provides a framework that can transparently integrate several real-time applications on the same computing device, allowing the isolation of the execution environment in terms of resources and faults. Several studies on partitioning software platforms have been reported; however, to the best of our knowledge, extensive comparison and analysis of design and implementation alternatives have not been conducted owing to the extreme complexity of their implementation and measurement. In this paper, we present three design alternatives for partitioning at the user, kernel, and virtual machine monitor levels, which are compared quantitatively. In particular, we target the worldwide standard software platform for avionics systems, that is, Aeronautical Radio, Incorporated Specification 653 (ARINC 653). Overall, our study provides valuable design references and demonstrates the characteristics of design alternatives. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Summary: As we approach exascale, computational parallelism will have to drastically increase in order to meet throughput targets. Many‐core architectures have exacerbated this problem by trading reduced clock speeds, core complexity, and computation throughput for increasing parallelism. This presents two major challenges for communication libraries such as MPI: the library must leverage the performance advantages of thread level parallelism and avoid the scalability problems associated with increasing the number of processes to that scale. Hybrid programming models, such as MPI+X, have been proposed to address these challenges. MPI THREAD MULTIPLE is MPI's thread safe mode. While there has been work to optimize it, it largely remains non‐performant in most implementations. While current applications avoid MPI multithreading due to performance concerns, it is expected to be utilized in future applications. One of the major synchronous data structures required by MPI is the matching engine. In this paper, we present a parallel matching algorithm that can improve MPI matching for multithreaded applications. We then perform a feasibility study to demonstrate the performance benefit of the technique. [ABSTRACT FROM AUTHOR]

Summary: Reliable mesh‐based simulations are needed to solve complex engineering problems. Mesh adaptivity can increase reliability by reducing discretization errors but requires multiple software components to exchange information. Often, components exchange information by reading and writing a common file format. This file‐based approach becomes a problem on massively parallel computers where filesystem bandwidth is a critical performance bottleneck. Our approach using data streams and component interfaces avoids the filesystem bottleneck. In this paper, we present these techniques and their use for coupling mesh adaptivity to the PHASTA computational fluid dynamics solver, the Albany multi‐physics framework, and the Omega3P linear accelerator frequency analysis applications. Performance results are reported on up to 16,384 cores of an Intel Knights Landing‐based system. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a novel visual educational configurable simulator for computer architecture and organization (COCONUT). By using the simulator students can create their own processor with an arbitrary architecture and simple organization on the register transfer level, write an assembly program to be executed on the processor and observe the instruction execution phases of the program on the processor. The students can create their processor by using the simulator of a computer system with fixed and configurable parts. The configurable part allows students to use the simulator for defining the instruction decoding of the processor operation unit and the content of the microprogram memory of the processor control unit. The simulator's usage was evaluated at the University of Belgrade—School of Electrical Engineering on two courses for two consecutive school years. The evaluation results showed that 80% of the students stated that the simulator helped them to better understand the course material and that they had a positive user experience with the simulator. [ABSTRACT FROM AUTHOR]

Summary: This paper describes a methodology to improve the energy efficiency of high‐performance multiprocessor architectures with dynamic and partial reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. Field‐programmable gate arrays are increasingly being used in cameras owing to their suitability for real‐time image processing with intensive, high‐performance tasks and to the recent advances in dynamic reconfiguration that further improve energy efficiency. The approach used to best exploit DPR is based on the better coupling of 2 decisive elements in the problem of heterogeneous deployment: design space exploration and advanced scheduling. We show how a tight integration of exploration, energy‐aware scheduling, common power models, and decision support in heterogeneous DPR multiprocessor system‐on‐a‐chip mapping can be used to improve the energy efficiency of hardware acceleration. Applying this to a mobile vehicle license‐plate tracking and recognition service results in up to a 19‐fold improvement in energy efficiency compared with software multiprocessor execution (in terms of energy‐delay product) and up to more than a threefold improvement compared with a multiprocessor with static hardware acceleration (ie, without DPR). [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we propose PCPN ET, a deep‐learning based approach for estimating local 3D shape properties in point clouds. In contrast to the majority of prior techniques that concentrate on global or mid‐level attributes, e.g., for shape classification or semantic labeling, we suggest a patch‐based learning method, in which a series of local patches at multiple scales around each point is encoded in a structured manner. Our approach is especially well‐adapted for estimating local shape properties such as normals (both unoriented and oriented) and curvature from raw point clouds in the presence of strong noise and multi‐scale features. Our main contributions include both a novel multi‐scale variant of the recently proposed PointNet architecture with emphasis on local shape information, and a series of novel applications in which we demonstrate how learning from training data arising from well‐structured triangle meshes, and applying the trained model to noisy point clouds can produce superior results compared to specialized state‐of‐the‐art techniques. Finally, we demonstrate the utility of our approach in the context of shape reconstruction, by showing how it can be used to extract normal orientation information from point clouds. [ABSTRACT FROM AUTHOR]

This paper presents CoopREP, a system that provides support for fault replication of concurrent programs based on cooperative recording and partial log combination. CoopREP uses partial logging to reduce the amount of information that a given program instance is required to store to support deterministic replay. This allows reducing substantially the overhead imposed by the instrumentation of the code, but raises the problem of finding a combination of logs capable of replaying the fault. CoopREP tackles this issue by introducing several innovative statistical analysis techniques aimed at guiding the search of the partial logs to be combined and needed for the replay phase. CoopREP has been evaluated using both standard benchmarks for multithreaded applications and real-world applications. The results highlight that CoopREP can successfully replay concurrency bugs involving tens of thousands of memory accesses, while reducing recording overhead with respect to state-of-the-art noncooperative logging schemes by up to 13× (and by 2.4× on average). [ABSTRACT FROM AUTHOR]

Clock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high-performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)-Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC-UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip-Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a high resolution time-to-digital converter (TDC) for low-area applications. To achieve both high resolution and low circuit area, we propose a dual-slope voltage-domain TDC, which is composed of a time-to-voltage converter (TVC) and an analog-to-digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single-slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non-linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain-boosting current source is applied to overcome the low output impedance of the current source in the sub-100-nm CMOS process. The prototype TDC is implemented using a 65-nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8-bit 8.86-ps resolution and an integrated non-linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper proposes a discrete-time charge domain filter that achieves complex conjugate poles in the transfer function of the filter. To achieve complex conjugate poles, local feedbacks are inserted around two successive discrete-time integrators. The feedback path is implemented through a transconductance cell which applies a continuous time current into the integrators. Analytical models have been proposed to approximate the behavior of the filter. These models confirm that the structure is capable of realizing complex poles and thus can be used to synthesize any type of filter structures such as Butterworth, Chebysheve, etc. To show the effectiveness of the proposed architecture, Butterworth filters of order 2 and 4 operating at 50MS/s are designed and implemented in 180-nm CMOS technology with 1.8-V power supply. The effect of circuit nonidealities on the performance of the filter is analyzed and verified through simulations. Simulation results show that a conventional charge domain filter can be simply extended to implement complex conjugate poles while the noise and linearity performance of the filter are also improved. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a novel list-based scheduling algorithm called Improved Predict Earliest Finish Time for static task scheduling in a heterogeneous computing environment. The algorithm calculates the task priority with a pessimistic cost table, implements the feature prediction with a critical node cost table, and assigns the best processor for the node that has at least 1 immediate successor as the critical node, thereby effectively reducing the schedule makespan without increasing the algorithm time complexity. Experiments regarding aspects of randomly generated graphs and real-world application graphs are performed, and comparisons are made based on the scheduling length ratio, robustness, and frequency of the best result. The results demonstrate that the Improved Predict Earliest Finish Time algorithm outperforms the Predict Earliest Finish Time and Heterogeneous Earliest Finish Time algorithms in terms of the schedule length ratio, frequency of the best result, and robustness while maintaining the same time complexity. [ABSTRACT FROM AUTHOR]

Recent graphic processing units (GPUs) have remarkable raw computing power, which can be used for very computationally challenging problems. Like in micromagnetic simulations, where the magnetostatic field computation to analyze the magnetic behavior at very small time and space scale demands a huge computation time. This paper presents a multidimensional FFT-based parallel implementation of a magnetostatic field computation on GPUs. We have developed a specialized 3D FFT library for magnetostatic field calculation on GPUs. This made it possible to fully exploit the symmetries inherent in the field calculation and other optimizations specific to the GPUs architecture. We have compared our results with the widely used CPU-based parallel OOMMF program and with an equivalent serial implementation on CPU. The results have shown a speedup of up to 95x and 8.7x for single and 66x and 4.6x for double precision floating point accuracy against equivalent serial implementation and OOMMF, respectively. [ABSTRACT FROM AUTHOR]

Because of the power and energy constraints in modern computing systems, it is important to find a balance between performance and power/energy consumption to produce not only energy efficient portable devices but also reliable computing systems. In this paper, we present an analytical investigation of the performance and power/energy consumption of a well-known medical application, 'ultrasound B-mode imaging,' which is implemented on modern commercial graphics processing units (GPUs). With this target application, we investigate the impact of GPU hardware features on performance, power, and energy by experimentally applying voltage and frequency scaling on various GPU devices. Based on our results, we mathematically build a performance prediction model to show the analytical relationship between the architectural features of those GPUs and the application performance. Our results show that the performance prediction model has errors of less than 8.71% and that there exists an energy-optimal point in the design space spanned by the core clock frequency. We expect that our model can help engineers to design an ultrasound diagnosis system with the most suitable GPU that satisfies cost, performance, and power/energy constraints. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy efficiency and I/O performance analysis of low‐power architectures when compared to conventional architectures, with the goal of studying the viability of using them as storage servers. Our results show that despite the fact the power demand of the storage device amounts for a small fraction of the power demand of the whole system, significant increases in power demand are observed when accessing the storage device. We investigate the access pattern impact on power demand, looking at the whole system and at the storage device by itself, and compare all tested configurations regarding energy efficiency. Then we extrapolate the conclusions from this research to provide guidelines for when considering the replacement of traditional storage servers by low‐power alternatives. We show the choice depends on the expected workload, estimates of power demand of the systems, and factors limiting performance. These guidelines can be applied for other architectures than the ones used in this work. [ABSTRACT FROM AUTHOR]

Summary: With the emergence of IoT and cloud computing technologies, massive data are generated from various applications everyday and communicated through the Internet. Secure communication is essential to protect these data from malicious attacks. Block ciphers are one mechanism to offer such protection but unfortunately involve intensive computations that can be performance bottlenecks to the servers, especially when the data center needs to handle thousands of concurrent transactions. In this paper, we investigate the feasibility of the GPU as an accelerator to perform high‐speed encryption in server environments. We present optimized implementations of a conventional block cipher (AES) and new lightweight block ciphers (LEA, Chaskey, SIMON, SPECK, and SIMECK) across three new GPU architectures (Kepler, Maxwell, and Pascal). For AES, we improve the fine‐grain implementation by utilizing the warp shuffle instruction available in these three new GPU architectures, which yield a 6%‐16% improvement over the previous implementations. For LEA, Chaskey, SIMON, SPECK, and SIMECK, we first analyze why they cannot have efficient fine‐grain implementations in the GPU and then present our optimization techniques, which are able to achieve impressive encryption speeds of 1.912, 637, 1.485, 2.291, and 1.478 Tb/s, respectively, in GTX1080. [ABSTRACT FROM AUTHOR]

Summary: While GPUs have seen a steady increase in usage, Xeon Phis have struggled in proving their value, and eventually got discontinued. Is this a matter of the Intel many‐core architecture's younger age or are there reasons due to specific features? This paper reviews quantitative information addressing these questions. Using two latest coprocessors, we evaluate performance and programming productivity across a range of microbenchmarks and applications. We consider productivity as the percentage of hand‐optimized performance reached by a simple high‐level parallel programming model that is translated onto the specific architectures by advanced compilers. We evaluate and compare the performance of the two coprocessors and point out where Xeon Phis fall short. We also briefly review the performance of different execution modes of Xeon Phis. Moreover, unlike common expectation, we found that Xeon Phis' productivity is marginally better that GPUs. The current results suggest that the performance advantage of GPUs outweighs the productivity benefit of Xeon Phis. Closing the performance gap and increasing the productivity benefit that a more regular many‐core paradigm can offer will be essential in designing a next‐generation architecture. [ABSTRACT FROM AUTHOR]

High performance fast multipole method is crucial for the numerical simulation of many physical problems. In a previous study, we have shown that task-based fast multipole method provides the flexibility required to process a wide spectrum of particle distributions efficiently on multicore architectures. In this paper, we now show how such an approach can be extended to fully exploit heterogeneous platforms. For that, we design highly tuned graphics processing unit (GPU) versions of the two dominant operators P2P and M2L) as well as a scheduling strategy that dynamically decides which proportion of subsequent tasks is processed on regular CPU cores and on GPU accelerators. We assess our method with the StarPU runtime system for executing the resulting task flow on an Intel X5650 Nehalem multicore processor possibly enhanced with one, two, or three Nvidia Fermi M2070 or M2090 GPUs (Santa Clara, CA, USA). A detailed experimental study on two 30 million particle distributions (a cube and an ellipsoid) shows that the resulting software consistently achieves high performance across architectures. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]