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The article reports that a team of researchers at Stanford University is trying to quantify the uncertainty inherent in their supercomputer computations so that engineers can build appropriate tolerances into their designs. The group is investigating hypersonic aircraft, which would fly through the atmosphere at six or twelve times the speed of sound. Researchers have created a new computer language that will make it easier to program and run complex simulations on the supercomputers of the future.

The article looks at simulation methods for radar system designs such as radar antennas, radar control systems, and radome systems. Mathematical and high-performance computing models for various radar systems are evaluated, including the finite element method, hybrid numerical models, and distributed memory parallel simulations.

The article offers information on concurrent testing in semiconductors. It is deemed to boost test times below the device-limited test time (DLTT) by testing various cells of the device in parallel. It involves the simultaneous testing of multiple cells. While traditional programs would test a system-on-chip device, which contains a digital core, analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and specialty digital and analog cells, serially and then test its functionality as a complete system, concurrent testing would allow testing the cells in parallel, reducing overall testing time.

The article reports on the developments in computer programming industry in the U.S. It notes that OpenMP portable supports multiplatform, shared-memory parallel programming and targets Symmetrical-multiprocessing (SMP) systems. It states that parallel programming platforms target general-purpose processing architectures, however, the multicore graphics processing units (GPUs) found in most high-performance 3D video adapters are also available. Moreover, it notes that parallel programming on SMP architectures deals with virtual memory, pointers and multithreading facilities that have been commonly used for decades using languages like C, C++, and Java.

The article focuses on the demand for multicore processor resources that can cater multiheaded applications and to take advantage of parallelism. It notes that the problem arises when individual applications make as many threads as the number of cores available and each thread performs central processing unit (CPU)-intensive tasks. Moreover, the lack of systemwide knowledge stops the overall system performance. Results of the various tests conducted as well as the author's recommendations and suggestions are also presented.

The article examines multithreaded programming concepts to show how developers can take advantage of multicore processors. Multithreaded programming is becoming an even more critical technique for software developers to master as hardware architectures move to multicore processors. Programming strategies that include task parallelism, data parallelism, and pipelining may be implemented to further optimize performance after mastering the basics. Programming models and tools that express parallelism should be considered to assist in multithreading code and providing scalability benefits for future applications.

This article describes the use of parallel processing techniques to reduce cellular test time. In 2006, an estimated 750 million cellular handsets were shipped and this quantity is likely to increase by 2011. Due to complex architectures, reducing the test time of wireless handsets is considered difficult. For instance, a large number of wireless handsets require testing due to multiple cellular standards and for its need to adhere to noncellular standards like global positioning system (GPS), Bluetooth and WiFi.

The article discusses parallel programming using Python-based NetworkSpaces (NWS). In the past Parallel programing required large and expensive machines and used older languages, such as the Fortran. With many computers being multicore and with multiple computers accessible to most users, developers are working with newer languages like Python and R for parallel programing. NWS, according to the article, is easy to learn and accessible and has been used to run parallel programs on many motherboards. It does not require specialized tools or hardware. Developed at Scientific Computing Associates, it is available at SourceForge. Instructions on how to install the programs are discussed in the article.

The article discusses the advantages of using Serial RapidIO technology in connecting digital signal processors for massive signal processing requirements. Serial RapidIO is a high-speed point-to-point protocol used for much simpler multi-processor designing and inter-processing communications. RapidIO is architecturally divided in three layers logical, transport and physical which also account for its flexibility for use in a number of applications together with high-processing capabilities. Ambric Semiconductor Co. has also developed an Am2000 massive parallel fixed-point TeraOps solution for complex video and image processing markets. It provide a simplified platform to develop and debug embedded applications with the help of its structural object programming model. INSET: DESIGN IT YOUR WAY WITH RHAPIDIO.

The article presents the author's discussion of multithreading using an OSGi device. The author explains that the OSGi Alliance Service Platform forms part of the Java-based environment. The components of the OSGi framework are libraries and services designed to execute code from different sources. The Eclipse OSGi runtime may also be applied as a stand-alone framework. Aside from improving performance or taking advantage of chip multiprocessors, multithreading in OSGi is important in terms of getting something done.

The article reports on development of new high-speed computer chip to revolutionize gaming technology in Australia. The Cell chip, based on a design inspired by supercomputers, runs at least 10 times as fast as Intel's most powerful Pentium chip. Cell boasts a staggering fiftyfold advantage in handling graphics-intensive applications.

The article reports on next-generation low power multiprocessor systems-on-chip (MPSoC). Designers must almost invariably trade the ever-increasing demand for performance against stringent power budgets, particularly for battery-operated devices. In modern processor core design, designers widely take advantage of techniques to control and minimize power dissipation. But in contrast to the single processor scenario, the software programmer's decisions in the MPSoC domain regarding application mapping and task-level parallelism are key in determining the power/performance trade-off points.

Discusses the processing of digital images using OpenMP-based multithreading filter system. Selection of threading method; Information on threading the radial blur algorithm; Process of tuning the filter. INSET: Barycentric Coordinates.

Focuses on usage of two-dimensional input/output (I/O) fabrics to link arrays of processors for simplifying data transfer and enabling parallel processing. Design of a third-generation (3G) chip; Structure of two-dimensional I/O fabrics; Scalability and determinism of 3G devices. INSET: 2-D-FABRIC I/O AVOIDS WORST-CASE LATENCY.

Discusses the significance of parallel processing in speeding visualization of scientific data. Utilization of multi-threading and distributed computing techniques; Consideration of account issues applicable to single-threaded code; Requirement of robust solutions.

Discusses the anatomy of multiprocessor design that improves performance of various applications through parallel processing. Provision of continuous iterative processing facility by microprocessor architecture; Use of microprocessor architectures in embedded designs; Simplification of application development effort by partitioning design over several processors. INSET: MULTIPROCESSOR PROGRAMMING LANGUAGES.

Reports on the introduction of high-speed switch fabrics for multiprocessing connections. Advantages over standard parallel buses; Features of emerging pseudoserial interconnect systems. INSET: Early MP Switch Fabrics.

Discusses issues in implementing queuing and scheduling for high-performance routers. Challenges in scaling to next-generation routers and beyond; Mix of techniques involving the best approach; Algorithms to speed selected tasks; Innovative hardware; Parallel-processing techniques.

Focuses on parallel processing in computational fluid dynamics (CFD) modeling simulations. Influence on automotive and aerospace testing; Domain decomposition as basis of parallel processing; Benefits of CFD simulations.

Focuses on equipment used for simulating severe thunderstorms and tornadoes. Numerical methods of cloud models; Details on the design and implementation of cloud-modelling software; Importance of parallel processing on simulating thunderstorms and tornadoes; Importance of scientific visualization for a researcher; Forecasts on simulations of thunderstorms.

Discusses the advantages of using massively parallel processing (MPP) systems as foundations for large data warehouses and decision support systems. Guidelines for choosing between MPP and symmetric multiprocessing (SMP) servers and software; MPP systems' limitless scalability; Parallel databases; Importance of MPP to information technology (IT) executives. INSET: At General Accident, customers are key..

Presents an overview of `The Commercial Parallel Processing Conference,' sponsored by CMP Publications, Inc. and the Gartner Group, on September 27-29, 1995, in Chicago, Illinois. Impact of commercialization of parallel processing on information technology; Future of parallel databases; Achievement of high performance in commercial parallel processing.

Discusses the usefulness of symmetric multiprocessing (SMP) in real-time computing. Categories of high-end embedded applications for SMP; Growth in SMP hardware and real-time operating system solutions; Factors to consider when designing real-time SMP systems.

Reports on the increasing utility of parallel processing in production engineering environments. Future of parallel processing; Approaches of major companies to parallel computing; Reasons behind the momentum toward parallel computing; Exploration of the limits of parallel processing; Progress made in integrating parallel-processing computers into personal computer- and workstation-based engineering networks.

Focuses on the challenges faced by HealthPartners Inc. and MCI Telecommunications Corp. and the hardware decisions they made for their data warehousing projects. Systems chosen by the companies; Debate among information system (IS) professionals about the relative benefits of symmetrical multiprocessing (SMP) and massively parallel processing (MPP).

Describes the features of parallel processor computers. Emergence of several parallel-processing designs; Caveats of the cluster arrangement; Symmetric multiprocessor (SMP) as true parallel systems; Benefits of the scalable parallel processing (SSP) approach; SPP's solution to problems users encounter with other high-speed computers. INSETS: Brief guide to terminology.;How does a compiler find threads?..

Describes the Active Expressions library for parallel programming with C++, which combines the conciseness and `checkability' of language extensions with portability and extensibility of a library. Developing Active Expressions; Defining operators; Implementing operators; Returning to the Mandelbrot Set task.

Discusses parallel-processing supercomputing technology. Shifting of focus to scalability; IBM Corp.'s 9076 SP1; Parsytec Computer GmbH's Xplorer; Sequent Computer Systems' WinServer; Applications; Comparison of loosely and tightly coupled architectures; Parix programming environment; Software scalability; IBM's Vulcan architecture; Cray Research's T3D massively parallel computer. INSET: Embedded systems look at parallelism..

The article reports that the floorplan for next generation of accelerated jrocessing units (APUs) is Heterogeneous System Architecture (HSA) from AMD. It states that HSA to be beneficial for the Heterogeneous System Architecture Intermediate Language (HSAIL) and associated design environment. It further mentions that HSAIL virtual machine consists of at least one host Central Processing Unit and an HSA component.

Reports on the slow development of high performance software as compared to hardware. High Performance Computing and Communications program; Parallel processing; Value of computer sciences and applications research to industry.

The article presents a control system project which uses the LabView of National Instrument and a parallel port of PC. It is showed that the circuit in this Design Idea controls the inbound and outbound traffic of cars in a parking lot. The article also presents the detailed information of the control system including the LabView diagrammatic program, inputs, and a limit for the parking lot.

Earlier this year, Cadence (www.cadence.com) introduced the Clarity 3D Solver, a 3D electromagnetic (EM) field solver for printed-circuit-board (PCB) and integrated-circuit (IC) package design. Cadence believes that the solution to today's thermal analysis challenges lies in its new Celsius Thermal Solver tool, which enables iterative electrical-thermal co-simulation at the IC, package/ PCB, and system levels. At the IC level, the Celsius Thermal Solver tool allows for analysis within the chip. [Extracted from the article]

Focuses on the advantages of high performance computing with Linux clusters. Features and capabilities of Linux clusters; History of the adoption of clusters within the scientific community; Association of technical computing clusters with parallel processing; Difference of Linux clusters from other available options.

Focuses on multiprocessor computers. Comparison of multiprocessor computers to normal computers; Discussion of multithreading; Differences between multiprocessing and multiprocess; How operating systems take advantage of the additional processing power of a computer; Symmetric versus asymmetric multiprocessing systems.

Reports developments related to avionics as of January 2002. Plans of ARINC to demonstrate an inflight broadband communication capability; Development of an advanced head-mounted eye-tracking systems by Rockwell Collins' Polhemus Inc.; Use of parallel processing and 4D imaging to visualize aerodynamic flow noise.

Focuses on the release of parallelized versions of database management systems. Accessibility of parallel computing technology to information system shops; Parallel processing on symmetric multi-processing machines; Commercial use of massively parallel processing (MPP). INSETS: MPP: Not ready for real time?.;Nothing wrong with being commercial..

Focuses on computer architectures' use of a large number of scalable parallel processors to develop fast and flexible design concepts. Increase of processors' memory capacity and the number of needed input/output ports; Exploration of productivity enhancements by independent software vendors.

Presents graphs and a chart showing the results of the survey on the use of massively parallel processing (MPP) and symmetrical processing (SMP) technologies. Most popular vendors; Customer satisfaction; Sending on MPPs and SMPs.

Reports that the technologies of symmetrical multiprocessors (SMP) and massively parallel processors (MPP) have the potential to combine in the future. National Association of Securities Dealers' (NASD) use of a Unix SMP server; Vendors that are preparing products for the combined technology; MPPs advantage over SMP in terms of reliability and availability.

Presents answers to questions regarding massively parallel processing (MPP). Applications; Costs of a shift from legacy systems to MPP; MPP suppliers; Components. INSETS: Suppliers going after the commercial market.;What is MPP?.;What is MPP's future?..

Focuses on the design of multiprocessors. Challenges in designing multiprocessors; Employment of parallel processing in multiprocessor architectures; Hierarchal model of parallel processing; Ways to provide rapid synchronization; Features of the network supercomputer level of the hierarchy.

Reports on MacNeal-Schwendler Corp.'s adaptation of the structural program NASTRANS to take advantage of the parallel processing features of AIX, the UNIX operating system of International Business Machines used on the RS/6000 SP reduced instruction set supercomputer. Company's contract with Tera Computer Co. for the availability of NASTRANS for Tera's multithreaded architecture parallel scheme.

Reports that Intel and Samsung will cooperate to supply massively parallel processing supercomputers to South Korea and other Asian countries. Collaboration between Intel's Scalable Systems Division and Samsung Data Systems Co. of Seoul to distribute Intel's Paragon XP/S and Paragon XP/E scalable, massively parallel computers.

The article offers information on parallel-processing technologies for 5G and machine-learning (ML) solutions presented at the 2018 Hot Chips Symposium including Xilinx's Everest adaptive compute acceleration platform (ACAP), Tachyum's Prodigy chip and Mythic's matrix multiplying flash-memory technology.

The article offers brief information the Automata Processor from Micron Technology Inc.

The article presents information on a graphical processing unit (GPU) with a higher memory system developed by Japan-based computer manufacturer Fujitsu. Topics include the concept of deep neural learning (DNL) technology used for content identification and audio recording deciphering, the capability of the memory of GPUs for parallel processing, and the testing of the memory system in the Caffe open source deep learning framework software.

The article discusses the aspects of determining the multicore computing results of supercomputers. The author mentions that synchronous dynamic random-access memory (SDRAM) and flash memory bottlenecks are the hindrance for fast computations, but disk drive speeds can also determine the rate at which supercomputers deliver results. He also tackles the role of climate simulations in identifying the calculation rate.

Gives advice on buying high performance computing (HPC) tools. Measurements of HPC systems; Features of the HPC Challenge Suite; Factors to consider before buying HPC products. INSET: The High Performance Computing Challenge Suite.

The article focuses on the diversity of computational approaches and mathematical algorithms that came forward over the years during the development of high performance computer technology. It has been assessed that the most beneficial, cost-effective computing resource for a simulation differs considerably from one application to another. The majority of super computer centers choose to have a single general-purpose, homogeneous system. The net result is that some application suffers: the memory intensive calculations do not have optimal amounts memory, while the greater compute-intensive calculations do not have optimal numbers of processors. In addition, different microprocessors are more appropriate for specific types of scientific applications than for others. The lifetime of scientific codes is expressed in decades while the lifetime of computers is expressed in years, which is also a major problem for users of parallel supercomputers.

Reports on the development of the Earth System Modeling Facility supercomputer by researchers from Irvine, California. Capability of the supercomputer to simulate the Earth's climactic changes up to 300 hundred years in the future; Benefits of the supercomputer on the study of human influences such as global warming and pollution on natural climate cycles; Software that coordinates the symphony of combined Shared Memory Parallelism with Multiple Program Multiple Data.