Search

Implementation of challenging Exploration Systems Missions Directorate objectives and strategies can be constrained by onboard computing capabilities and power efficiencies. The Radiation Hardened Electronics for Space Environments (RHESE) High Performance Processors for Space Environments project will address this challenge by significantly advancing the sustained throughput and processing efficiency of high-per$ormance radiation-hardened processors, targeting delivery of products by the end of FY12.

A new saturation current model is presented for the n-channel G4-FET, a novel 4-gate transistor.

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

Electrical power requirements for the next generation of deep space missions cover a wide range from the kilowatt to the milliwatt.

Advanced thermoelectric microdevices integrated into thermal management packages and low power, electrical source systems are of interest for a variety of space and terrestrial applications. By shrinking the size of the thermoelements, or legs, of these devices, it becomes possible to handle much higher heat fluxes, as well as operate at much lower currents and higher voltages that are more compatible with electronic components. The miniaturization of state-of-the-art thermoelectric module technology based on Bi2Te3 alloys is limited due to mechanical and manufacturing constraints for both leg dimensions (100-200 gm thick minimum) and the number of legs (100-200 legs maximum). We are investigating the development of novel microdevices combining high thermal conductivity substrate materials such as diamond, thin film metallization and patterning technology, and electrochemical deposition of thick thermoelectric films. It is anticipated that thermoelectric microcoolers with thousands of thermocouples and capable of pumping more than 200 W/sq cm over a 30 to 60 K temperature difference can be fabricated. In this paper, we report on our progress in developing an electrochemical deposition process for obtaining 10-50 microns thick films of Bi2Te3 and its solid solutions. Results presented here indicate that good quality n-type Bi2Te3, n-type Bi2Te(2.95)Se(0.05) and p-type Bi(0.5)Sb(1.5)Te3 thick films can be deposited by this technique. Some details about the fabrication of the miniature thermoelements are also described.

Miniaturized thermoelectric devices integrated into thermal management packages and low power, high voltage, electrical power source systems are of interest for a variety of space and terrestrial applications.

Active thermal control for electronics on Mars Rovers imposes a serious penalty in weight, volume, power consumption, and reliability.

The advanced miniaturization of all the on-board spacecraft functions into a highly integrated, modular, and reliable architecture is a major enabling technology for future deep-space and Earth orbiting science missions.

Advanced thermoelectric microdevices integrated into thermal management packages and low power, electrical source systems are of interest for a variety of space and terrestrial applications.

UNKNOWN

Due to the combined increase in circuit integration and chip power dissipation, there is a rapidly growing demand for solving the thermal management issues of power microelectronics.

The fatigue of thin film metal interconnections in high density electronics packaging subjected to thermal cycling has been evaluated using a probabilistic fracture mechanics methodology. This probabilistic methodology includes characterization of thin film stress using an experimentally calibrated finite element model and simulation of flaw growth in the thin films using a stochastic crack growth model.

We report on resistivity and chemical stability of Cr/Au bilayers deposited by sputtering on three kinds of substrates: alumina, aluminum nitride and aluminum nitride coated alumina. The insertion loss of Cr/Au microstrip lines fabricated on these three substrates was low and stable after 100 cycles in the -65 degree C to 125 degree C temperature range.

Commercial and government communication, radar, and information systems face the challenge of cost and mass reduction via the application of advanced packaging technology. A majority of both government and industry support has been focused on low frequency digital electronics.

The reaction between a sputtered-deposited Ta film (320 nm thick) and a single crystalline (001) beta-SiC substrate induced by vacuum annealing at temperatures of 600-1200 C for 1 h (30 min at 1100 C) is investigated by 3 MeV He(+2) backscattering spectrometry, x-ray diffraction, secondary ion mass spectrometry, and transmission and scanning electron microscopies. No significant reaction is observed at 800 C or at lower tempertures. At 900 C, the main product phases are Ta2C and carbon-stabilized Ta5Si3. A minor amount of unreacted Ta is also present. After annealing at 1000 C, all the tantalum has reacted; the reaction zone possesses a multilayered structure of beta-SiC/TaC/carbon-stabilized Ta5Si3/alpha-Ta5Si3/Ta2C. The diffusion path at 1000 C is plotted on the isothermal section of the Ta-Si-C phase diagram. At 1100 C, the reacted layer has an interface with the SiC substrate that is still quite flat but has a rough surface due to the formation of macroscopic voids within the reacted layer. The equilibrium products predicted by the phase diagram are TaC and TaSi2. This final state is reached by annealing at 1200 C for 1 h. At that point, the reacted layer has a latterally very uneven structure and morphology.

Gold has been used as a conductor material in many microelectronic applications because of its low resistivity, bondability, and oxidation/corrosion resistance.

UNKNOWN

A new millimeter-wave package architecture with supporting electrical, mechanical and material science experiment and analysis is presented.

Electrical measurements on shallow Si n+-p junction diodes with a 30-nm TiSi2 contacting layer demonstrate that an 80-nm-thick amorphous Ta36Si14N50 film prepared by reactive RF sputtering of a Ta5Si3 target in an Ar/N2 plasma very effectively prevents the interaction between the Si substrate with the TiSi2 contacting layer and a 500-nm Cu overlayer. The Ta36Si14N50 diffusion barrier maintains the integrity of the I-V characteristics up to 900 C for 30-min annealing in vacuum. It is concluded that the amorphous Ta36Si14N50 alloy is not only a material with a very low reactivity for copper, titanium, and silicon, but must have a small diffusivity for copper as well.

The thermal stability of reactively sputtered tungsten-nitrogen alloy thin films is investigated for the application as diffusion barriers in silicon contact metallizations. The composition of W-N barriers is varied over a wide range including pure W. Aluminum, gold, and silver are used as low resistivity overlayers. Metallurgical interactions at temperatures ranging from 500 to 900 C are studied. Incorporating nitrogen into tungsten advantageously stabilizes all three systems. The overall failure takes place rapidly above critical temperatures that depend on both the metal overlayer and the microstructure of the barrier. In some cases, W-N alloys can effectively prevent interdiffusion at temperatures as high as 800 C for 30 min.

Amorphous W-Zr and W-N alloys were investigated as diffusion barriers in silicon metallization schemes. Data were presented showing that amorphous W-Zr crystallizes at 900 C, which is 200 C higher than amorphous W-Ni films, and that both films react with metallic overlayers at temperatures far below the crystllization temperature. Also, W-N alloys (crystalline temperature of 600 C) were successfully incorporated as a diffusion barrier in contact structures with both Al and Ag overlayers. The thermal stability of the electrical characteristics of shallow n(+)p junctions significantly improved by incorporating W-N layers in the contact system. One important fact demonstated was the critical influence of the deposition parameters during formation of these carriers.

Diffusion barrier research was focussed on lowering the chemical reactivity of amorphous thin films on silicon. An additional area of concern is the reaction with metal overlays such as aluminum, silver, and gold. Gold was included to allow for technology transfer to gallium arsenide PV cells. Amorphous tungsten nitride films have shown much promise. Stability to annealing temperatures of 700, 800, and 550 C were achieved for overlays of silver, gold, and aluminum, respectively. The lower results for aluminum were not surprising because there is an eutectic that can form at a lower temperature. It seems that titanium and zirconium will remove the nitrogen from a tungsten nitride amorphous film and render it unstable. Other variables of research interest were substrate bias and base pressure during sputtering.