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Wireless Network-on-Chip (WNoC) is a promising concept which provides a solution to overcome the scalability issues in prevailing networks-in-package for many-core processors. However, the electromagnetic propagation inside the chip package leads to energy reverberation, resulting in Inter-Symbol Interference (ISI) with high delay spreads. Time Reversal (TR) is a technique that benefits the unique time-invariant channel with rich multipath effects to focus the energy to the desired transceiver. TR mitigates both ISI and co-channel interference, hence providing parallel communications in both space and time. Thus, TR is a versatile candidate to improve the aggregate bandwidth of wireless on-chip networks provided that a Medium Access Control (MAC) is used to efficiently share the wireless medium. In this paper, we explore a simple yet resilient TR-based MAC protocol (TR-MAC) design for WNoC. We propose to manage multiple parallel transmissions with simultaneous spatial channels in the same time slot with TR precoding and focused energy detection at the transceiver. Our results show that TR-MAC can be employed in massive computing architectures with improved latency and throughput while matching with the stringent requirements of the physical layer.

Quantum computers are expected to scale in size to close the gap that currently exists between quantum algorithms and quantum hardware. To this end, quantum compilation techniques must scale along with the hardware constraints, shifting the current paradigm of obtaining an optimal compilation to relying on heuristics that allow for a fast solution, even though the quality of such a solution may not be optimal. Significant concerns arise as the execution time of current mapping techniques experiences a notable increase when applied to quantum computers with a high number of qubits. In this work, we present Route-Forcing, a quantum circuit mapping algorithm that shows an average speedup of $3.7\times$ compared to the state-of-the-art scalable techniques, reducing the depth of the mapped circuit by $4.7 \times$ at the expense of adding $1.3 \times$ more SWAP gates. Moreover, the proposed mapping algorithm is adapted and tuned for what is expected to be the next generation of quantum computers, in which different processors are interconnected to increase the total number of qubits, allowing for more complex computations., Comment: Accepted to IEEE QCE 2024

Modularity is a promising approach for scaling up quantum computers and therefore integrating higher qubit counts. The essence of such architectures lies in their reliance on high-fidelity and fast quantum state transfers enabled by generating entanglement between chips. In addressing the challenge of implementing quantum coherent communication channels to interconnect quantum processors, various techniques have been proposed to account for qubit technology specifications and the implemented communication protocol. By employing Design Space Exploration (DSE) methodologies, this work presents a comparative analysis of the cavity-mediated interconnect technologies according to a defined figure of merit, and we identify the configurations related to the cavity and atomic decay rates as well as the qubit-cavity coupling strength that meet the efficiency thresholds. We therefore contribute to benchmarking contemporary cavity-mediated quantum interconnects and guide the development of reliable and scalable chip-to-chip links for modular quantum computers., Comment: 6 pages, 4 figures

Application-specific quantum computers offer the most efficient means to tackle problems intractable by classical computers. Realizing these architectures necessitates a deep understanding of quantum circuit properties and their relationship to execution outcomes on quantum devices. Our study aims to perform for the first time a rigorous examination of quantum circuits by introducing graph theory-based metrics extracted from their qubit interaction graph and gate dependency graph alongside conventional parameters describing the circuit itself. This methodology facilitates a comprehensive analysis and clustering of quantum circuits. Furthermore, it uncovers a connection between parameters rooted in both qubit interaction and gate dependency graphs, and the performance metrics for quantum circuit mapping, across a range of established quantum device and mapping configurations. Among the various device configurations, we particularly emphasize modular (i.e., multi-core) quantum computing architectures due to their high potential as a viable solution for quantum device scalability. This thorough analysis will help us to: i) identify key attributes of quantum circuits that affect the quantum circuit mapping performance metrics; ii) predict the performance on a specific chip for similar circuit structures; iii) determine preferable combinations of mapping techniques and hardware setups for specific circuits; and iv) define representative benchmark sets by clustering similarly structured circuits.

The Artificial Intelligence field is flooded with optimisation methods. In this paper, we change the focus to developing modelling methods with the aim of getting us closer to Artificial General Intelligence. To do so, we propose a novel way to interpret reality as an information source, that is later translated into a computational framework able to capture and represent such information. This framework is able to build elements of classical cognitive architectures, like Long Term Memory and Working Memory, starting from a simple primitive that only processes Spatial Distributed Representations. Moreover, it achieves such level of verticality in a seamless scalable hierarchical way., Comment: To be published by AGI 2024 conference proceedings

Wireless Network-on-Chip (WNoC) has been proposed as a low-latency, versatile, and broadcast-capable complement to current interconnects in the quest for satisfying the ever-increasing communications needs of modern computing systems. However, to realize the promise of WNoC, multiple wireless links operating at several tens of Gb/s need to be created within a computing package. Unfortunately, the highly integrated and enclosed nature of such computing packages incurs significant Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), not only preventing the deployment of multiple spatial channels, but also severely limiting the symbol rate of each individual channel. In this work, Time Reversal (TR) is proposed as a means to compensate the channel impairments and enable multiple concurrent high-speed links at the chip scale. We offer evidence, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude and allow the deployment of multiple concurrent links towards achieving aggregate speeds in excess of 100 Gb/s. Finally, the challenges relative to the realization of TR at the chip scale are analyzed from the implementation, protocol support, and architectural perspectives.

The concept of Wireless Network-on-Chip (WNoC) has emerged as a potential solution to address the escalating communication demands of modern computing systems due to their low-latency, versatility, and reconfigurability. However, for WNoC to fulfill its potential, it is essential to establish multiple high-speed wireless links across chips. Unfortunately, the compact and enclosed nature of computing packages introduces significant challenges in the form of Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), which not only hinder the deployment of multiple spatial channels but also severely restrict the symbol rate of each individual channel. In this paper, we posit that Time Reversal (TR) could be effective in addressing both impairments in this static scenario thanks to its spatiotemporal focusing capabilities even in the near field. Through comprehensive full-wave simulations and bit error rate analysis in multiple scenarios and at multiple frequency bands, we provide evidence that TR can increase the symbol rate by an order of magnitude, enabling the deployment of multiple concurrent links and achieving aggregate speeds exceeding 100 Gb/s. Finally, we evaluate the impact of reducing the sampling rate of the TR filter on the achievable speeds, paving the way to practical TR-based wireless communications at the chip scale.

Quantum computing represents a paradigm shift in computation, offering the potential to solve complex problems intractable for classical computers. Although current quantum processors already consist of a few hundred of qubits, their scalability remains a significant challenge. Modular quantum computing architectures have emerged as a promising approach to scale up quantum computing systems. This paper delves into the critical aspects of distributed multi-core quantum computing, focusing on quantum circuit mapping, a fundamental task to successfully execute quantum algorithms across cores while minimizing inter-core communications. We derive the theoretical bounds on the number of non-local communications needed for random quantum circuits and introduce the Hungarian Qubit Assignment (HQA) algorithm, a multi-core mapping algorithm designed to optimize qubit assignments to cores with the aim of reducing inter-core communications. Our exhaustive evaluation of HQA against state-of-the-art circuit mapping algorithms for modular architectures reveals a $4.9\times$ and $1.6\times$ improvement in terms of execution time and non-local communications, respectively, compared to the best performing algorithm. HQA emerges as a very promising scalable approach for mapping quantum circuits into multi-core architectures, positioning it as a valuable tool for harnessing the potential of quantum computing at scale., Comment: Accepted to ACM Transaction in Quantum Computing

The upcoming landscape of Earth Observation missions will defined by networked heterogeneous nanosatellite constellations required to meet strict mission requirements, such as revisit times and spatial resolution. However, scheduling satellite communications in these satellite networks through efficiently creating a global satellite Contact Plan (CP) is a complex task, with current solutions requiring ground-based coordination or being limited by onboard computational resources. The paper proposes a novel approach to overcome these challenges by modeling the constellations and CP as dynamic networks and employing graph-based techniques. The proposed method utilizes a state-of-the-art dynamic graph neural network to evaluate the performance of a given CP and update it using a heuristic algorithm based on simulated annealing. The trained neural network can predict the network delay with a mean absolute error of 3.6 minutes. Simulation results show that the proposed method can successfully design a contact plan for large satellite networks, improving the delay by 29.1%, similar to a traditional approach, while performing the objective evaluations 20x faster., Comment: 8 pages, 5 figures, conference

Designing efficient quantum processor topologies is pivotal for advancing scalable quantum computing architectures. The communication overhead, a critical factor affecting the execution fidelity of quantum circuits, arises from inevitable qubit routing that brings interacting qubits into physical proximity by the means of serial SWAP gates to enable the direct two-qubit gate application. Characterizing the qubit movement across the processor is crucial for tailoring techniques for minimizing the SWAP gates. This work presents a comparative analysis of the resulting communication overhead among three processor topologies: star, heavy-hexagon lattice, and square lattice topologies, according to performance metrics of communication-to-computation ratio, mean qubit hotspotness, and temporal burstiness, showcasing that the square lattice layout is favourable for quantum computer architectures at a scale., Comment: 5 pages, 5 figures

Quantum computing holds immense potential for solving classically intractable problems by leveraging the unique properties of quantum mechanics. The scalability of quantum architectures remains a significant challenge. Multi-core quantum architectures are proposed to solve the scalability problem, arising a new set of challenges in hardware, communications and compilation, among others. One of these challenges is to adapt a quantum algorithm to fit within the different cores of the quantum computer. This paper presents a novel approach for circuit partitioning using Deep Reinforcement Learning, contributing to the advancement of both quantum computing and graph partitioning. This work is the first step in integrating Deep Reinforcement Learning techniques into Quantum Circuit Mapping, opening the door to a new paradigm of solutions to such problems.

Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) devices era. Based upon interconnecting tens to hundreds of quantum cores via a quantum intranet, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation, and therefore enables executing large-scale algorithms on quantum computers. In order to optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would also provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a pioneering characterization of the spatio-temporal inter-core qubit traffic in large-scale circuits. The programs are executed on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the scalability of the presented algorithms, provide a set of guidelines to improve mapping quantum circuits to multi-core processors, and lay the foundations of benchmarking large-scale multi-core architectures., Comment: 34 pages, 9 figures

Modular quantum computing architectures offer a promising alternative to monolithic designs for overcoming the scaling limitations of current quantum computers. To achieve scalability beyond small prototypes, quantum architectures are expected to adopt a modular approach, featuring clusters of tightly connected quantum bits with sparser connections between these clusters. Efficiently distributing qubits across multiple processing cores is critical for improving quantum computing systems' performance and scalability. To address this challenge, we propose the Hungarian Qubit Assignment (HQA) algorithm, which leverages the Hungarian algorithm to improve qubit-to-core assignment. The HQA algorithm considers the interactions between qubits over the entire circuit, enabling fine-grained partitioning and enhanced qubit utilization. We compare the HQA algorithm with state-of-the-art alternatives through comprehensive experiments using both real-world quantum algorithms and random quantum circuits. The results demonstrate the superiority of our proposed approach, outperforming existing methods, with an average improvement of 1.28$\times$.

Quantum computing has revolutionized the field of computer science with its extraordinary ability to handle classically intractable problems. To realize its potential, however, quantum computers need to scale to millions of qubits, a feat that will require addressing fascinating yet extremely challenging interconnection problems. In this paper, we provide a context analysis of the nascent quantum computing field from the perspective of communications, with the aim of encouraging the on-chip networks community to contribute and pave the way for truly scalable quantum computers in the decades to come., Comment: 6 pages, 4 figures; appearing in Proceedings of the IEEE/ACM NoCArc 2023

Wireless communications in the terahertz band have been recently proposed as complement to conventional wired interconnects within computing packages. Such environments are typically highly reverberant, hence showing long channel impulse responses and severely limiting the achievable rates. Fortunately, this communications scenario is static and can be pre-characterized, which opens the door to techniques such as time reversal. Time reversal acts a spatial matched filter and has a spatiotemporal focusing effect, which allows not only to increase the achievable symbol rates, but also to create multiple spatial channels. In this paper, the multi-user capability of time reversal is explored in the context of wireless communications in the terahertz band within a computing package. Full-wave simulations are carried out to validate the approach, whereas modulation streams are simulated to evaluate the error rate as a function of the transmitted power, symbol rate, and number of simultaneous transmissions.

Recently emerged Topological Deep Learning (TDL) methods aim to extend current Graph Neural Networks (GNN) by naturally processing higher-order interactions, going beyond the pairwise relations and local neighborhoods defined by graph representations. In this paper we propose a novel TDL-based method for compressing signals over graphs, consisting in two main steps: first, disjoint sets of higher-order structures are inferred based on the original signal --by clustering $N$ datapoints into $K\ll N$ collections; then, a topological-inspired message passing gets a compressed representation of the signal within those multi-element sets. Our results show that our framework improves both standard GNN and feed-forward architectures in compressing temporal link-based signals from two real-word Internet Service Provider Networks' datasets --from $30\%$ up to $90\%$ better reconstruction errors across all evaluation scenarios--, suggesting that it better captures and exploits spatial and temporal correlations over the whole graph-based network structure., Comment: Accepted as Oral at the Second Learning on Graphs Conference (LoG 2023). The recording of the talk can be found in https://www.youtube.com/watch?v=OcruIkiRkiU

Wireless Network-on-Chip (WNoC) is a promising paradigm to overcome the versatility and scalability issues of conventional on-chip networks for current processor chips. However, the chip environment suffers from delay spread which leads to intense Inter-Symbol Interference (ISI). This degrades the signal when transmitting and makes it difficult to achieve the desired Bit Error Rate (BER) in this constraint-driven scenario. Time reversal (TR) is a technique that uses the multipath richness of the channel to overcome the undesired effects of the delay spread. As the flip-chip channel is static and can be characterized beforehand, in this paper we propose to apply TR to the wireless in-package channel. We evaluate the effects of this technique in time and space from an electromagnetic point of view. Furthermore, we study the effectiveness of TR in modulated data communications in terms of BER as a function of transmission rate and power. Our results show not only the spatiotemporal focusing effect of TR in a chip that could lead to multiple spatial channels, but also that transmissions using TR outperform, BER-wise, non-TR transmissions it by an order of magnitude

Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate., Comment: Submitted to IEEE QCE 2023

Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect., Comment: 5 pages, 2 figures, accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 2023

Nanoscale devices with Terahertz (THz) communication capabilities are envisioned to be deployed within human bloodstreams. Such devices will enable fine-grained sensing-based applications for detecting early indications (i.e., biomarkers) of various health conditions, as well as actuation-based ones such as targeted drug delivery. Associating the locations of such events with the events themselves would provide an additional utility for precision diagnostics and treatment. This vision yielded a new class of in-body localization coined under the term "flow-guided nanoscale localization". Such localization can be piggybacked on THz communication for detecting body regions in which biological events were observed based on the duration of one circulation of a nanodevice in the bloodstream. From a decades-long research on objective benchmarking of "traditional" indoor localization, as well as its eventual standardization (e.g., ISO/IEC 18305:2016), we know that in early stages the reported performance results were often incomplete (e.g., targeting a subset of relevant performance metrics), carrying out benchmarking experiments in different evaluation environments and scenarios, and utilizing inconsistent performance indicators. To avoid such a "lock-in" in flow-guided localization, in this paper we propose a workflow for standardized performance evaluation of such localization. The workflow is implemented in the form of an open-source simulation framework that is able to jointly account for the mobility of the nanodevices, in-body THz communication between with on-body anchors, and energy-related and other technological constraints (e.g., pulse-based modulation) at the nanodevice level. Accounting for these constraints, the framework is able to generate the raw data that can be streamlined into different flow-guided localization solutions for generating standardized performance benchmarks., Comment: 6 pages, 4 figures, 16 references, available at: https://bitbucket.org/filip_lemic/flow-guided-localization-in-ns3/src/sequential/

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using long random vectors known as hypervectors. Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) has shown promise as it is very efficient in performing matrix-vector multiplications, which are common in the HDC algebra. Although HDC architectures based on IMC already exist, how to scale them remains a key challenge due to collective communication patterns that these architectures required and that traditional chip-scale networks were not designed for. To cope with this difficulty, we propose a scale-out HDC architecture called WHYPE, which uses wireless in-package communication technology to interconnect a large number of physically distributed IMC cores that either encode hypervectors or perform multiple similarity searches in parallel. In this context, the key enabler of WHYPE is the opportunistic use of the wireless network as a medium for over-the-air computation. WHYPE implements an optimized source coding that allows receivers to calculate the bit-wise majority of multiple hypervectors (a useful operation in HDC) being transmitted concurrently over the wireless channel. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. Through evaluations at the on-chip network and complete architecture levels, we demonstrate that WHYPE can bundle and distribute hypervectors faster and more efficiently than a hypothetical wired implementation, and that it scales well to tens of receivers. We show that the average error rate of the majority computation is low, such that it has negligible impact on the accuracy of HDC classification tasks., Comment: Accepted at IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS). arXiv admin note: text overlap with arXiv:2205.10889

Wireless communications at the chip scale emerge as a interesting complement to traditional wire-based approaches thanks to their low latency, inherent broadcast nature, and capacity to bypass pin constraints. However, as current trends push towards massive and bandwidth-hungry processor architectures, there is a need for wireless chip-scale networks that exploit and share as many channels as possible. In this context, this work addresses the issue of channel sharing by exploring the design space of multi-channel Medium Access Control (MAC) protocols for chip-scale networks. Distinct channel assignment strategies for both random access and token passing are presented and evaluated under realistic traffic patterns. It is shown that, even with the improvements enabled by the multiple channels, both protocols maintain their intrinsic advantages and disadvantages., Comment: Accepted for lecture presentation at IEEE ISCAS 2023

We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may be attributed to increased charge carrier density in the channel and thus reduced saturation velocity due to carrier-carrier scattering.

Wireless Networks-on-Chip (WNoCs) are regarded as a disruptive alternative to conventional interconnection networks at the chip scale, yet limited by the relatively low aggregate bandwidth of such wireless networks. Hence, any method to increase the amount of concurrent channels in this scenario is of high value. In this direction, and since WNoC implies close integration of multiple antennas on a chip anyway, in this paper we present a feasibility study of compact monopole antenna arrays in a flip-chip environment at millimeter-wave and sub-terahertz frequencies. By means of a full-wave solver, we evaluate the feasibility to create, at will, concentrations of field in different spots of the chip. This way, we set the steps towards spatial multiplexing that enables concurrent multicast communications and also increases the aggregate bandwidth of the wireless network. Our results at 60 GHz show two clearly separable parallel channels that radiate simultaneously from two opposite corners of the chip, achieving a Signal-to-Interference Ratio (SIR) of around 40 dB, which proves that the channels are independent of each other even in such an enclosed environment. Further, we see potential to expand our approach to three or more concurrent channels, and to frequencies beyond 100 GHz.

Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects., Comment: 7 pages, to be presented at the ACM NanoCom 2022

Analog In-Memory Computing (AIMC) is emerging as a disruptive paradigm for heterogeneous computing, potentially delivering orders of magnitude better peak performance and efficiency over traditional digital signal processing architectures on Matrix-Vector multiplication. However, to sustain this throughput in real-world applications, AIMC tiles must be supplied with data at very high bandwidth and low latency; this poses an unprecedented pressure on the on-chip communication infrastructure, which becomes the system's performance and efficiency bottleneck. In this context, the performance and plasticity of emerging on-chip wireless communication paradigms provide the required breakthrough to up-scale on-chip communication in large AIMC devices. This work presents a many-tile AIMC architecture with inter-tile wireless communication that integrates multiple heterogeneous computing clusters, embedding a mix of parallel RISC-V cores and AIMC tiles. We perform an extensive design space exploration of the proposed architecture and discuss the benefits of exploiting emerging on-chip communication technologies such as wireless transceivers in the millimeter-wave and terahertz bands.

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) systems have been recently proved to be one of the most energy-efficient options, due to hypervector manipulations in the memory itself that reduces data movement. Although implementations of HDC on single IMC cores have been made, their parallelization is still unresolved due to the communication challenges that these novel architectures impose and that traditional Networks-on-Chip and Networks-in-Package were not designed for. To cope with this difficulty, we propose the use of wireless on-chip communication technology in unique ways. We are particularly interested in physically distributing a large number of IMC cores performing similarity search across a chip, and maintaining the classification accuracy when each of which is queried with a slightly different version of a bundled hypervector. To achieve it, we introduce a novel over-the-air computing that consists of defining different binary decision regions in the receivers so as to compute the logical majority operation (i.e., bundling, or superposition) required in HDC. It introduces moderate overheads of a single antenna and receiver per IMC core. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. It is demonstrated that the proposed approach allows to both bundle at least three hypervectors and scale similarity search to 64 IMC cores seamlessly, while incurring an average bit error ratio of 0.01 without any impact in the accuracy of a generic HDC-based classifier working with 512-bit vectors., Comment: This paper has been accepted at 2022 IEEE International Joint Conference on Neural Networks (IJCNN)

The next generation of wireless networks is expected to tap into the terahertz (0.1--10 THz) band to satisfy the extreme latency and bandwidth density requirements of future applications. However, the development of systems in this band is challenging as THz waves confront severe spreading and penetration losses, as well as molecular absorption, which leads to strong line-of-sight requirements through highly directive antennas. Recently, reconfigurable intelligent surfaces (RISs) have been proposed to address issues derived from non-line-of-sight propagation, among other impairments, by redirecting the incident wave toward the receiver and implementing virtual-line-of-sight communications. However, the benefits provided by a RIS may be lost if the network operates at multiple bands. In this position paper, the suitability of the RIS paradigm in indoor THz scenarios for 6G is assessed grounded on the analysis of a tunable graphene-based RIS that can operate in multiple wideband transparency windows. A possible implementation of such a RIS is provided and numerically evaluated at 0.65/0.85/1.05 THz separately, demonstrating that beam steering and other relevant functionalities are realizable with excellent performance. Finally, the challenges associated with the design and fabrication of multi-wideband graphene-based RISs are discussed, paving the way to the concurrent control of multiple THz bands in the context of 6G networks., Comment: in IEEE Vehicular Technology Magazine, 2022

In this work, we examine the potential of autonomous operation of a reconfigurable intelligent surface (RIS) using wireless energy harvesting from information signals. To this end, we first identify the main RIS power-consuming components and introduce a suitable power-consumption model. Subsequently, we introduce a novel RIS power-splitting architecture that enables simultaneous energy harvesting and beamsteering. Specifically, a subset of the RIS unit cells (UCs) is used for beamsteering while the remaining ones absorb energy. For the subset allocation, we propose policies obtained as solutions to two optimization problems. The first problem aims at maximizing the signal-to-noise ratio (SNR) at the receiver without violating the RIS's energy harvesting demands. Additionally, the objective of the second problem is to maximize the RIS harvested power, while ensuring an acceptable SNR at the receiver. We prove that under particular propagation conditions, some of the proposed policies deliver the optimal solution of the two problems. Furthermore, we report numerical results that reveal the efficiency of the policies with respect to the optimal and very high-complexity brute-force design approach. Finally, through a case study of user tracking, we showcase that the RIS power-consumption demands can be secured by harvesting energy from information signals., Comment: 31 pages, 8 figures

The reconfigurable intelligent surface is a promising technology for the manipulation and control of wireless electromagnetic signals. In particular, it has the potential to provide significant performance improvements for wireless networks. However, to do so, a proper reconfiguration of the reflection coefficients of unit cells is required, which often leads to complex and expensive devices. To amortize the cost, one may share the system resources among multiple transmitters and receivers. In this paper, we propose an efficient reconfiguration technique providing control over multiple beams independently. Compared to time-consuming optimization techniques, the proposed strategy utilizes an analytical method to configure the surface for multi-beam radiation. This method is easy to implement, effective and efficient since it only requires phase reconfiguration. We analyze the performance for indoor and outdoor scenarios, given the broadcast mode of operation. The aforesaid scenarios encompass some of the most challenging scenarios that wireless networks encounter. We show that our proposed technique provisions sufficient improvements in the observed channel capacity when the receivers are close to the surface in the indoor office environment scenario. Further, we report a considerable increase in the system throughput given the outdoor environment.

Graphene supports surface plasmon polaritons with comparatively slow propagation velocities in the THz region, which becomes increasingly interesting for future communication technologies. This ability can be used to realize compact antennas, which are up to two orders of magnitude smaller than their metallic counterparts. For a proper functionality of these antennas some minimum material requirements have to be fulfilled, which are presently difficult to achieve, since the fabrication and transfer technologies for graphene are still evolving. In this work we analyze available graphene materials experimentally and extract intrinsic characteristics at THz frequencies, in order to predict the dependency of the THz signal emission threshold as a function of the graphene relaxation time tau_r and the chemical potential mu_c., Comment: 2 pages, 1 table

Relational data present in real world graph representations demands for tools capable to study it accurately. In this regard Graph Neural Network (GNN) is a powerful tool, wherein various models for it have also been developed over the past decade. Recently, there has been a significant push towards creating accelerators that speed up the inference and training process of GNNs. These accelerators, however, do not delve into the impact of their dataflows on the overall data movement and, hence, on the communication requirements. In this paper, we formulate analytical models that capture the amount of data movement in the most recent GNN accelerator frameworks. Specifically, the proposed models capture the dataflows and hardware setup of these accelerator designs and expose their scalability characteristics for a set of hardware, GNN model and input graph parameters. Additionally, the proposed approach provides means for the comparative analysis of the vastly different GNN accelerators., Comment: ISCAS 2021

Graph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of reconfigurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for mappers or design-space exploration tools to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNN inference, spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution., Comment: Accepted for publication at the 36th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2022)

Nanoscale wireless networks are expected to revolutionize a variety of domains, with significant advances conceivable in in-body healthcare. In healthcare, these nanonetworks will consist of energy-harvesting nanodevices passively flowing through the bloodstream, taking actions at certain locations, and communicating results to more powerful Body Area Network (BAN) nodes. Assuming such a setup and electromagnetic nanocommunication in the Terahertz (THz) frequencies, we propose a network architecture that can support fine-grained localization of the energy-harvesting in-body nanonodes, as well as their two-way communication with the outside world. The main novelties of our proposal lie in the introduction of location-aware and Wake-up Radio (WuR)-based wireless nanocommunication paradigms, as well as Software-Defined Metamaterials (SDMs), to THz-operating energy-harvesting in-body nanonetworks. We argue that, on a high level, the proposed architecture can handle (and actually benefits from) a large number of nanonodes, while simultaneously dealing with a short range of THz in-body propagation and highly constrained nanonodes., Comment: 7 pages, 5 figures, 1 table

Metasurfaces, the two-dimensional counterpart of metamaterials, have caught great attention thanks to their powerful capabilities on manipulation of electromagnetic waves. Recent times have seen the emergence of a variety of metasurfaces exhibiting not only countless functionalities, but also a reconfigurable response. Additionally, digital or coding metasurfaces have revolutionized the field by describing the device as a matrix of discrete building block states, thus drawing clear parallelisms with information theory and opening new ways to model, compose, and (re)program advanced metasurfaces. This paper joins the reconfigurable and digital approaches, and presents a metasurface that leverages the tunability of graphene to perform beam steering at terahertz frequencies. A comprehensive design methodology is presented encompassing technological, unit cell design, digital metamaterial synthesis, and programmability aspects. By setting up and dynamically adjusting a phase gradient along the metasurface plane, the resulting device achieves beam steering at all practical directions. The proposed design is studied through analytical models and validated numerically, showing beam widths and steering errors well below 10 degrees and 5% in most cases. Finally, design guidelines are extracted through a scalability analysis involving the metasurface size and number of unit cell states., Comment: 12 pages

Deep neural network (DNN) models continue to grow in size and complexity, demanding higher computational power to enable real-time inference. To efficiently deliver such computational demands, hardware accelerators are being developed and deployed across scales. This naturally requires an efficient scale-out mechanism for increasing compute density as required by the application. 2.5D integration over interposer has emerged as a promising solution, but as we show in this work, the limited interposer bandwidth and multiple hops in the Network-on-Package (NoP) can diminish the benefits of the approach. To cope with this challenge, we propose WIENNA, a wireless NoP-based 2.5D DNN accelerator. In WIENNA, the wireless NoP connects an array of DNN accelerator chiplets to the global buffer chiplet, providing high-bandwidth multicasting capabilities. Here, we also identify the dataflow style that most efficienty exploits the wireless NoP's high-bandwidth multicasting capability on each layer. With modest area and power overheads, WIENNA achieves 2.2X--5.1X higher throughput and 38.2% lower energy than an interposer-based NoP design., Comment: ASPDAC '21

Metasurfaces are envisaged to play a key role in next-generation wireless systems due to their powerful control over electromagnetic waves. The last decade has witnessed huge advances in this regard, shifting from static to programmable metasurfaces. The HyperSurface (HSF) paradigm takes one step further by integrating a network of controllers within the device with the aim of adding intelligence, connectivity, and autonomy. However, little is known about the traffic that this network will have to support as the target electromagnetic function or boundary conditions change. In this paper, we lay down the foundations of a methodology to characterize the workload of programmable metasurfaces and then employ it to analyze the case of beam steering HSFs. We observe that traffic is bursty and highly dependent on the position of the target. These results will enable the early-stage evaluation of intra-HSF networks, as well as the estimation of the system performance and cost.

Software-Defined Metamaterials (SDMs) show a strong potential for advancing the engineered control of electromagnetic waves. As such, they are envisioned to enable a variety of exciting applications, among others in the domains of smart textiles, high-resolution structural monitoring, and sensing in challenging environments. Many of the applications envisage deformations of the SDM structures, such as their bending, stretching or rolling, which implies that the locations of metamaterial elements will be changing relative to one another. In this paper, we argue that if the metamaterial elements would be accurately localizable, this location information could potentially be utilized for enabling novel SDM applications, as well as for optimizing the control of the elements themselves. To enable their localization, we assume that these elements are controlled wirelessly through a Terahertz (THz)-operating nanonetwork. We consider the elements to be power-constrained, with their sole powering option being to harvest energy from different environmental sources. By means of simulation, we demonstrate sub-millimeter accuracy of the two-way Time of Flight (ToF)-based localization, as well as high availability of the service (i.e., consistently more than 80% of the time), which is a result of the low energy consumed in the localization process. Finally, we qualitatively characterize the latency of the proposed localization service, as well as outline several challenges and future research directions., Comment: 49 pages, 19 figures, 2 tables

Graph Neural Networks (GNNs) have exploded onto the machine learning scene in recent years owing to their capability to model and learn from graph-structured data. Such an ability has strong implications in a wide variety of fields whose data is inherently relational, for which conventional neural networks do not perform well. Indeed, as recent reviews can attest, research in the area of GNNs has grown rapidly and has lead to the development of a variety of GNN algorithm variants as well as to the exploration of groundbreaking applications in chemistry, neurology, electronics, or communication networks, among others. At the current stage of research, however, the efficient processing of GNNs is still an open challenge for several reasons. Besides of their novelty, GNNs are hard to compute due to their dependence on the input graph, their combination of dense and very sparse operations, or the need to scale to huge graphs in some applications. In this context, this paper aims to make two main contributions. On the one hand, a review of the field of GNNs is presented from the perspective of computing. This includes a brief tutorial on the GNN fundamentals, an overview of the evolution of the field in the last decade, and a summary of operations carried out in the multiple phases of different GNN algorithm variants. On the other hand, an in-depth analysis of current software and hardware acceleration schemes is provided, from which a hardware-software, graph-aware, and communication-centric vision for GNN accelerators is distilled., Comment: 35 pages, 9 figures, 8 tables, 188 references

Being a very promising technology, with impressive advances in the recent years, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Although continued progress in the fabrication and control of qubits is required, quantum computing scalability will depend as well on a comprehensive architectural design considering a multi-core approach as an alternative to the traditional monolithic version, hence including a communications perspective. However, this goes beyond introducing mere interconnects. Rather, it implies consolidating the full communications stack in the quantum computer architecture. In this paper, we propose a double full-stack architecture encompassing quantum computation and quantum communications, which we use to address the monolithic versus multi-core question with a structured design methodology. For that, we revisit the different quantum computing layers to capture and model their essence by highlighting the open design variables and performance metrics. Using behavioral models and actual measurements from existing quantum computers, the results of simulations suggest that multi-core architectures may effectively unleash the full quantum computer potential., Comment: 15 pages, 9 figures

As the current standardization for the 5G networks nears completion, work towards understanding the potential technologies for the 6G wireless networks is already underway. One of these potential technologies for the 6G networks are Reconfigurable Intelligent Surfaces (RISs). They offer unprecedented degrees of freedom towards engineering the wireless channel, i.e., the ability to modify the characteristics of the channel whenever and however required. Nevertheless, such properties demand that the response of the associated metasurface (MSF) is well understood under all possible operational conditions. While an understanding of the radiation pattern characteristics can be obtained through either analytical models or full wave simulations, they suffer from inaccuracy under certain conditions and extremely high computational complexity, respectively. Hence, in this paper we propose a novel neural networks based approach that enables a fast and accurate characterization of the MSF response. We analyze multiple scenarios and demonstrate the capabilities and utility of the proposed methodology. Concretely, we show that this method is able to learn and predict the parameters governing the reflected wave radiation pattern with an accuracy of a full wave simulation (98.8%-99.8%) and the time and computational complexity of an analytical model. The aforementioned result and methodology will be of specific importance for the design, fault tolerance and maintenance of the thousands of RISs that will be deployed in the 6G network environment., Comment: Submitted to IEEE OJ-COMS

Programmable metasurfaces have garnered significant attention as they confer unprecedented control over the electromagnetic response of any surface. Such feature has given rise to novel design paradigms such as Software-Defined Metamaterials (SDM) and Reconfigurable Intelligent Surfaces (RIS) with multiple groundbreaking applications. However, the development of programmable metasurfaces tailored to the particularities of a potentially broad application pool becomes a daunting task because the design space becomes remarkably large. This paper aims to ease the design process by proposing a methodology that, through a semi-analytical model of the metasurface response, allows to derive performance scaling trends as functions of a representative set of design variables. Although the methodology is amenable to any electromagnetic functionality, this paper explores its use for the case of beam steering at 26 GHz for 5G applications. Conventional beam steering metrics are evaluated as functions of the unit cell size, number of unit cell states, and metasurface size for different incidence and reflection angles. It is shown that metasurfaces 5$\lambda\times$5$\lambda$ or larger with unit cells of $\lambda/3$ and four unit cell states ensure good performance overall. Further, it is demonstrated that performance degrades significantly for angles larger than $\theta > 60^o$ and that, to combat this, extra effort is needed in the development of the unit cell. These performance trends, when combined with power and cost models, will pave the way to optimal metasurface dimensioning.

Deep Neural Networks have flourished at an unprecedented pace in recent years. They have achieved outstanding accuracy in fields such as computer vision, natural language processing, medicine or economics. Specifically, Convolutional Neural Networks (CNN) are particularly suited to object recognition or identification tasks. This, however, comes at a high computational cost, prompting the use of specialized GPU architectures or even ASICs to achieve high speeds and energy efficiency. ASIC accelerators streamline the execution of certain dataflows amenable to CNN computation that imply the constant movement of large amounts of data, thereby turning on-chip communication into a critical function within the accelerator. This paper studies the communication flows within CNN inference accelerators of edge devices, with the aim to justify current and future decisions in the design of the on-chip networks that interconnect their processing elements. Leveraging this analysis, we then qualitatively discuss the potential impact of introducing the novel paradigm of wireless on-chip network in this context., Comment: ICECS2019

Recent developments in nanotechnology herald nanometer-sized devices expected to bring light to a number of groundbreaking applications. Communication with and among nanodevices will be needed for unlocking the full potential of such applications. As the traditional communication approaches cannot be directly applied in nanocommunication, several alternative paradigms have emerged. Among them, electromagnetic nanocommunication in the terahertz (THz) frequency band is particularly promising, mainly due to the breakthrough of novel materials such as graphene. For this reason, numerous research efforts are nowadays targeting THz band nanocommunication and consequently nanonetworking. As it is expected that these trends will continue in the future, we see it beneficial to summarize the current status in these research domains. In this survey, we therefore aim to provide an overview of the current THz nanocommunication and nanonetworking research. Specifically, we discuss the applications envisioned to be supported by nanonetworks operating in the THz band, together with the requirements such applications pose on the underlying nanonetworks. Subsequently, we provide an overview of the current contributions on the different layers of the protocol stack, as well as the available channel models and experimentation tools. As the final contribution, we identify a number of open research challenges and outline several potential future research directions., Comment: 37 pages, 11 figures, 7 tables

Software-defined metasurfaces are electromagnetically ultra-thin, artificial components that can provide engineered and externally controllable functionalities. The control over these functionalities is enabled by the metasurface tunability, which is implemented by embedded electronic circuits that modify locally the surface resistance and reactance. Integrating controllers within the metasurface cells, able to intercommunicate and adaptively reconfigure it, thus imparting a desired electromagnetic operation, opens the path towards the creation of an artificially intelligent (AI) fabric where each unit cell can have its own sensing, programmable computing, and actuation facilities. In this work we take a crucial step towards bringing the AI metasurface technology to emerging applications, in particular exploring the wireless mm-wave intercell communication capabilities in a software-defined HyperSurface designed for operation is the microwave regime. We examine three different wireless communication channels within the landscape of the reflective metasurface: Firstly, in the layer where the control electronics of the HyperSurface lie, secondly inside a dedicated layer enclosed between two metallic plates, and, thirdly, inside the metasurface itself. For each case we examine the physical implementation of the mm-wave transponder nodes, we quantify communication channel metrics, and we identify complexity vs. performance trade-offs.

Network-on-Chip (NoC) is currently the paradigm of choice to interconnect the different components of System-on-Chips (SoCs) or Chip Multiprocessors (CMPs). As the levels of integration continue to grow, however, current NoCs face significant scalability limitations and have prompted research in novel interconnect technologies. Among these, wireless intra-chip communications have been under intense scrutiny due to their low latency broadcast and architectural flexibility. Thus far, the practicality of the idea has been studied from the RF front-end and the network interface perspectives, whereas little to no attention has been placed on another essential component: the data converters. This article aims to fill this gap by providing a comprehensive analysis of the requirements of the scenario, as well as of the current performance and cost trends of Analog-to-Digital Converters (ADCs). Based on Murmann's data, we demonstrate that ADCs will not be a roadblock for the realization of wireless intra-chip communications although current designs do not meet their demands fully., Comment: Presented at DCIS 2018

Recent emergence of metasurfaces has enabled the development of ultra-thin flat optical components through different wavefront shaping techniques at various wavelengths. However, due to the non-adaptive nature of conventional metasurfaces, the focal point of the resulting optics needs to be fixed at the design stage, thus severely limiting its reconfigurability and applicability. In this paper, we aim to overcome such constraint by presenting a flat reflective component that can be reprogrammed to focus terahertz waves at a desired point in the near-field region. To this end, we first propose a graphene-based unit cell with phase reconfigurability, and then employ the coding metasurface approach to draw the phase profile required to set the focus on the target point. Our results show that the proposed component can operate close to the diffraction limit with high focusing range and low focusing error. We also demonstrate that, through appropriate automation, the reprogrammability of the metamirror could be leveraged to develop compact terahertz scanning and imaging systems, as well as novel reconfigurable components for terahertz wireless communications., Comment: 10 pages, 5 figures, published in Scientific Reports (Nature)

Metasurfaces, the two-dimensional counterpart of metamaterials, have caught great attention thanks to their powerful control over electromagnetic waves. Recent times have seen the emergence of a variety of metasurfaces exhibiting not only countless functionalities, but also a reconfigurable or even programmable response. Reconfigurability, however, entails the integration of tuning and control circuits within the metasurface structure and, as this new paradigm moves forward, new reliability challenges may arise. This paper examines, for the first time, the reliability problem in programmable metamaterials by proposing an error model and a general methodology for error analysis. To derive the error model, the causes and potential impact of faults are identified and discussed qualitatively. The methodology is presented and instantiated for beam steering, which constitutes a relevant example for programmable metasurfaces. Results show that performance degradation depends on the type of error and its spatial distribution and that, in beam steering, error rates over 10% can still be considered acceptable.

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and 7.3x, respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case., Comment: 12 pages, 10 figures. IEEE Transactions on Communications Journal, 2020