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This study shows the effects of an ultrathin Al2O3-doped ZnO (AZO) interlayer inserted between the channel layer and source/drain (S/D) electrodes on the electrical contact properties of amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs). In particular, Al2O3-doping ratio-dependent variations in electrical contacts were systemically investigated, which were modulated by adjusting the number of Al2O3 injection cycles during atomic-layer-deposition (ALD) of AZO. Consequently, a-IGZO TFTs using a 1.8-nm-thick AZO interlayer (IL) with an Al2O3:ZnO sub-cycle ratio of 2:8 showed the lowest specific contact resistivity of (4.2 ± 7.3) $\times 10^{-{7}}\,\,\Omega \cdot $ cm2. This value is three orders of magnitude lower than that of devices without the AZO IL. This substantial improvement could be attributed to the IL’s high electron concentration of $1.9\times 10^{{18}}$ /cm3, which greatly lowered the effective Schottky barrier height between IGZO and the S/D electrodes. This enhanced electrical contact led to a field-effect mobility increase from 38.8 ± 0.8 to 45. 3 ± 0.6 cm2/Vs.

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (μFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3NL TFT showed remarkable electrical performance: μFEof 77.1 ± 0.67 cm2/(V s), VTHof 0.70 ± 0.25 V, SSof 100 ± 10 mV/dec, and ION/OFFof 8.9 × 109with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTHof +0.27, −0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

This study investigates the effect of oxygen plasma (PO) on the crystalline structure of tellurium (Te) thin films during reactive sputtering. Introduction of oxygen radicals suppresses uncontrolled rapid growth of hexagonal Te crystals, amorphizing the deposited Te thin film. This amorphous phase changes to the hexagonal phase upon alumina encapsulation. A 4-nm-thick Te transistor with a PO of 7% exhibits outstanding device performances, with a field-effect mobility up to 40.8 cm2V−1s−1 and an on/off current modulation ratio up to $1.1\times 10^{{6}}$ . These behaviors originate from alleviated random polycrystallinity in the corresponding thin film. However, when PO increases above 7%, amorphization progresses further, and remnant oxygen ions hamper the growth of the hexagonal phase in Te thin film. Consequently, hole transport is degraded. This study suggests tellurium oxide as a crystallization retarder for high-performance p-channel Te transistors.

This study shows the effect of single spinel phase crystallization on drain-induced barrier lowering (DIBL) of indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) with submicron channel length. The 0.9- $\mu \text{m}$ -long amorphous IZTO (a-IZTO) TFT shows a poor DIBL of 318 mV/V. In contrast, a significant improvement in the DIBL is achieved in the single spinel phase IZTO (s-IZTO) TFT, which could be attributed to the suppression of lateral diffusion of oxygen vacancy ( $\text{V}_{\text {O}}{)}$ and low VO defects through crystallization-induced enforcement of metal-oxygen bonds. Consequently, 0.9- $\mu \text{m}$ -long s-IZTO TFT reveals a small DIBL of 92 mV/V as well as a high field-effect mobility of 90.1 cm2/Vs and a low subthreshold swing of 0.1 V/dec. In addition, reliability against external bias temperature stress is considerably improved through single-phase crystallization, leading to an insignificant threshold voltage shift of +0.4 (−0.4) V under positive (negative) bias stress with electric field of 2 (−2) MV/cm at 60 °C for 10,000 s, respectively, in the 0.9- $\mu \text{m}$ -long s-IZTO TFT.

In this article, the mechanism of stability in amorphous indium-gallium-zinc oxide ( ${a}$ -IGZO) thin-film transistors (TFTs) with a natural length of $\sim $ 8 nm was investigated from the perspective of hafnium oxide (HfO $_{{2}}{)}$ gate dielectric point defects. The point defects in HfO2 responded to external stresses such as electric field ( ${E}{)}$ and temperature. In particular, oxygen vacancies and the positively charged defects caused an abnormal negative shift in threshold voltage ( ${V}_{\text {TH}}{)}$ under positive gate bias temperature stress (PBTS). Therefore, reducing the positively charged defects was important to eliminate the abnormal behavior. Inserting a 0.7-nm-thick ultrathin SiO2 interlayer between ${a}$ -IGZO and optimized HfO2 further improved device performance including stability. Consequently, the resultant ${a}$ -IGZO TFT exhibited promising device performance with $\mu _{\text {FE}}$ of 22.3 ±0.5 cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ , subthreshold swing (SS) of 64 ±0.5 mVdec $^{-{1}}$ , hysteresis of 4 mV, and $\Delta {V}_{\text {TH}}$ of 124 mV under harsh PBTS with ${E}$ of 4 MV/cm at 80 °C for 3600 s.

This study investigated the effect of hydrogen (H) on the performance of amorphous In–Ga–Zn–Sn oxide (a-In0.29Ga0.35Zn0.11Sn0.25O) thin-film transistors (TFTs). Ample H in plasma-enhanced atomic layer deposition (PEALD)-derived SiO2can diffuse into the underlying a-IGZTO film during the postdeposition annealing (PDA) process, which affects the electrical properties of the resulting TFTs due to its donor behavior in the a-IGZTO. The a-In0.29Ga0.35Zn0.11Sn0.25O TFTs at the PDA temperature of 400 °C exhibited a remarkably higher field-effect mobility (μFE) of 85.9 cm2/Vs, a subthreshold gate swing (SS) of 0.33 V/decade, a threshold voltage (VTH) of −0.49 V, and an ION/OFFratio of ∼108; these values are superior compared to those of unpassivated a-In0.29Ga0.35Zn0.11Sn0.25O TFTs (μFE= 23.3 cm2/Vs, SS = 0.36 V/decade, and VTH= −3.33 V). In addition, the passivated a-In0.29Ga0.35Zn0.11Sn0.25O TFTs had good stability against the external gate bias duration. This performance change can be attributed to the substitutional H doping into oxygen sites (HO) leading to a boost in neand μFE. In contrast, the beneficial HOeffect was barely observed for amorphous indium gallium zinc oxide (a-IGZO) TFTs, suggesting that the hydrogen-doping-enabled boosting of a-IGZTO TFTs is strongly related to the existence of Sn cations. Electronic calculations of VOand HOusing density functional theory (DFT) were performed to explain this disparity. The introduction of SnO2in a-IGZO is predicted to cause a conversion from shallow VOto deep VOdue to the lower formation energy of deep VO, which is effectively created around Sn cations. The formation of HOby H doping in the IGZTO facilitates the efficient connection of atomic states forming the conduction band more smoothly. This reduces the effective mass and enhances the carrier mobility.

We report the effects of sputter‐based multi‐stack interlayer on the electrical contact properties of a‐IGZO TFTs. The a‐IGZO TFTs with a multi‐stack interlayer of TiN and IGTO showed remarkable outcomes, including the lowest specific contact resistivity (ρC) and the highest field‐effect mobility (μFET). This research suggests a highly effective approach to reduce the contact resistivity of oxide semiconductors by nearly two orders magnitude.

The high‐performance amorphous In‐Ga‐Sn‐O (a‐IGTO) thin‐film transistors (TFTs) was fabricated with plasma‐enhanced atomic layer deposition (PEALD)‐derived Al2O3high‐k gate dielectric at a maximum processing temperature of 150 °C. During the deposition of Al2O3dielectric on a‐IGTO films, the hydrogen (H) and excess oxygen (Oi) defects from the Al2O3act significant role on TFTs operation. The amounts of H and Oican be controlled by adjusting oxygen plasma density in radio‐frequency (rf) of PEALD. The optimized a‐IGTO TFT exhibit high‐performance electrical properties with field‐effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V.

Ultraviolet to infrared broadband spectral detection capability is a technological challenge for sensing materials being developed for high-performance photodetection. In this work, we stacked 9 nm-thick tellurium oxide (TeOx) and 8 nm-thick InGaSnO (IGTO) into a heterostructure at a low temperature of 150 °C. The superior photoelectric characteristics we achieved benefit from the intrinsic optical absorption range (300–1500 nm) of the hexagonal tellurium (Te) phase in the TeOxfilm, and photoinduced electrons are driven effectively by band alignment at the TeOx/IGTO interface under illumination. A photosensor based on our optimized heterostructure exhibited a remarkable detectivity of 1.6 × 1013Jones, a responsivity of 84 A/W, and a photosensitivity of 1 × 105, along with an external quantum efficiency of 222% upon illumination by blue light (450 nm). Simultaneously, modest detection properties (responsivity: ∼31 A/W, detectivity: ∼6 × 1011Jones) for infrared irradiation at 970 nm demonstrate that this heterostructure can be employed as a broadband phototransistor. Furthermore, its low-temperature processability suggests that our proposed concept might be used to design array optoelectronic devices for wide band detection with high sensitivity, flexibility, and stability.

In this work, high-performance amorphous In0.75Ga0.23Sn0.02O (a-IGTO) transistors with an atomic layer-deposited Al2O3dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (Oi) in the Al2O3film, which was controlled by adjusting the oxygen radical density (PO2: flow rate of O2/[Ar+O2]) in the radio-frequency (rf) plasma during ALD growth of Al2O3, significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and Oiin Al2O3/IGTO stacks according to PO2were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low PO2of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high PO2condition of 20% introduced O2molecules (or Oi) into the Al2O3film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and Oiin Al2O3by controlling the PO2, we fabricated high-performance IGTO transistors with a high field-effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V, and ION/OFFratio of ∼109even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the VTHshifts for exposure to PBS and NBS for this duration were 0.1 V and −0.15 V, respectively.

Development of high‐performance p‐channel thin‐film transistors (TFTs) can be an essential building block for next‐generation display technologies which require a great power efficiency. While an n‐channel InGaZnO TFT has been practically demonstrated, the counterparts are still challenging because of their ionic bonding nature. Here we report high‐performance p‐channel hexagonal tellurium (Te) TFT which exhibits outstanding device performances with a field‐effect mobility of 21.2 cm2/Vs, a current modulation ratio of 2.3 × 105, a subthreshold swing of 0.2 V/dec, and a threshold voltage of ‐0.3 V. This study shows a strong potential of p‐channel Te TFT for next‐generation display applications.

Effects of lanthanum (La) loading on the structural, optical, and electrical properties of tin monoxide (SnO) films were examined as a p-type semiconducting layer. La loading up to 1.9 atom % caused the texturing of the tetragonal SnO phase with a preferential orientation of (101), which was accompanied by the smoother surface morphology. Simultaneously, the incorporated La cation suppressed the formation of n-type SnO2in the La-doped SnO film and widened its optical band gap. These variations allowed the 1.9 atom % La-loaded SnO film to have a high hole mobility and carrier density, compared with the La-free control SnO film. The superior semiconducting property was reflected in the p-type thin-film transistor (TFT). The control SnO TFTs exhibited the field-effect mobility (μSAT) and ION/OFFratio of 0.29 cm2V–1s–1and 5.4 × 102, respectively. Enhancement in the μSATvalue and ION/OFFratio was observed for the TFTs with the 1.9 atom % La-loaded SnO channel layer: they were improved to 1.2 cm2V–1s–1and 7.3 × 103, respectively. The reason for this superior performance was discussed on the basis of smoother morphology, suppression of disproportionation conversion from Sn2+to Sn + Sn4+, and reduced gap-state density.

This paper reports a new p-type tin oxyselenide (SnSeO), which was designed with the concept that the valence band edge from O 2p orbitals in the majority of metal oxides becomes delocalized by hybridizing Se 4p and Sn 5s orbitals. As the Se loading increased, the SnSeO film structures were transformed from tetragonal SnO to orthorhombic SnSe, which was accompanied by an increase in the amorphous phase portion and smooth morphologies. The SnSe0.56O0.44film annealed at 300 °C exhibited the highest Hall mobility (μHall), 15.0 cm2(V s)−1, and hole carrier density (nh), 1.2 × 1017cm–3. The remarkable electrical performance was explained by the low hole effective mass, which was calculated by a first principle calculation. Indeed, the fabricated field-effect transistor (FET) with a p-channel SnSe0.56O0.44film showed the high field-effect mobility of 5.9 cm2(V s)−1and an ION/OFFratio of 3 × 102. This work demonstrates that anion alloy-based hybridization provides a facile route to the realization of a high-performance p-channel FET and complementary devices.

Drain-induced barrier lowering (DIBL) is one of the most critical obstacles degrading the reliability of integrated circuits based on miniaturized transistors. Here, the effect of a crystallographic structure change in InGaO [indium gallium oxide (IGO)] thin-films on the DIBL was investigated. Preferentially oriented IGO (po-IGO) thin-film transistors (TFTs) have outstanding device performances with a field-effect mobility of 81.9 ± 1.3 cm2/(V s), a threshold voltage (VTH) of 0.07 ± 0.03 V, a subthreshold swing of 127 ± 2.0 mV/dec, and a current modulation ratio of (2.9 ± 0.2) × 1011. They also exhibit highly reliable electrical characteristics with a negligible VTHshift of +0.09 (-0.14) V under +2 (-2) MV/cm and 60 °C for 3600 s. More importantly, they reveal strong immunity to the DIBL of 17.5 ± 1.2 mV/V, while random polycrystalline In2O3(rp-In2O3) and IGO (rp-IGO) TFTs show DIBL values of 197 ± 5.3 and 46.4 ± 1.2 mV/V, respectively. This is quite interesting because the rp- and po-IGO thin-films have the same cation composition ratio (In/Ga = 8:2). Given that the lateral diffusion of oxygen vacancies from the source/drain junction to the channel region via grain boundaries can reduce the effective length (Leff) of the oxide channel, this improved immunity could be attributed to suppressed lateral diffusion by preferential growth. In practice, the po-IGO TFTs have a longer Leffthan the rp-In2O3and -IGO TFTs even with the same patterned length. The effect of the crystallographic-structure-dependent Leffvariation on the DIBL was corroborated by technological computer-aided design simulation. This work suggests that the atomic-layer-deposited po-IGO thin-film can be a promising candidate for next-generation electronic devices composed of the miniaturized oxide transistors.

Capacitor structures utilized in modern dynamic random access memory (DRAM) cells require the conformal growth of high-kfilms on electrode materials. In this context, the atomic layer deposition (ALD) of rutile-phase TiO2on nearly lattice-matched substrates such as RuO2has been extensively explored. It is typically desired to grow such insulating films at high temperatures to ensure low defect concentrations and high crystallinity. However, with increasing growth temperature, it is also crucial to consider the aggravated effect of interface reactions that could potentially hinder final device performance. Here, we report the high-temperature ALD growth of TiO2on RuO2substrates using the heteroleptic precursor trimethoxy(pentamethylcyclopentadienyl)titanium ((CpMe5)Ti(OMe)3) and O3. High-quality, rutile-phase TiO2films with large dielectric constants of ∼100 could be grown at temperatures exceeding 300 °C. When the growth temperature reaches 330 °C, we find that an anomalous RuO2reduction reaction occurs due to interactions between the substrate and Ti precursor. The reduced Ru is transformed into volatile RuO4during the subsequent O3injection steps, resulting in partial etching of the substrate. Simple RuO2/TiO2/RuO2capacitor devices fabricated from optimized films demonstrate excellent dielectric performance with an equivalent oxide thickness (EOT) of 0.5 nm at leakage current densities of less than 10–7A/cm2. A further reduction of EOT to 0.4 nm could be achieved by implementing a single cycle of Al doping to the TiO2films, surpassing the benchmark values proposed for next-generation DRAM capacitors by a safe margin. Our findings clearly showcase the benefits of high-temperature ALD in the semiconductor technology, as well as providing guidelines for the interpretation of the convoluted interface reactions tied to its implementation.

In general, the electronic and optical properties of oxide films can significantly benefit from highly textured crystallinity. However, oxide films grown by atomic layer deposition (ALD), a powerful technique for the synthesis of high-quality, nanoscale thin films, usually exhibit amorphous or randomly oriented polycrystalline phases. Here, we demonstrate the growth of highly textured rutile phase ALD TiO2films through rational substrate design. Both a- and c-axis preferentially oriented TiO2films are obtained by varying the lattice parameters of the initial ALD growth surface. Under optimized conditions, we find that it is possible to deposit high-quality, c-axis preferentially aligned TiO2films with a bulk dielectric constant approaching 185, rivaling the single crystal limit. These films display a remarkably high dielectric constant of 117 despite thin thickness of 5.2 nm. Moreover, the addition of a single doping sequence of Al2O3successfully suppresses leakage currents to levels compatible with modern dynamic random access memory cells, all the while maintaining the high bulk dielectric constant of 137. These results clearly highlight the prospect of utilizing crystal orientation engineering in ALD thin films for emerging semiconductor devices.

Development of p‐type inorganic semiconductors for high performance thin‐film transistor (TFT) can be an essential ingredient for next‐generation display applications which requires a low power consumption. However, the conventional p‐type oxide semiconductors exhibit the poor electrical characteristics, which is mainly attributed to the inefficient conduction path formation from oxygen 2p orbitals. Here, we report a new p‐type material, tin oxyselenide (SnSeO) semiconductors for high performance p‐channel TFTs. The SnSeO was designed with the concept that valence band maximum (VBM), hole conduction path, becomes delocalized by hybridizing selenium 4p and tin 5s orbitals. The SnSe0.56O0.44thin‐film exhibited the highest Hall mobility of 15.0 cm2V‐1s‐1and hole carrier density of 1.2 x 1017cm‐3. In addition, the SnSe0.56O0.44TFT showed the excellent field‐effect mobility of 5.9 cm2V‐1s‐1and current modulation ratio of 3.0 x 102. This high mobility is explained by the low hole effective mass through valence band engineering, which was confirmed by density functional theory calculation. Moreover, complementary metal oxide semiconductor (CMOS) inverter using the p‐type SnSe0.56O0.44with n‐type IGZO showed excellent intrinsic gain of 15.7. This anion hybridization can provide a facile route to the realization of a high performance p‐channel TFT for next‐generation displays.

High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10‐8A to 2.4 × 10‐9A and the enhancement of the ION/OFFfrom 2.7 × 102to 2.8 × 103compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs.