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Byline: Kapish Khajuria Sure, the buzz around DDR5 RAM is undeniable. But unless you're already equipped with a high-end system or willing to splurge on a new motherboard and CPU [...]

In-memory computing architectures present a promising solution to address the memory- and the power-wall challenges by mitigating the bottleneck between processing units and storage. Such architectures incorporate computing functionalities inside memory arrays to make better use of the large internal memory bandwidth, thereby, avoiding frequent data movements. In-DRAM computing architectures offer high throughput and energy improvements in accelerating modern data-intensive applications like machine learning etc. In this manuscript, we propose a vector addition methodology inside DRAM arrays through functional read enabled on local word-lines. The proposed primitive performs majority-based addition operations by storing data in transposed manner. Majority functions are achieved in DRAM cells by activating odd number of rows simultaneously. The proposed majority based bit-serial addition enables huge parallelism and high throughput. We validate the robustness of the proposed in-DRAM computing methodology under process variations to ascertain its reliability. Energy evaluation of the proposed scheme shows 21.7X improvement compared to normal data read operations in standard DDR3-1333 interface. Moreover, compared to state-of-the-art in-DRAM compute proposals, the proposed scheme provides one of the fastest addition mechanisms with low area overhead (< 1% of DRAM chip area). Our system evaluation running the ${k}$ -Nearest Neighbor (${k}$ NN) algorithm on the MNIST handwritten digit classification dataset shows 11.5X performance improvement compared to a conventional von-Neumann machine. [ABSTRACT FROM AUTHOR]

Samsung Electronics Co. reported that it has begun mass producing the industry's first 2nd-generation of 10-nanometer class (1y-nm), 8-gigabit (Gb) DDR4 DRAM. For use in a range of next-generation computing [...]

Micron shares dropped 7% Wednesday on the company's warning it will reduce wafer production for DRAM and NAND memory by about 20% compared to its fourth fiscal quarter of 2022. [ABSTRACT FROM AUTHOR]

Micron announced its innovative 1-beta node DRAM is now shipping to some smartphone makers and chipset partners and is ready for mass production. [ABSTRACT FROM AUTHOR]

Advanced DRAM manufacturing demands rigorous, tight process control using high measurement precision and accurate, traceable, high-throughput metrology solutions. Scatterometry is one of the advanced metrology techniques that satisfies these requirements, […], One of the major contributions to the optical critical dimensions metrology uncertainty is the variations in optical properties (n&k's) of film stack materials. It is well-known that the optical properties of materials depend heavily on process conditions, such as operating conditions of deposition tools. However, in traditional approaches, n&k values have been used as fixed inputs in a scatterometry model that might result in significant metrology error. We describe an integrated scatterometry system used in a real production environment.

EXECUTIVE OVERVIEW The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures. We posit that for a […]

While attention in the realm of computer design has shifted away from the classic DRAM soft-error rate (SER) and focused instead on SRAM and microprocessor latch sensitivities as sources of potential errors, DRAM SER nonetheless remains a challenging problem. This is true even though both cosmic ray-induced and alpha-particle-induced DRAM soft errors have been well modeled and, to a certain degree, well understood. However, the often-overlooked alignment of a DRAM hard error and a random soft error can have major reliability, availability, and serviceability (RAS) implications for systems that require an extremely long mean time between failures. The net of this effect is that what appears to be a well-behaved, single-bit soft error ends up overwhelming a seemingly state-of-the-art mitigation technique. This paper describes some of the history of DRAM soft-error discovery and the subsequent development of mitigation strategies. It then examines some architectural considerations that can exacerbate the effect of DRAM soft errors and may have system-level implications for today's standard fault-tolerance schemes.

Innodisk is launching its new anti-sulfuration DRAM modules. According to a media release, in the new Innodisk anti-sulfuration modules, an extra protective layer is added, effectively isolating the silver from [...]

Sees DRAM industry supply bit growth of ~20% and NAND industry supply bit growth of [...]

OVERVIEW A Collaborative effort between a memory manufacturer and a semiconductor tool supplier focuses on optimizing inorganic chemicals for polymer removal from DRAM device structures using single-wafer spin processors, instead […]

During its 30-plus years, the venerable dynamic RAM has undergone a series of facelifts to boost density and performance. And the nipping and tucking isn't over, with system designers demanding […]

The Blue Gene[R]/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPC[R] cores, high-performance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higher-performance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously separate technologies. Since its introduction in the 1970s, the DRAM technology has been driven by cost while the logic technology has been driven by speed, leading to an ever-widening gap between slower memory and faster logic devices. That has led to the need for increasingly complex levels of memory hierarchies, resulting in considerable degradation of system performance despite many design and architecture compromises. DRAM can provide six to eight times as much memory as SRAM (static random access memory) in the same area, but has been too slow to be used at any cache level. Our studies, highlighted in this paper, indicated that the use of logic-based DRAM could resolve that difficulty--and was necessary for integrating systems on a chip. This has led to the inclusion of logic-based eDRAM as a memory option in the IBM ASICs (application-specific integrated circuits) product.

Memory IC buyers can expect price volatility and spot shortages for DRAMs later this year because of unprecedented transitions in densities, architectures and packages. DRAM manufacturers are beginning to ship [...]

FPGAs are finding greater use as core components in systems for networking, communications, storage, and high-performance computing applications requiring complex data processing. So, it is now mandatory that FPGA vendors […]

It's easy to see why the DRAM industry has declined since the mid 1990s. The industry has always been tied to the computer industry. When PC sales were growing 20% [...]

DRAM SUPPLIERS MIGHT DESIRE A ONE-SIZE-FITS-ALL FUTURE, but divergent application needs don't comply. DRAM users might prefer a custom chip, but its cost would be excessive. Can each side secure [...]

CEO Geoff Tate had a problem. Customers were unhappy. The stock was sagging. PR was awful. And, to add insult to injury, even some Wall Street analysts stopped paying attention. […]

OVERVIEW Issues associated with the integration of CVD low-k dielectrics for 100nm technology node applications are described, including key film properties and factors determining successful integration into advanced DRAM and […]

Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 \mu\ m^2 per fuse set by using a 5 \mu\ m diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%. [ABSTRACT FROM PUBLISHER]

MEMORY PRICES ARE AT AN ALL-TIME LOW, and enormous half-gigabit DRAMs, multigigabit flash memories and multimegabit SRAMs are rolling off suppliers' assembly lines. Those same memories are reading and writing [...]

In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits. [ABSTRACT FROM PUBLISHER]

SMART Modular Technologies reported sample availability of its 32GB DDR4 NVDIMM-N, making it the highest density DDR4 NVDIMM-N module available in the industry. The company said SMART will begin sampling [...]

Designing your own synchronous-DRAM controller lets you tune its cost, complexity, and performance to your application needs. You've got lots of options, so research the trade-offs before proceeding. Today's graphics [...]

Keys to coping with pricing competition and industry consolidation include technology, test equipment, and capital. With annual sales of more than $100 million, offices on three continents, and a loyal […]

DRAM manufacturers are exceeding past speed limits as memory architectures and product mix grow increasingly complex. Fast-page-mode (FPM) and EDO DRAMs are fairly simple and evolutionary. From there, it gets […]

Designers Detail Advanced Process Techniques And Finer-Dimension Design Rules At IEDM To Build Next-Generation Memories And Logic. Advances in cell structures for 1-and 4-Gbit DRAMs, 1-Gbit flash memories, and process […]

Novel Architectures For Next-Generation DRAMs Are Pushing Data-Transfer Rates Beyond 500 MHz While Offering New Features And Control Options. Today's computer systems and graphics subsystems are pushing standard DRAM architectures […]

Though DRAM buyers and sellers never had it easy, future architectures will test their strength and market savvy. The DRAM buyer's and seller's financial goals - to make money and […]

Despite finer process geometries, expanding transistor budgets, and broader function libraries, one vital element has remained largely absent from the industry's march toward system-on-a-chip - DRAM. With the development of […]

Dynamic random access memory (DRAM) bit density has increased nearly fourfold every three years, from 4 kbit in 1972 to 64 Mbit now. Each successive generation has maintained the same […]

Engineers are more familiar with conventional DRAMs than they are with SDRAMs, and using SDRAMs requires expertise that only few EEs posses. Still, SDRAM-controller designs need not be especially difficult; [...]

The future of Intel-based computing depends on how well--and how fast--PC memory schemes can keep up with processor designs. Computer memory has advanced with each microprocessor generation, becoming bigger, faster, […]

Personal computers, workstations, communication systems, and graphic subsystems have seen rapid growth in the demand for larger and faster memories. These systems use memories to write, store, and retrieve large […]

New York - Memory chip makers who think they can see a light at the end of the tunnel still have to watch out for on-coming trains, analysts warn. Memory, […]

Digital Advances Lead To Single-Chip MPEG-2 Encoders, 600-MHz RISC CP Us, and 4-Gbit DRAMs. High-performance processors and large memory chips have typically been the highlight of the digital portion of […]

Still digesting the implications of a shift from extended data out (EDO) DRAMs to synchronous DRAMs (SDRAMs), PC designers were warned last December not to grow too accustomed to their […]

To get high performance from high-speed systems, you need high-performance memories. Carefully analyze the EDO, SDRAM, and RDRAM system-timing parameters to see which memory type delivers the performance that your [...]

World's biggest chipmaker saw a record in bit shipments for memory in the quarter [ABSTRACT FROM AUTHOR]

The company is prepared to expand amid long-term growth expectations and short-term over-supply predictions. [ABSTRACT FROM AUTHOR]

Prices are going down, down, down-and your chances of finding a bargain on great new hardware are going up, up, up. Did you pay too much for your last computer? […]