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Moog Muse is a new flagship polysynth from Moog that offers a more affordable option compared to its predecessor, the Moog One. With eight analogue voices, a multi-timbral design, and a flexible approach to modulation, Muse maintains many of the features of the Moog One while dialing back on the all-bells-and-whistles approach. It has a slightly different visual style and offers a solid build with sturdy controls. Muse's sound engine includes three voltage-controlled oscillators, two resonant ladder filters, and a diffusion delay effect. While it may not be the most versatile synth in its price range, Muse delivers a characterful and rich sound that captures the essence of a Moog poly. [Extracted from the article]

This article from Computer Music magazine discusses the use of sequencers in synthesizer patches, specifically focusing on the BazilleCM synth plugin. The author explains how to create a sequencer polysynth patch using BazilleCM, providing step-by-step instructions for adjusting various settings and parameters. The article also touches on the debate surrounding the inclusion of onboard effects in synthesizer patches and offers recommendations for further listening. The author, Roland Schmidt, is an experienced programmer, sound designer, and producer who has worked in the music industry for 25 years. [Extracted from the article]

This document is a gear guide from the journal "Future Music" that provides reviews of various music equipment. It includes reviews of synthesizers such as the Oberheim TEO-5, Moog Muse, Groove Synthesis 3rd Wave, UDO Super Gemini, Waldorf Iridium Core, Sequential Take 5, Arturia PolyBrute 12, ASM Hydrasynth Deluxe, Arturia MiniFreak, and Korg Modwave. It also reviews digital audio workstations (DAWs) like Ableton Live, Reason Studios Reason, Bitwig Studio, Logic Pro, Image-Line FL Studio, Steinberg Cubase, Tracktion Waveform Pro, Universal Audio Luna, Avid Pro Tools, and Presonus Studio One. Additionally, it provides reviews of semi-modular synths including the Moog Labyrinth, Moog Spectravox, Intellijel Cascadia, Korg Volca Modular, Moog Mavis, Arturia MiniBrute 2S, Bastl Softpop SPII, Moog Matriarch, Behringer Neutron, and PWM Malevolent. [Extracted from the article]

The article discusses the features and capabilities of the UltraSpace multi-effect plugin from Tone2. The plugin offers various spatial effects, including reverb, delay, and dynamics. It comes with over 150 presets and allows for creative customization. The article provides step-by-step instructions on how to install and use the plugin, as well as tips on utilizing its reverb, multitap delay, and combination effects. The plugin also includes gating options and can be used to create unique and interesting sound effects. [Extracted from the article]

This paper addresses the problem of achieving consensus in leader-following multi-agent systems under event-triggered control, with considerations of model uncertainties, network time-delay, and random deception attacks. To address the challenges of limited network resources, we propose a novel event-triggered control scheme that employs a dynamic memory-based approach. The proposed scheme utilizes multiple historic event-triggered states that are correlated with the states of neighboring agents and the leader, and the threshold parameter varies dynamically with time. We establish a memory-based closed-loop system that considers both network delays and deception attacks. Using the Lyapunov stability theory, a sufficient condition is derived to ensure consensus performance, and the desired controller gains and triggered matrices are obtained by solving linear matrix inequalities. Besides, we provide a comparative analysis of the memoryless dynamic event-triggered control. Finally, we validate the effectiveness of proposed approach with simulation results. [ABSTRACT FROM AUTHOR]

Kings of Leon is a band formed by three brothers and a cousin from the Followill family. They started in Nashville, Tennessee, and gained success in the UK before achieving mainstream success worldwide. Influenced by Southern rock, blues, and classic bands like Thin Lizzy and The Rolling Stones, their music blends rock with a garage punk vibe. The band has won two Grammys and has a strong family bond, which has helped them avoid the tensions and tantrums often associated with success. Their guitar parts often complement each other, and their songs are built around the G Major scale. They use AC30 type amps for a rock tone and employ double-stop chords and open-string harmonies. Their debut album, "Youth and Young Manhood," and their successful album, "Only By The Night," feature popular tracks like "Sex On Fire" and "Use Somebody." [Extracted from the article]

The article discusses the Epiphone Inspired By Gibson Custom Jimi Hendrix 'Love Drops' Flying V guitar. The guitar is based on Jimi Hendrix's custom Gibson Flying V, which he used later in his life. The Epiphone version is part of the Inspired By Gibson Custom range and features a recreation of Hendrix's original artwork. It also includes premium electronics, such as Gibson USA pickups, CTS pots, and a Mallory capacitor. The guitar comes with a hardshell case and is available in both right- and left-handed models. [Extracted from the article]

This article discusses six portable practice solutions for guitarists who are away from home but still want to practice. The solutions include the VOX AMPLUG3 AC30, BLACKSTAR FLY 3, BOSS KATANA-MINI, FENDER MUSTANG MICRO, POSITIVE GRID SPARK GO, and LINE 6 POD EXPRESS. Each solution offers different features such as amp models, effects, headphone operation, and connectivity options. Prices range from £47 to £199. [Extracted from the article]

In this paper, the secure synchronization control problem of a class of complex time-delay dynamic networks (CTDDNs) under denial of service (DoS) attacks is studied. Based on the pinning control strategy, a non-fragile sampling controller is designed for a small number of nodes in the complex network. It can effectively solve the problem of limited communication resources and has good anti-interference performance. In order to resist the influence of DoS attacks, an improved comparator algorithm is designed to obtain the specific information of DoS attacks, including the upper and lower bounds of the DoS attacks duration, the DoS attacks frequency and the specific active/sleeping interval of DoS attacks. Based on Lyapunov stability theory and by designing the pinning non-fragile sampling controller, new security synchronization criteria are established for CTDDNs. Finally, two numerical examples are given to verify the validity of the theories. [ABSTRACT FROM AUTHOR]

Boss has released the third generation of their Katana amps, which were first launched eight years ago. The new lineup includes seven models, ranging from combos to heads, with features and tonal improvements across the board. Each model is equipped with six amp models and offers over 60 individual effects through the Boss Tone Studio app. The range also includes the flagship Katana Artist models, which offer an enhanced experience with custom speakers and additional control options. Prices start at £293 for the entry-level model and go up to £691 for the Katana Artist combo. [Extracted from the article]

The article discusses recent installations of sound systems in various clubs around the world. The Other Side in Amsterdam is the first nightclub to adopt L-Acoustics' L-ISA spatial audio system, providing a fully immersive auditory experience for patrons. Potato Head Beach Club in Bali has chosen 1 Sound speakers for its indoor and outdoor areas, while Barstool Nashville in Tennessee features a state-of-the-art system from DAS Audio. Mantra Club in Jakarta has installed a KV2 sound system, and Tenax in Florence has upgraded its system with K-array speakers. These installations aim to enhance the clubbing experience and provide high-quality sound for both DJs and live performances. [Extracted from the article]

This study introduces a fault compensation control approach for a class of affine nonlinear time-delay systems using adaptive dynamic programming (ADP). By establishing an observer, the ADP-derived approach facilitates the estimation of potential actuator faults within the system. A novel value function is devised to incorporate the estimated fault and state delay. Subsequently, the control laws are derived from this innovative value function. The Hamilton–Jacobi–Bellman equation associated with this innovative value function is effectively solved using a critic neural network. Then, it is demonstrated through Lyapunov theory that the closed-loop systems achieve uniform ultimate boundedness. The efficacy of the current fault compensation strategy is validated through simulation instances. A notable contribution of the proposed method is its extension of the ADP technique to address the challenge of fault compensation in nonlinear time-delay systems. • A fault compensation control approach for nonlinear time-delay systems using adaptive dynamic programming (ADP). • The ADP-derived approach facilitates the estimation of potential actuator faults within the system. • The Hamilton–Jacobi–Bellman equation associated with this innovative value function is effectively solved using a critic neural network. [ABSTRACT FROM AUTHOR]

Researchers at the University of Texas MD Anderson Cancer Center have conducted a study on reducing blood culture contamination in adult cancer patients presenting to the Emergency Department (ED). Contamination of blood cultures can lead to misdiagnosis, unnecessary antibiotic exposure, and increased financial burdens. The study found that a standardized blood culture collection process followed by ED nurses, along with the use of chlorhexidine swabs, can significantly reduce contamination rates. Implementing readily available premade blood culture kits also improves compliance with best practices. [Extracted from the article]

A recent study conducted by researchers at the University of the South Toulon-Var in France explored the effects of a visual dynamic device on motion sickness. The device, which consists of vertical light-emitting diodes, was tested on fifteen individuals with moderate to severe motion sickness susceptibility. The study found that the device delayed symptom onset and increased the time spent in a motion sickness simulator. However, further research is needed to evaluate its effects during prolonged exposure to motion sickness-inducing stimuli. This research was supported by the French Ministere de l'Enseignement Superieur, de la Rechercher et de l'Innovation and has been peer-reviewed. [Extracted from the article]

The launch of the Northumberland line between Newcastle and Ashington has been delayed until December due to weather-related construction impacts. The delay is being addressed by all partners involved in the project, with the hope of opening the line earlier than the new date. The line will initially open with three stations, with the remaining three to follow in 2025. The anticipated final cost of the project is £298.5 million, with an expected return of £1.50 for every £1 invested. [Extracted from the article]

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations. [ABSTRACT FROM AUTHOR]

The EPTL notes lack of preventive maintenance activities for Thar block 2 transmission lines despite multiple tripping events last year and this year. Ms/Engro Powergen Thar Limited (EPTL) has expressed its concern over the delay in construction of dedicated transmission line for SECL (Thar Block-1) and lack of preventive maintenance at Block-2. [Extracted from the article]

This paper introduces a new true random number generator (TRNG) based on a three-edge ring oscillator. Our design uses a new technique with a time-to-digital converter to effectively acquire jitter accumulated independently by each edge. As a part of the security evaluation, we present the stochastic model of the TRNG’s digital noise source and estimate a lower bound of the min-entropy per random bit. Starting from the obtained entropy bound, we propose a procedure for selecting and implementing an area-efficient and throughput-optimal post-processing function based on the best known linear codes that will increase the output min-entropy rate to more than 0.999. The proposed TRNG exquisitely balances low design effort and resource consumption with high throughput and a high min-entropy rate, making it more suitable for randomness-demanding and resource-constrained platforms than the state-of-the-art. The complete implementation of the TRNG digital noise source and the post-processing occupies 33 slices and achieves a throughput of 12.5 Mbps on Xilinx Zynq-7000 FPGAs. The min-entropy of the generated random bits is assessed by NIST SP 800-90B entropy estimators, and the tested sequences pass the AIS-31 test suit. [ABSTRACT FROM AUTHOR]

The article focuses on a study comparing ventilator circuits to delay ventilator-associated pneumonia (VAP) in neurological patients. Topics include the effectiveness of conventional versus closed-loop ventilatory circuits, the timing of VAP onset, and the impact on patient outcomes such as duration of mechanical ventilation and hospital stay.

Singapore Airlines is offering $10,000 in compensation to passengers who sustained minor injuries during a flight that experienced extreme turbulence. The airline is also providing advance payments of $25,000 to those with more serious injuries. The incident occurred when the Boeing 777 jet encountered turbulence near Myanmar, causing a 180-foot drop and resulting in severe injuries to several dozen passengers. The airline has apologized for the traumatic experience and is offering refunds, additional payouts, and covering initial expenses for all passengers. [Extracted from the article]

Ship-radiated noise recognition remains a challenging issue in underwater acoustic signal processing for a variety of reasons. The ocean ambient noise influences the signal quality, and the scarcity of samples limits the performance of deep learning algorithms. In this study, a self-attention mechanism and residual block-based time-delay neural network (SRTDNN) is proposed to improve the recognition performance of ship-radiated noise. The noise samples are first segmented and transformed into three-dimensional Mel-scale frequency cepstral coefficients (3D-MFCC), which combine static and dynamic characteristics of targets through the concatenation of MFCC, Delta MFCC and Delta-Delta MFCC. Subsequently, 3D-MFCC are fed as input to the SRTDNN. The SRTDNN extracts time-domain features of inputs through the TDNN layers and then assigns different weights to the frame and channel dimensions of the feature maps through two attention mechanisms. The Res Connections and Res2Block are interspersed to facilitate convergence. During training, a time-domain and frequency-domain data augmentation pipeline is designed to alleviate the lack of samples. Experiments with public and real sea experiment datasets are conducted to compare the SRTDNN with acknowledged high-quality recognition methods. The results show that the SRTDNN has a significant improvement in recognition performance. Furthermore, the ablation tests demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10−12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

The article discusses the Boss Delay Machine DM-101, a hybrid delay pedal that combines analog BBDs with digital control. The pedal offers 12 different styles of delay, including classic BBD-style delay, multi-head mode, and various two-channel effects. It has a stereo output and can be used with both guitars and synthesizers. The DM-101 is highly recommended for guitarists and is also well-suited for studio use. It offers MIDI, USB, and stereo outputs, but it is not cheap. Overall, it is considered one of the best delay pedals on the market. [Extracted from the article]

Delay is a widely used effect in music production, synthesizers, and guitars. It works by storing an incoming signal in its buffer and then playing back a repeat of that stored signal after a set interval. Delay devices can be used to create various effects, from thickening vocals to echoey synth lines. They differ from reverb effects, which replicate acoustic reflections, by storing the input signal in a buffer and repeating it after a specific time. Delay can be used in mono or stereo, and there are options to adjust the timing of the repeats and pan them for a bouncing effect. The dry/wet mix control is used to balance the original sound with the delayed signal. Delay devices often have filters and EQ controls to shape the tone of the delayed signal, and some offer saturation stages and different delay algorithms to emulate iconic hardware units. [Extracted from the article]

NUSofting has released a new effects plugin called Sosir Freeze-Delay, which is available for free. This plugin can transform plucked, staccato sounds into sustained, bowed sounds by freezing and delaying the input signal. It can be used with various input signals, such as guitars, synths, vocals, or samples, to create ambient soundscapes. The plugin features two stages of sound processing, a virtual bow, delay line with feedback and modulation, gain knobs, a reverb option, and controls for changing the base timbre, applying filtering, adjusting delay time and feedback, and controlling the LFO. The developer of Sosir took inspiration from a preset on Strymon's BigSky reverb pedal. The plugin is available for download in VST3/AU formats from nusofting.com. [Extracted from the article]

For nonlinear time-delay systems with uncertainties, the existing approaches to robust model predictive control (MPC) are based on the min–max optimization formulation. Unfortunately, these approaches are generally conservative for most practical problems. For this sake, this article proposes a tube-based MPC consisting of MPC and control contraction metric (CCM) controller. The MPC is utilized as a nominal controller to generate a reference trajectory, while the CCM controller is used as a local ancillary controller to guarantee the actual trajectory to be contained within a robust invariant tube centered along the reference trajectory. Besides, we construct a variational formulation multidimensional Taylor network (MTN) as the basis function to search for the minimal geodesic. With the effective training algorithm, MTN could efficiently approximate the solution with high accuracy. The incremental exponential stability of the considered systems is proved theoretically, and the effectiveness of the proposed method is illustrated by numerical simulation. [ABSTRACT FROM AUTHOR]

This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of $2.9\mu \text{s}$ and $4.2\mu \text{s}$ for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation. [ABSTRACT FROM AUTHOR]

The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only $4\times $ redundancy. [ABSTRACT FROM AUTHOR]

In the literature, the effects of switching with average dwell time (ADT), Markovian switching, and intermittent coupling on stability and synchronization of dynamic systems have been extensively investigated. However, all of them are considered separately because it seems that the three kinds of switching are different from each other. This article proposes a new concept to unify these switchings and considers global exponential synchronization almost surely (GES a.s.) in an array of neural networks (NNs) with mixed delays (including time-varying delay and unbounded distributed delay), switching topology, and stochastic perturbations. A general switching mechanism with transition probability (TP) and mode-dependent ADT (MDADT) (i.e., TP-based MDADT switching in this article) is introduced. By designing a multiple Lyapunov–Krasovskii functional and developing a set of new analytical techniques, sufficient conditions are obtained to ensure that the coupled NNs with the general switching topology achieve GES a.s., even in the case that there are both synchronizing and nonsynchronizing modes. Our results have removed the restrictive condition that the increment coefficients of the multiple Lyapunov–Krasovskii functional at switching instants are larger than one. As applications, the coupled NNs with Markovian switching topology and intermittent coupling are employed. Numerical examples are provided to demonstrate the effectiveness and the merits of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this article, the finite-time $H_\infty $ state estimation problem is addressed for a class of discrete-time neural networks with semi-Markovian jump parameters and time-varying delays. The focus is mainly on the design of a state estimator such that the constructed error system is stochastically finite-time bounded with a prescribed $H_\infty $ performance level via finite-time Lyapunov stability theory. By constructing a delay-product-type Lyapunov functional, in which the information of time-varying delays and characteristics of activation functions are fully taken into account, and using the Jensen summation inequality, the free weighting matrix approach, and the extended reciprocally convex matrix inequality, some sufficient conditions are established in terms of linear matrix inequalities to ensure the existence of the state estimator. Finally, numerical examples with simulation results are provided to illustrate the effectiveness of our proposed results. [ABSTRACT FROM AUTHOR]

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard $0.18~\mu \text{m}$ CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than $16~\mu \text{s}$. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage. [ABSTRACT FROM AUTHOR]

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode. [ABSTRACT FROM AUTHOR]

An M-ary Differential Chaos Shift Keying modulation using Chaotic Shape-forming Filter (CSF-M-DCSK) is proposed here to transmit two sub-streams with different system performances. The chaotic shape-forming filter is used to generate the chaotic carrier which is modulated according to the DCSK concept. The modulated chaotic signal is demodulated by a coherent matched filter receiver and the maximum likelihood decision rule is used to get the best noise performance. Compared to DCSK and its enhanced versions, the new modulation scheme offers not only better noise and multipath performances but also a higher data rate. The hardware implementation of the proposed method is as simple as that of a conventional communication system. Analytical expressions have been derived for the CSF-M-DCSK Bit Error Rate (BER) and its performance has been evaluated in AWGN and multipath channels by simulations. The new CSF-M-DCSK system has been implemented and successfully tested on a Wireless open-Access Research Platform (WARP). Results of simulations and measurements performed in real application scenarios have proven the feasibility and superiority of CSF-M-DCSK over its competitors. [ABSTRACT FROM AUTHOR]

This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify the operation polarity of the two-step digital-slope conversion. Besides, the two-step digital-slope conversion shares the unary DAC with different weights, which not only mitigates the resolution issues of the digital-slope quantizer but also converts the residue without requiring gain-error calibration. The two-step digital-slope ADC can be divided into three conversion steps and provide 1-bit, 5.7-bit, and 4-bit resolution for each conversion cycle. The digital-offset correction then encodes the three sets of outputs and subtracts the digital-offset caused by the feedback-process latency of the quantizers. The proposed two-step digital-slope ADC is manufactured using 1P9M 65-nm CMOS technology, and the active area of the prototype is 0.0946 square millimeter. At the Nyquist frequency, the SNDR and SFDR measured at 1.2 V, and 300 MS/s are 60.72 dB and 70.05 dB, respectively. With the power consumption of 6.2mW, the corresponding Walden FoM is 23.3 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2MS/s SAR ADC is designed using 130nm CMOS process with 0.5V power supply voltage. Measured results show that the ADC can work normally from 0.5V to 1V supply voltage, with the sampling rate increasing from 2MS/s to 32MS/s. The ADC achieves an SNDR (signal-to-noise distortion ratio) of 56.7dB, corresponding to an ENOB (effective number of bits) of 9.13 bits and consumes $3.4\mu \text{W}$ , resulting in a figure of merit (FoM) of 3.03 fJ/c.-s at 0.5V supply voltage and 2MS/s sampling rate. [ABSTRACT FROM AUTHOR]

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation are investigated. The digitally controlled shunt-capacitor inverter (SCI) delay cell leads to an extremely small design with the delay line being the only analog component, while the voltage controlled current-starved inverter (CSI) delay cell has a lower power consumption and less jitter. The proposed design procedure of the SCI based DLL allows fast simulation using Verilog based models since no analog low pass filter is required. Using the proposed modeling technique for the PDC, the behavior of the DLL can be estimated based on input clock jitter specifications. The SCI and CSI based multiphase DLL designs are fabricated in a 65nm CMOS process operated from a 1.2V supply. The proposed SCI based DLL occupies only 0.0048mm2 of active area and consumes 2.25mW at 2.5GHz input frequency with a 622.6MHz sample clock. The RMS jitter of the circuit is 1.2 ps and 1.4 ps for the DLL loop and the phase shifter loop, respectively. The RMS jitter is significantly reduced with the CSI based DLL to 0.86 ps and the power consumption of 2.64mW at 4GHz input frequency with a 996.1MHz sample clock provides an improved power efficiency compared to the SCI based DLL. As a trade-off, the area is increased to 0.0085mm2 due to the use of a $\Delta \Sigma $ modulator and an analog low pass filter. [ABSTRACT FROM AUTHOR]

The agents’ deployment over a line segment under protocols with communication delays and switching is studied. It is assumed that no information about the value of the communication delay and no information about switching policy in the communication graph is available. It is shown that neither delay values nor switching policy in a natural class may influence convergence of the agent states to the equidistant distribution over the line segment. Similar result is obtained for deployment over the circle. The theoretical results are illustrated by simulations. The proofs relay on both well-known and recent approaches to the stability analysis of positive systems. [ABSTRACT FROM AUTHOR]

A recent study conducted by researchers at Southern Federal University in Rostov Na Donu, Russia, has explored the synthesis conditions for Nbf-modified 8,13-dihydroberberine derivatives. Berberine, a natural alkaloid, has a wide range of biological activity, and its derivatives show promise for pharmacological applications. The researchers developed a microfluidic flow system using a 3D printed chip, which allowed them to synthesize hybrid berberine derivatives with an NBF fragment at the C-13 position. This approach resulted in up to a 30% increase in product yields compared to traditional batch synthesis, and the substances exhibited high antioxidant activity without toxic effects on cell cultures. The study suggests that the microfluidic approach coupled with UV-Vis diagnostics is a promising tool for optimizing and screening synthesis conditions of challenging alkaloid derivatives. [Extracted from the article]

Linear, or almost linear phase in the design of digital differentiators depends both on the method of calculation of the filter coefficients and the adopted structural design. Acknowledging the importance of this design objective, we developed a method to derive infinite impulse response differentiators which tackles it from both perspectives and yields improved characteristics compared to our previous design. We have replaced the differentiator structure comprising an all-pass filter and a delay line with a configuration of two infinite impulse response all-pass filters. Furthermore, we provide a procedure for determining an improved initial solution to the optimization of filter coefficients, as well as a procedure for improving the differentiator's magnitude response. The final solution exhibits considerably lower error at low frequencies and is thus suitable for the common scenario where the relevant spectral content decreases with frequency. The proposed filters of third and fifth order outperform many existing solutions in literature, especially in terms of the phase characteristic and time-domain performance. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the $1^{st}$ and $2^{nd}$ Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system’s step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 pspp at 10 Gb/s under a PRBS $2^{31}-1$ pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after −20-dB channel loss. The die area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

A new, all-digital on-chip peak-to-peak (p-p) jitter measurement circuit (OCJM) that features automatic resolution calibration for high PVT-variation resilience without a reference clock and off-line calibration is presented in this paper. The OCJM uses a front-end self-referenced circuit (SRC) to eliminate the jitter-free reference signal and a back-end p-p jitter detector (PPD) to perform p-p jitter measurements. The key design of the proposed OCJM is that the SRC and the PPD share a Vernier delay line (VDL) so that the run-time PVT information automatically extracted from the SRC operation can be carried onto the PPD to achieve automatic on-line resolution calibration. Besides this feature, the OCJM uses on-chip direct p-p jitter measurement with only 1-time readouts to eliminate the huge power consumption of the off-chip data communication while avoiding data loss of a possible large jitter caused by PVT variations during off-chip data communication. These techniques make the proposed OCJM suitable for any-time, any-site jitter measurements for SoC applications. The proposed OCJM is fabricated in a 28-nm CMOS. The measurement results show that the timing resolution and minimum measurable jitter range specifications are met under extreme PVT conditions while achieving 98% clock cycle and energy reduction compared to the conventional OCJM designs. [ABSTRACT FROM AUTHOR]

We consider a digital encoding/processing system in which both the analog-to-digital converter and the digital signal processor are implemented by repeating a single fundamental design unit: the digital delay. Timing becomes an integral part of the resulting signal representation and processing, thereby promising to improve with technology scaling. System properties are studied and design considerations for a potential integrated implementation are discussed. Simulation results confirm the theory. [ABSTRACT FROM AUTHOR]

Two improved structures of high resolution digital pulse width modulator (DPWM) control circuit are proposed. Embedded digital clock manager (DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array (FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides, the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability. [ABSTRACT FROM AUTHOR]

Features Nebula, a serial digital computer created under the sponsorship of Oregon State University Departments of mathematics and Engineering. Application of a glass delay line memory; Presence of command structure similar to large parallel machines; Capabilities of the machine.