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In this paper, SiC MOSFETs capacitance is monitored when a DC bias is applied between Drain and Source. The arising capacitance exhibits a sharp peak in the inversion region which is related to the SiC/SiO2 interface traps properties. Temperature effects on such peak are investigated using both experimental and numerical results. The peak shifts toward lower Gate voltage as temperature increases, in agreement with the threshold voltage reduction at higher temperature.

This paper presents the design of a high-efficiency high power-density traction chain, based on an original high-speed machine concept powered by an innovative power converter, featuring built-in voltage boosting. The input power source is a 60 V battery. The inverter is designed with hybrid semiconductor technology: silicon on the input (low-voltage) side and silicon carbide on the output (higher-voltage) side. The switching frequency of the primary and secondary side switches can be set independently for best efficiency and electro-magnetic signature. The paper includes the detailed design of magnetic components enabling dual switching frequency operation and reduction of current stress in semiconductors and capacitors by means of interleaved cross-coupled inductance power cells. Preliminary prototype development and experimental test results are also discussed.

Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the SiO2/SiC interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the SiO2/SiC interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the SiO2/SiC interface.

Thanks to the increasing availability of silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) with outstanding static and dynamic performances, the number of applications in which these devices are used is rapidly growing. Despite that, the maximum current rating of such devices is usually limited at few hundred amps, which sets an upper bound for the power level at which these transistors can be adopted. A viable solution to this problem consists in paralleling several SiC MOSFETs. However, the design of parallel configurations needs optimization since mismatched performances can cause the enhanced stress of a subset of devices, which can ultimately lead to premature failure of the whole module. In this contribution, several sets of Monte Carlo (MC) electrothermal simulations of parallel SiC MOSFETs are used to systematically relate the deviations of devices and circuit parameters to the resulting uneven power dissipation. To this purpose, a set of relevant parameters is identified and statistically described. Thereafter, the simulation of a 200-kHz synchronous buck converter relying on mismatched parallel MOSFETs is performed as a case study. Eventually, a methodology to derive a guideline for the design of reliable multichip configurations is developed. The methodology is based on the iteration of MC simulations for different tolerances of the parameters.

VTH instabilities of SiC MOSFET are made of a permanent and a recoverable part. VTH hysteresis is a recoverable instability which affects the operation of the device since the threshold voltage depends on the negative bias applied previously. In this paper, the phenomenon is assessed through experiments and TCAD simulation. The results are in good agreement and show that the VTH hysteresis is mainly caused by the hole trapping in the oxide near the interface. The C(V) characteristics of the measured device is similar to the simulated device having a concentration of 1012 holes/cm2 trapped at the interface.

Despite their growing adoption in a variety of applications, SiC MOSFETs are generally not available at high current rating. Therefore, there is a high demand for power modules exploiting configurations based on parallel devices. However, these products still need optimization in order to ensure long-term reliability. This paper presents a methodology relying on fast electrothermal simulations aimed at aiding this optimization procedure. The proposed approach is applied to a power module in which the parallel MOSFETs are realistically subject to mismatched parameters.

This paper presents a preliminary study of the impact of device electro-thermal parameter spread and temperature variation on the robustness of SiC MOSFET parallel multi-chip power switch architectures. Reference is made to 1200 V – 80 mΩ rated commercial devices. Some major parameters are identified and selected, presenting experimental evidence of their impact during transient overload events. An advanced physics-based simulation model is then employed to extend the analysis to a more comprehensive set of parameters and operational conditions.

In this paper, thermal loading of the state-of-the-art gallium nitride (GaN) High-electron-mobility transistors (HEMTs) and traditional Si Insulated-gate bipolar transistors (IGBTs) in three-level active neutral-point-clamped photovoltaic inverters is presented considering real-field long-term mission profiles (i.e., ambient temperature and solar irradiance). A comparison of Si IGBT against GaN HEMT with three different possibilities: 1) with thermal interface material (TIM) at 10 kHz; 2) without TIM at 10 kHz; and 3) with TIM at 300 kHz has been performed. The assessment results indicate lower thermal stress with GaN HEMT devices at 10 kHz in comparison with Si IGBT. At high switching frequencies, the results show that the significant system level cost savings can be achieved without compromise of operating efficiency with GaN HEMTs. Both simulations and experimental tests are provided to demonstrate the thermal loading analysis approach. More important, the proposed analysis and comparison approach can be used for lifetime and reliability analysis of wide bandgap devices.

The behavior of silicon carbide (SiC) power MOSFETs under stressful short-circuit (SC) conditions is investigated in this paper. Two different SC failure phenomena for SiC power MOSFETs are thoroughly reported. Experimental evidence and TCAD electrothermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations and are reported along with their effects on devices’ SC capability.