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The eMeet SmartCam C960 2K is a popular 1440p webcam with good value. Strengths include good noise cancelling and decent imagery. There are a few drawbacks, but no dealbreakers. [ABSTRACT FROM AUTHOR]

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Copyright of KI - Kälte Luft Klimatechnik is the property of Hüthig GmbH and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper aims to introduce a technique that utilizes both dynamical mechanisms and machine learning to reduce dimensionality in high-dimensional complex systems. Specifically, the method employs Hopf bifurcation theory to establish a model paradigm and use machine learning to train location parameters. The effectiveness of the proposed method is evaluated by testing the Van Der Pol equation and it is found that it possesses good predictive ability. In addition, simulation experiments are conducted using a hunting motion model, which is a well-known practice in high-speed rail, demonstrating positive results. To ensure the robustness of the proposed method, we tested it on noisy data. We introduced simulated Gaussian noise into the original dataset at different signal-to-noise ratios (SNRs) of 10 db, 20 db, 30 db, and 40 db. All data and codes used in this paper have been uploaded to GitHub. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

In this paper, a design methodology for SiGe HBT-based low-noise amplifiers (LNAs) is proposed that can be utilized for both sub-1-dB noise figure (NF) and wide bandwidth as an alternative to the conventional simultaneous input noise and power matching technique. This paper focuses on the removal of the series base inductor and the inclusion of an output matching network as a design parameter that can be used to achieve both sub-1dB NF and wide bandwidth. The effects of the mentioned design parameters on NF and bandwidth are described and analyzed, including the comparison of results with the conventional design technique. To demonstrate the validity of the analysis and impact of utilizing base-to-collector capacitance on LNA performance metrics, two different LNAs implemented in a 0.13- $\mu \text{m}$ SiGe technology. The first LNA achieves a lower than 1-dB NF with 26-dB gain at 8.5 GHz, and the second LNA exhibits wideband operation, with a better than 10-dB return losses in the range of 8–35 GHz and lower than 3-dB NF from 6 to 20 GHz. The sub-1-dB LNA reaches −17.3 dBm of input-referred compression point (IP1dB), with a power consumption of 62 mW and an area of 0.795 mm2. The wideband LNA achieves 17.6 dB of peak gain with a 48.5-mW power consumption and 0.69-mm2 chip area. To the best of our knowledge, this paper achieves the best NF performance in the literature utilizing a SiGe technology, while the wideband LNA exhibits the best operational bandwidth, together with a reasonable low-noise performance. [ABSTRACT FROM AUTHOR]

Phase locked loops for fractional frequency synthesis typically use Digital $\Delta \Sigma $ Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional- ${N}$ frequency synthesizers with polynomial nonlinearities. [ABSTRACT FROM AUTHOR]

To solve the ship course control problem with nonlinear terms, input saturation, and complex noise, this paper proposes a saturated ship course control method with complex noise based on generalized fuzzy hyperbolic model (GFHM). Due to the characteristics of fewer identification parameters, GFHM can simplify the complexity of traditional ship fuzzy models. GFHM is more suitable for multi-variable nonlinear systems such as ships of which variables are limited and difficult to measure. Furthermore, to deal with the input rudder angle saturation problem caused by the limited capability to compensate the shipboard equipment controller, an auxiliary system is proposed. And the complex noise in the navigation environment is described by the random process. Then, a new type of ship fuzzy course controller is designed based on the theoretical framework of random differential equations (RDEs) and it is proved that the ship course system under the proposed GFHM-based controller is noise-to-state stable in probability (NSS-P) and the state is an asymptotic gain in probability (AG-P). The simulation results show that the proposed algorithm in this paper can effectively control the ship's course. [ABSTRACT FROM AUTHOR]

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove that the fundamental noise invariants under input and output impedance transformations are the eigenvalues of a permuted version of the noise correlation matrix and that there is no feedback operation that preserves them. Known invariants, such as the minimum equivalent noise temperature ${T}_{{N}{min}}$ and ${N}$ , may be expressed in terms of such eigenvalues. In addition, we provide a complete characterization of the four noise parameters of two-port passive dissipative networks in terms of their gain parameters and derive the condition under which the invariant ${4N}{T}_{{0}}{/}{T}_{{N}{min}}$ of passive nonreciprocal networks is lower than two. We also extend the theory of special noise invariants to LNAs with lossy input matching network. Overall, the impact of the findings emerging from the theory is highlighted through theorems, remarks, circuit examples, and studies on widespread design methodologies. [ABSTRACT FROM AUTHOR]

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings. [ABSTRACT FROM AUTHOR]

Computationally-secure cryptographic algorithms implemented on a physical platform leak significant “side-channel” information through their power supplies. Correlational power attack is an efficient power side-channel attack (SCA) technique, which analyzes the statistical correlation between the estimated and the measured supply current traces to extract the secret key. The existing power SCA countermeasures are mainly based on reducing the SNR of the leaked information, power balancing, or gate-level masking, each of which introduces significant power, area or performance overheads, which calls for an efficient generic countermeasure. This paper presents ASNI: Attenuated Signature Noise Injection, which is an energy-efficient generic countermeasure, and shows SCA resistance on the AES-128 encryption as an application. ASNI uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by ${>}200 \times $ in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the ASNI, with the AES-128 core operating at 40 MHz, shows that the system remains secure even after 1 M encryptions, with $\sim 25 \times $ reduction in power overhead compared to that of noise addition alone. [ABSTRACT FROM AUTHOR]

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6 lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard $0.18~\mu \text{m}$ CMOS technology. It achieves transimpedance gain of 68.3dB $\Omega $ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of $0.97~\mu $ Arms. The chip occupies 0.78 mm2 while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC. [ABSTRACT FROM AUTHOR]

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital $\Delta \Sigma $ modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

A new approach to augment existing noise models in a relaxation oscillator by including noise spikes during state change, an important aspect hitherto not covered in existing noise models, is proposed. Such noise spike is due to regeneration at the jump and this paper attempts to offer an explanation by viewing state change as a physical phase change in a thermodynamic system, which is also due to regeneration. The connection is established by viewing the relaxation oscillator as a combination of bistable circuit (exhibits metastablility) and a timing capacitor. Similarly the thermodynamic system exhibits physical phase change (metastability). Formula is derived to predict the “magnitude” of the noise spike, as a function of regeneration parameter, and hence design parameter such as gm, R, {I}_{0}. Simulations (Eldo) on circuits and simulations (Metropolis) on thermodynamic system as well as measurements on circuits fabricated in 0.13 \mu$m CMOS technology are consistent with theory. [ABSTRACT FROM PUBLISHER]

Self-organizing map (SOM)-based motif mining, despite being a promising approach for problem solving, mostly fails to offer a consistent interpretation of clusters with respect to the mixed composition of signal and noise in the nodes. The main reason behind this shortcoming comes from the similarity metrics used in data assignment, specially designed with the biological interpretation for this domain, which are not meant to consider the inevitable noise mixture in the clusters. This limits the explicability of the majority of clusters that are supposedly noise dominated, degrading the overall system clarity in motif discovery. This paper aims to improve the explicability aspect of learning process by introducing a composite similarity function (CSF) that is specially designed for the k -mer-to-cluster similarity measure with respect to the degree of motif properties and embedded noise in the cluster. Our proposed motif finding algorithm in this paper is built on our previous work robust elicitation algorithms for discovering (READ) [1] and termed READ Deoxyribonucleic acid motifs using CSFs (READ _{\rm csf} ), which performs slightly better than READ and shows some remarkable improvements over SOM-based SOMBRERO and SOMEA tools in terms of F$ -measure on the testing data sets. A real data set containing multiple motifs is used to explore the potential of the READ _{\rm csf} for more challenging biological data mining tasks. Visual comparisons with the verified logos extracted from JASPAR database demonstrate that our algorithm is promising to discover multiple motifs simultaneously. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a time-interleaved RF carrier modulation and demodulation technique, suitable for high frequency mixer applications under a constraint of active device speed limitation. The presents are in essence mixer arrays where modulated outputs by a series of time-delayed carriers with a reduced frequency, compared with a carrier frequency in fundamental mixers, will be interleaved in the time domain to synthesize the final output. The mixer arrays inherit an FIR filtering function, and the time interleaving process is equivalent to the filtering process where the arrays select the fundamental tone or its harmonics of a carrier in a periodic manner. The carrier waveform and duty-cycle play important roles in the noise performance of the mixer arrays. A comprehensive noise analysis is presented in this paper for both cases of correlated-noise and uncorrelated-noise mixer arrays. To minimize output noise power, optimization of carrier duty-cycle and noise filtering technique have been proposed and analyzed extensively for various types of carrier pulse. Finally analytical mismatch models are provided and output SNR degradations under finite mismatches amongst mixer array elements have been discussed based on the mismatch models. All theoretical analyses are verified through behavioral mixer array simulations including Monte-Carlo statistical simulations. [ABSTRACT FROM AUTHOR]

The paper introduces a new concept of a true random number generator (TRNG). Most metastability-based solutions operate on the uncertainty of a logical output state of a device (flip-flop, D-latch) aimed to be resolved from an exact metastable point. However, it has been shown that the metastable point of a bistable circuit (which is practically impossible to reach) does not guarantee absolute randomness or sufficient entropy. We propose the concept of a device in which the direct proximity of the metastable point is not mandatory. In our concept the transition times of two devices are compared. Such construction is less sensitive to the proximity of the metastable point, temperature fluctuations, and power supply instabilities. The paper briefly describes the metastability phenomena in general and other known metastability-based TRNG concepts. A new concept of a dual-metastability time-competitive generator is presented, analyzed both numerically and theoretically, and verified based on the sample circuit's implementation. Empirical and statistical test results are presented. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of energy-to-peak stochastic stability (EPSS) of two-dimensional (2-D) Roesser systems in the presence of state time-varying delays and multiplicative noises. First, a scheme that ensures a 2-D stochastic time-delay system is stochastically stable with an attenuation performance is proposed. The scheme presented in this paper can be regarded as an extension of the Lyapunov–Krasovskii functional method for 2-D stochastic time-delay systems, focusing on the EPSS problem. The proposed scheme is then utilized to derive delay-dependent EPSS conditions in terms of tractable linear matrix inequalities. A numerical example is given to illustrate the effectiveness of the derived stability conditions. [ABSTRACT FROM AUTHOR]

This paper studies the optimal decentralized state-feedback control of large-scale systems. The large-scale system is composed of subsystems and defined over a connected digraph. One step time is required for information to travel across an edge in the graph. Under the above-mentioned setup, when subsystem process noises are uncorrelated, the explicit optimal state-feedback controller can be designed by independence decomposition based on information hierarchy graph. However, this decomposition method fails when the subsystem process noises are correlated. In this paper, we propose a new decomposition method for system state and control input, and split the optimal state-feedback control problem with correlated process noises into two subproblems that can be solved separately. The solution to the first subproblem can be obtained by solving a linear matrix equation. The second subproblem is solved by algebraic Ricatti equation. [ABSTRACT FROM AUTHOR]

This paper proposes a low-temperature coefficient (TC), noise, and offset bandgap reference (BGR) for the high precision applications. In order to reduce the offset voltage and noise introduced by the error amplifier, the offset and noise suppression technique is proposed. A five-piece linear compensation has been applied in the BGR to improve the TC performance. Moreover, an adaptive current loop is added to the bandgap reference to enhance the current driving capability. The proposed BGR is implemented in a $0.35~\mu \text{m}$ standard CMOS process occupying an active area of $0.22 \times 0.28$ mm2. The measured results show that the average TC is 3 ppm/°C −45 °C to 125 °C after trimming. The output reference voltage of 2.47 V can achieve $3.6~\mu \text{V}$ (rms) noise from 0.1 to 10 Hz. In the supply voltage range of 2.6 to 5 V, the proposed BGR can deliver $30~\mu \text{A}$ load current and its PSRR is about −83 dB @ 100Hz. [ABSTRACT FROM AUTHOR]

In this paper, we will present an all-CMOS oscillator based on monolithically integrated MEMS resonators fabricated from the VIA layer (tungsten) of a 0.35~\mu \textm CMOS technology process. With this CMOS MEMS closed-loop system, the nonlinear MEMS frequency response due to the electrostatic actuation has been reconstructed. Using a phase-controlled closed-loop the frequency stability of the self-sustained oscillator at different nonlinear operation points has been analyzed, showing an optimal point belonging to the unstable region of the MEMS resonator. [ABSTRACT FROM AUTHOR]

Purpose: Pulsating torques cause a number of problems in electrical machines, including mechanical vibrations, acoustic noise and the depreciation of mechanical equipment. In induction motors, the slot skewing method is an effective way to solve these issues; however, it has some drawbacks such as output torque drop, stray loss intensification due to inter-bar currents and iron loss increment. Besides, slot skewing may not be practical in higher-rated induction motors. In this regard, this paper introduces a modified non-skewed rotor (MNSR) structure as a possible alternative to the skewed designs. Design/methodology/approach: The proposed structure includes a two-segmented rotor with an intermediate ring between the rotor parts that are mounted on the shaft with a relative shift angle. Detailed information about the idea and structure of the MNSR as well as its manufacturing aspects will be presented in the second section of the paper. First, the working principle of the proposed design is described via analytical equations to provide an insight into the concept. The shifting angle will then be calculated by analyzing the harmonic contents of the electromagnetic torque. Finally, the validity of the analytical method will be verified by developing three-dimensional finite element models. Findings: It is demonstrated that by using the proposed rotor structure, the torque ripple has been reduced to a satisfactory level without significantly affecting the mean torque, unlike the skewing method. Furthermore, the new method could avoid the disadvantages of the skewing method while enhancing other motor characteristics such as iron loss. Also, the total volume of the MNSR is equal to the initial design, and the mass and material differences are also negligible. Originality/value: In this paper, a MNSR is introduced as a possible alternative to the skewed patterns. The study mainly focused on electromagnetic torque profile characteristics, i.e. the mean torque enhancement and the ripple reduction. The MNSR structure can be used for general purposes and high-performance applications, especially where excellent torque characteristics are required. [ABSTRACT FROM AUTHOR]

In the era of big data, the data in many business scenarios are characterized by a small number of labelled samples and a large number of unlabelled samples. It is quite difficult to classify and identify such data and provide effective decision support for a business. A commonly employed processing method in this kind of data scenario is the disagreement-based semisupervised learning method, i.e., exchanging high-confidence samples among multiple models as pseudolabel samples to improve each model's classification performance. As such pseudolabel samples inevitably contain label noise, they may interfere with the subsequent model learning and damage the robustness of the ensemble model. To solve this problem, a semisupervised classification algorithm based on noise learning theory and a disagreement cotraining framework is proposed. In this model, first, the probably approximately correct (PAC) estimation theory under label noise conditions is applied, the relationship between the label noise level and model robust estimation in the process of multiround cotraining is discussed, and a disagreement elimination algorithm framework based on multiple-model (feature argument and select (FANS) algorithm and L1 penalized logistics regression (PLR) algorithm) cotraining is constructed based on this theoretical relationship. The experimental results show that the algorithm proposed in this paper gives not only a high-confidence sample set that meets the upper bound constraint of the label noise level but also a robust ensemble model capable of resisting sampling bias. The work performed in this paper provides a new research perspective for semisupervised learning theory based on disagreement. [ABSTRACT FROM AUTHOR]

The article discusses various papers presented at the 13th International Conference on Low Frequency Noise and Vibration and its Control held in Tokyo, Japan from October 20 to 23, 2009. The event recorded 64 delegates from different countries. The papers presented include a review of the perception of low frequency noise (LFN) and the responses of people to LFN, a discussion on the problems associated with low frequency air vibration and a lecture on the possibility of infrasonic music.

The common mode (CM) current in differential circuits generates CM noise which radiates in the environment and causes electromagnetic interference (EMI) with electronic devices in proximity. This noise is generated due to imbalance in the charging and discharging paths of the driver circuit and asymmetric equalization. A systematic study of how asymmetric equalizer increase the CM noise is still lacking. Few active on-chip solutions are proposed for wireline transmitters up to 20-Gbps speed. However, these solution does not suppress CM noise by the equalizer and they could not support four-level pulse amplitude modulation (PAM-4) optical transmitters. This paper analyzes two potential sources of EMI-related CM noise, the common mode logic (CML) driver and feed forward equalization (FFE) circuit, and presents a novel on-chip active circuit technique for automatic CM noise cancellation in high-speed PAM-4 transmitter. This solution provides the benefits of small size and low cost by eliminating the need for discrete components to suppress EMI. The post-layout simulation demonstrates that the CM noise cancellation circuit (CMNC) efficiently mitigate the EMI by suppressing the CM noise up to 90% and consumes 5 mW, with core area of $17 \mu m \times 9 \mu m$. [ABSTRACT FROM AUTHOR]

It is well known that multi-agent systems (MASs) are ubiquitous in natural and artificial systems. This paper aims at bridging the gap between transmission noise and sampled data for robust consensus of MASs. In detail, we have developed a theoretical framework for analyzing the robust consensus of MASs with sampled-data controllers and transmission noises. Using the delay-input and discretization approaches, we obtain two sufficient conditions on the existence of sampling periods and controller parameters for robust consensus of MASs, respectively. In particular, we deduce the estimates of the convergence speeds of consensus errors for the above two methods. Finally, numerical simulations are also given to validate our theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents the design of a continuous-time \Delta\Sigma modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm^2 and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 \mum CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 \muW, which corresponds to a figure-of-merit of 0.85 pJ/conv. [ABSTRACT FROM AUTHOR]

Checking validity of a model is a crucial step in the process of system identification. This is especially true when dealing with switched affine systems since, in this case, the problem of system identification from noisy data is known to be generically NP-Hard and can only be solved in practice by using heuristics and relaxations. Therefore, before the identified models can be used for instance for controller design, they should be systematically validated against additional experimental data. In this paper we address the problem of model (in)validation for multi-input multi-output switched affine systems in output error form with unknown switches. As a first step, we prove that necessary and sufficient invalidation certificates can be obtained by solving a sequence of convex optimization problems. In principle, these problems involve increasingly large matrices. However, as we show in the paper by exploiting recent results from semialgebraic geometry, the proposed algorithm is guaranteed to stop after a finite number of steps that can be be explicitly computed from the a priori information. In addition, this algorithm exploits the sparse structure of the underlying optimization problem to substantially reduce the computational burden. The effectiveness of the proposed method is illustrated using both academic examples and a non-trivial problem arising in computer vision: activity monitoring. [ABSTRACT FROM AUTHOR]

This paper presents a low-power compact analog circuit for processing time varying signals. The proposed circuit implements temporal differentiation, amplification and rectification, i.e., separation of outputs into on and off pathways. It is based on a hysteretic differentiator circuit, commonly used in neuromorphic vision sensors to implement temporal edge detection. This paper presents a thorough analysis of the original circuit and identifies the source of the problems and limitations it has for processing real-world sensory signals. The steps required to solve this problem are presented as well as an extended circuit with tunable gain and adaptable threshold that allows thresholding of small temporal changes (noise) and high-pass filtering of large temporal changes. The new circuit proposed is particularly suited for focal plane implementation of both gradient based and token based motion algorithms that require robust detection of temporal discontinuities. The circuit has been designed and successfully integrated into a 64 × 1 test prototype motion chip, fabricated in standard 350 nm CMOS technology. The paper provides extensive experimental characterization results. [ABSTRACT FROM PUBLISHER]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper is concerned with the almost sure exponential synchronization of a multilayer network which is set up on a non-strongly connected digraph that can be classified into several layers by Tarjan’s algorithm. Note that, in the multilayer network, white-noise-based time-varying coupling and drift term coupling are proposed to simulate two kinds of coexisting distinguishable interactions between vertices. We develop a normal analytical framework for studying synchronization of the multilayer network. Firstly, via aperiodically intermittent pinning noises, synchronization of vertices situated on the first layer is achieved in the layered network. Secondly, under the impact of the white-noise-based time-varying coupling in diffusion term, synchronization of the vertices located in other layer networks is developed with the support of synchronization for the pinned vertices. Employing Lyapunov method, graph theory and stochastic analysis technique, a criterion of almost sure global exponential synchronization is obtained. By adopting the concepts of average noise control rate and average noise control period proposed recently, we lessen the conservativeness of the conditions restricted on aperiodically intermittent noise control to optimize our results. Furthermore, an application to a class of Chua’s circuits is exhibited in detail. In the end, we provide a numerical example to verify the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

• Our paper shows how to stabilize an unstable nonlinear delay hybrid SDEs with Lévy noise. • We design a feedback control in both drift and diffusion parts based on discrete-time observations. • We prove the existence and boundedness of the unique global solution under a new set of suitable conditions. • We discuss several kinds of stability for the controlled system using Lyapunov functions. • Our findings improve and generalize some works done in the stabilization theory. There are many hybrid stochastic differential equations (SDEs) in the real-world that don't satisfy the linear growth condition (namely, SDEs are highly nonlinear), but they have highly nonlinear characteristics. Based on some existing results, the main difficulties here are to deal with those equations if they are driven by Lévy noise and delay terms, then to investigate their stability in this case. The present paper aims to show how to stabilize a given unstable nonlinear hybrid SDEs with Lévy noise by designing delay feedback controls in the both drift and diffusion parts of the given SDEs. The controllers are based on discrete-time state observations which are more realistic and make the cost less in practice. By using the Lyapunov functional method under a set of appropriate assumptions, stability results of the controlled hybrid SDEs are discussed in the sense of p th moment asymptotic stability and exponential stability. As an application, an illustrative example is provided to show the feasibility of our theorem. The results obtained in this paper can be considered as an extension of some conclusions in the stabilization theory. [ABSTRACT FROM AUTHOR]

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given. [ABSTRACT FROM AUTHOR]

Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant inter-symbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end’s first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design tradeoffs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise. [ABSTRACT FROM AUTHOR]

Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is observable right after manufacturing, such as geometric variations, work function, and random dopant fluctuation. This is in contrast to time-dependent variability (TDV), i.e., differences in the defects of transistors, which is not macroscopically observable immediately after manufacturing. In fact, defects are electrically neutral until they capture a carrier [with mechanisms called bias temperature instability (BTI) and random telegraph noise (RTN)] and thus become observable through their induced degradation. Therefore, transistors which are characterized identically after manufacturing will drift apart during their lifetime, as their susceptibility to effects such as BTI and RTN is different. In this paper, we model for the first time TDV from a defect-centric physical perspective all the way to the circuit level. Our novel defect-centric transistor reliability specification provides a fast, yet accurate method to estimate an upper bound for TDV on the transistor level, while our novel worst cell (WCL) and worst value (WVL) libraries allow for fast evaluation of the impact of TDV on the timing of circuits. Our approach is fully compatible with existing EDA tool flows, allowing us to model and optimize complex circuits like full microprocessors. By evaluating the impact of TDV with our reliability specification and variability-aware cell libraries, we are able to model TDV, which allowed us to reduce the required defect variability guardband by 46%. In addition, we provide design optimization strategies on each abstraction level such as limiting continuous stress, transistor hardening, and implement a novel variability-aware synthesis to achieve up to 57% additional guardband reduction. [ABSTRACT FROM AUTHOR]

In previous work, generally, stochastic delayed coupled systems were considered on a network with a single weight. However, stochastic delayed coupled systems on a network with multi-weights have not been fully investigated and remain to be important and challenging. Hence, in this paper, time delays and Lévy noise are taken into account in stochastic coupled systems on a network with multi-weights. Furthermore, synchronization of stochastic delayed coupled systems with Lévy noise on a network with multi-weights (SDCSLM) is first studied via aperiodically intermittent control. Then, by means of the Lyapunov method, graph theory and some techniques of inequalities, some sufficient conditions for $p$ th moment exponential synchronization of SDCSLM are obtained. Particularly, as a practical application of the theoretical results, the exponential synchronization in mean square of stochastic Chua’s circuits with time delays and Lévy noise on a network with multi-weights is studied in detail. Finally, some numerical simulations are given to show the effectiveness of the theoretical results. [ABSTRACT FROM AUTHOR]

Accurately resolving small fluorescence power variations in presence of noise and high-background tissue autofluorescence from deep brain structures with a fiber photometry system requires highly linear and sensitive photo detectors. This paper presents a high-dynamic range (DR) CMOS biosensor fusing a low-noise photosensing front-end with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $\Sigma \Delta $ ADC, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide-dynamic range and high-precision fluorescence sensing. The reset noise is canceled out by an embedded noise cancellation scheme which is subtracting the reset noise from the signal using a correlated double sampling scheme. Unlike other solutions, the biosensor has a short conversion time of $306.5~\mu \text{s}$ compared to a typical fluoresence sampling period of 10 ms, providing a very low duty cyle of 3%, which is a key to achieve low excitation source power consumption in this application to extend system autonomy, and to avoid photobleaching and phototoxicity in the tissue. The proposed optoelectronic biosensor is implemented in a 0.18- $\mu \text{m}$ CMOS technology, consuming $93~\mu \text{W}$ from a 3.3-V supply voltage while achieving a DR of 104 dB, a minimum detectable current of $1.3~\text {pA}_{\mathrm{ rms}}$ , and a chip area of 0.475 mm2. We present the measured performance of the biosensor using an optical experimental setup including a LED driver, a fiber optic, and a test board. [ABSTRACT FROM AUTHOR]

This paper deals with the $H_{\infty }$ fault detection (FD) problem for a class of buck converter with the transmission-induced multiplicative noises and the event-triggered scheme under the network environment. The model of buck converter is approximated by a nonlinear model, and it is further analyzed based on the electricity knowledge. Due to the dynamic characteristics of network transmission, multiplicative noises need to be considered, which are described as a product of some uncorrelated standardized normal distribution and the transmitted signal. Meanwhile, an event-triggered mechanism is utilized for the purpose of reducing the energy consumption, and an FD observer is designed to detect the fault presented in buck converter. Some novel sufficient conditions are given in terms of linear matrix inequalities to guarantee the robust stability of the FD system, and the $H_{\infty }$ optimal fault tracking performance index is also achieved. Finally, an illustrative example is provided to show the validity and merit of the proposed method. [ABSTRACT FROM AUTHOR]

Perimeter-gated single-photon avalanche diodes (PGSPADs) have been shown to mitigate premature edge breakdown without unduly increasing the area of the device. PGSPADs are three terminal devices. In this paper, we develop a probability-based SPICE model for the PGSPAD and fully characterize an $18 \times 18$ pixel analog PGSPAD-based CMOS silicon photomultiplier (SiPM). The noise model is derived using theories of carrier thermal generation, carrier diffusion, and inter-band tunneling. Parameters are derived using fabricated PGSPAD devices and model validity is verified with experimental measurements. The designed PGSPAD SiPM is implemented in standard $0.5~\mu \text{m}$ 2-poly, 3-metal CMOS process, and is characterized for dark current, sensitivity, and signal-to-noise ratio (SNR) throughout the visible spectral range for varying bias voltages. Models show that the reduction of dark events in the PGPSAD is primarily caused by a reduction in band-to-band tunneling. Thus, as a function of the applied gate voltage the PGPSAD shows an improvement of SNR over a range of 1 to 1150. The sensitivity of the presented SiPM is $1.06 \times 10^{3}$ A/W/cm2. The designed PGSPAD SiPM shows great promise over standard SiPM for applications, such as neutron detection which requires high sensitivities and high SNRs. [ABSTRACT FROM AUTHOR]

In this paper, a built-in self-test and in situ analog circuit optimization platform is proposed and characterized. By integrating a fully digital optimization engine and self-test circuits along with circuits-under-optimization (CUO), this platform can automatically find an operating point that makes a good balance among multiple competing characteristic goals. Therefore, the arbitrary linear time-invariant CUO can be optimized even when there are large process-voltage-temperature variations and aging effects of devices. This platform is analyzed to determine the required accuracy of its building blocks in terms of noise and linearity. The feasibility of this platform is proved by a case study utilizing a Tow-Thomas bandpass biquad. [ABSTRACT FROM AUTHOR]

A transimpedance amplifier (TIA) in the front-end of a radiation detector is required to convert the current pulse produced by a light-detector to a voltage pulse with amplitude and shape suitable for the subsequent processing. We consider in this paper the specifications of a positron emission tomography (PET) scanner for medical imaging. [ABSTRACT FROM AUTHOR]

This paper exploits the predominance of embedded memories in current and emerging wireless transceivers as a means to save power via channel state aware voltage scaling. The paper presents a statistical model that captures errors in embedded memories due to voltage over-scaling and maps the errors to a Gaussian distribution that represents a combination of communication channel noise and hardware noise. Designers can use the proposed model to investigate different power management policies, that capture the performance of the system as a function of both channel and hardware dynamics, thus creating a much richer design space of power, performance and reliability. A case study of a DVB receiver is presented and the validity of the proposed model is confirmed by simulations. [ABSTRACT FROM AUTHOR]

The article offers information on the discovery of gravitational waves by the Laser Interferometer Gravitational-Wave Observatory (LIGO) and questions raised on the validity of LIGO's discoveries. Topics discussed include the views of Andrew Jackson, the spokesperson of a group of physicists who have analyzed LIGO's data; the methods used by LIGO to extract gravitational wave signal from the noise; and the views of Neil Cornish of Montana State University, a data analysts for LIGO, on it.

In this paper, we propose a symplectic numerical integration method for a class of Hamiltonian stochastic differential equations with multiplicative Lévy noise in the sense of Marcus. We first construct a general symplectic Euler scheme for these equations, then we prove its convergence. In addition, we provide realizable numerical implementations for the proposed symplectic Euler scheme in detail. Some numerical experiments are conducted to demonstrate the effectiveness and superiority of the proposed method by the simulations of its orbits, Hamiltonian and convergence order over a long time interval. The results show the applicability of the methods considered. [ABSTRACT FROM AUTHOR]

This paper addresses integral input-to-state stability (iISS) for stochastic nonlinear dynamical systems and develops Lyapunov-type criteria. The developments offer an iISS small-gain framework for verifying robustness of interconnected systems with respect to disturbances. The framework not only includes input-to-state stability (ISS) as a special case, but also highlights fundamental differences between the stochastic and deterministic systems. In particular, dealing with nonlinearities in interconnection gives rise to a unique issue of degradation in the presence of stochastic noises. This paper addresses this issue by coping judiciously with the effect of the gradient of Lyapunov functions of subsystems through diffusion fields in composing a Lyapunov function of the entire system. This paper employs two types of robustness notions, and demonstrates that the influence of the stochastic degradation on one notion is considerably different from the influence on the other notion in dealing with interconnected systems. [ABSTRACT FROM PUBLISHER]

This paper addresses the problem of obtaining an estimate of a particular module of interest that is embedded in a dynamic network with known interconnection structure. In this paper it is shown that there is considerable freedom as to which variables can be included as inputs to the predictor, while still obtaining consistent estimates of the particular module of interest. This freedom is encoded into sufficient conditions on the set of predictor inputs that allow for consistent identification of the module. The conditions can be used to design a sensor placement scheme, or to determine whether it is possible to obtain consistent estimates while refraining from measuring particular variables in the network. As identification methods the Direct and Two Stage Prediction-Error methods are considered. Algorithms are presented for checking the conditions using tools from graph theory. [ABSTRACT FROM AUTHOR]

This paper addresses the robust gradient learning (RGL) problem. Gradient learning models aim at learning the gradient vector of some target functions in supervised learning problems, which can be further used to applications, such as variable selection, coordinate covariance estimation, and supervised dimension reduction. However, existing GL models are not robust to outliers or heavy-tailed noise. This paper provides an RGL framework to address this problem in both regression and classification. This is achieved by introducing a robust regression loss function and proposing a robust classification loss. Moreover, our RGL algorithm works in an instance-based kernelized dictionary instead of some fixed reproducing kernel Hilbert space, which may provide more flexibility. To solve the proposed nonconvex model, a simple computational algorithm based on gradient descent is provided and the convergence of the proposed method is also analyzed. We then apply the proposed RGL model to applications, such as nonlinear variable selection and coordinate covariance estimation. The efficiency of our proposed model is verified on both synthetic and real data sets. [ABSTRACT FROM AUTHOR]