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There has been an increasing interest in multi-task learning for video understanding in recent years. In this work, we propose a generalized notion of multi-task learning by incorporating both auxiliary tasks that the model should perform well on and adversarial tasks that the model should not perform well on. We employ Necessary Condition Analysis (NCA) as a data-driven approach for deciding what category these tasks should fall in. Our novel proposed framework, Adversarial Multi-Task Neural Networks (AMT), penalizes adversarial tasks, determined by NCA to be scene recognition in the Holistic Video Understanding (HVU) dataset, to improve action recognition. This upends the common assumption that the model should always be encouraged to do well on all tasks in multi-task learning. Simultaneously, AMT still retains all the benefits of multi-task learning as a generalization of existing methods and uses object recognition as an auxiliary task to aid action recognition. We introduce two challenging Scene-Invariant test splits of HVU, where the model is evaluated on action-scene co-occurrences not encountered in training. We show that our approach improves accuracy by ~3% and encourages the model to attend to action features instead of correlation-biasing scene features.

Compounds 2-5, incorporating various elements of the 3,4′- bis(piperidine) core associated with the sponge-derived alkaloid haliclonacyclamine A (HA, 1), have been prepared through, inter alia, aldol-type reactions of N-substituted piperidin-4-ones and

A series of enantiomerically pure C8cC15 monoseco analogues, 2330, of the alkaloids cryptopleurine (1) and julandine (2) have been prepared using cinnamyl chloride 37 and (S)- or (R)-2-methylpiperidine as key building blocks. Two related compounds, 31 and 32, have also been synthesized. Each of these analogues has been subjected to various biological evaluations and most of them show dramatically reduced cytotoxicity compared with parent system 1. Nevertheless, they are potent anti-angiogenic agents. The formation and single-crystal X-ray analysis of the spirocyclic dienone 54, a by-product arising from attempts to prepare analogue 32, is also described.

Four enantiomerically pure monoseco-analogues, 5, 7, 9, and 11, of the phenanthroquinolizidine alkaloid julandine (1) and four of congener cryptopleurine (2), viz. compounds 6, 8, 10, and 12, have been prepared and subjected to preliminary biological evaluation. These analogues show dramatically reduced cytotoxicity compared with the parent system 2 but they are, nevertheless, potent anti-angiogenic agents.

Two novel analogues, 2 and 3, of the C-riboside showdomycin (1) have been prepared by exploiting the N-TIPS-substituted pyrrole 7 as a synthetic equivalent for the maleimide C3 anion. The tetraacetate precursor, 12, of target 2 as well as target 3 itself

Tuberose (Polianthes tuberosa L. cv. Double) corms at the vegetative, early floral initiation, and flower bud differentiation stages were assayed for free indole-3-acetic acid (IAA), esterified IAA, and peptidyl IAA. The corms in the vegetative stage contained higher free IAA than those from the early floral initiation stage. Free IAA in corm tissues increased 2.7-fold at flower bud differentiation as compared to the vegetative stage. In the vegetative corms, a marked promotion of leaf differentiation was recorded. In contrast, corms from the early floral initiation stage contained less free IAA, whereas esterified IAA and peptidyl IAA increased dramatically. It is concluded that the level of free IAA in vegetative corms is correlated with leaf differentiation, and that the early floral initiation stage is correlated with a reduction in free IAA and an increase in IAA conjugates in the corms. Moreover, increases in free IAA and decreases in IAA conjugates in the floral differentiation stage, as compared to the early floral initiation stage, indicates that free IAA is correlated with flower development.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Chapter 2 reports our new research results. We present three algorithms to test the instruction decoding function of microprocessors.

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI(Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VSLI-based systems. As a result of the rapidly increasing complexity of modern digital LSI/VLSI systems, functional testing is attracting more attention than ever not only in the computer manufacturing industry but also in the diversified potential applications. Functional testing uses a representation of a digital system higher than the gate-level testing. In functional testing, functional faults with respect to the functional specification (e.g., addition operation in a processor) are tested instead of a signal faults (e.g., a line stuck-at logical 0) in the circuit representation. The purpose of functional testing is to validate correct functional operations of digital systems according to their specifications.

This paper presents three algorithms to test the instruction decoding function of microprocessors. The algorithms are based on the knowledge of some timing and control information available to users through microprocessor manuals and data sheets. The tests are functional in nature. The authors establish the order of complexity of the algorithms presented in this paper. As an example, the test complexity for a microprocessor is computed and the results are compared with a known algorithm.

Functional testing is a feasible solution for LSI/VLSI test generation and design verification. In this paper, we present a systematic way to perform functional testing using an advanced symbolic execution technique. Symbolic execution is a very useful and powerful software engineering technique mainly used in program analysis including test generation. Often a single symbolic execution of a program may represent a large number of normal test runs.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.

This paper presents a method for functional testing of microprocessors. First, we develop a control fault model at the RTL (Register Transfer Language) level. Based on this model, we establish testing requirements for control faults. We present three test procedures to verify the write and read sequences and use the write and read sequences to test other instructions in a microprocessor. By utilizing k-out-of-m codes, we can use fewer tests to cover more faults, thereby reducing the test generation time. (Author)

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI (Very Large Scale Integrated) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VLSI-based systems. This report is organized into two chapters. Chapter 1 presents the state-of-the-art for the functional testing of LSI/VLSI devices with special emphasis on microprocessor testing. Various types of IC chips are briefly discussed. Different approaches for testing the functional faults of LSI/VLSI are surveyed and the comparison of these methods are given. Fault models for representing the faults and fault coverage of the tests are discussed. Some of the important unresolved problems and current trends in testing VLSI are pointed out.

Microprocessor is a type of complex sequential machine. The current approach is to test microprocessor by instruction execution. Generally, before executing an instruction-under-test, we have to write certain data into some registrers, and after executing the instruction, we have to read the contents of the registers. Therefore, if the write or read instruction is faulty, we may not be able to test the instruction-under-test. To solve this problem, Thatte and Abraham have to label instructions and define test order in detail before testing. In addition, they do not consider the partial execution of an instruction. So one of the instruction decoding faults I(j)/I(j)+I(k) is assumed that, instead of executing I(j), both insructions I(j) and I(k) are executed to completion. This raises the problem of practicality. Abraham and Packer's method is simple, but their 'register read' test procedure does not guarantee the correctness of write and read register functions for any data. In our work, we consider the write and read register function as a kernel of a microprocessor; similar to a sequential machine, and we use the checking experiment to verify the kernal based on the fault models. Then we use the kernal for testing other instructions. Our approach consists of three steps: Step 1: Establish the fault model for representing functional faults, Step 2: Determine the requirement for test generation, and Step 3: Based on the requirements, develop testing mprocedures.

We started the project by initiating a study of available literature that is related to the scope of work for this project. Testing of high complexity LSI and VLSI components has become very important, and has been receiving considerable interest. The project involves a test-effectiveness measure. Because of the complexity of the problem, it has not yet been satisfactorily approached by others. Some work on information theoretic approach has been reported, but the approach does not appear to be suitable for testing digital system with high fault coverage. We feel that test-effectiveness measure should be related with physically possible failures, and thus the measure should be available to use detailed information of the circuitry if it is available.

The author has studied thoroughly the fundamental contributions made by Thatte and Abraham who have considered the problem of micro-processor testing, Based on the architecture information available to a user and the instruction set for a given microprocessor, they define a graph model of the microprocessor under consideration. This model is then used to derive necessary tests. Their approach is, first to label the nodes and edges in the graph based on the observability of such nodes and edges. The faults are divided into five different classes namely register decoding, instruction decoding/control, data path, data storage and data manipulation faults. Explicit models are given for all these fault classes and functional units. It is assumed that no more than one functional unit is faulty, though any number of faults of one class can be present. Procedures are then developed to detect faults of different classes. They have also studied the fault coverage of their tests for a Hewlett Packard system.