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This paper presents a power supply using an increased switching frequency to minimize the size of energy storing components, thereby addressing the demands for increased power densities in power supplies. 100 MHz and higher switching frequencies have been used in resonant power converters, which along with the possible integration of passive components on silicon wafer, present a beneficial solution in applications such as mobile phones. This paper presents a design for a 9 W class E resonant power converter in an 0.18 µm CMOS process. The converter is driven by a self oscillating gate drive, which is presented in an in-depth mathematical analysis. The gate resistance of the designed transistors is of critical importance in order to achieve the correct phase shift required for zero-voltageswitching. The Z-parameter method is used to characterize the transistors which is verified through simulations. The required spiral inductors was modeled, and simulations show Q values of as high as 14 at a switching frequency of 250 MHz. Simulations of the converter show an efficiency of 55 % with a self oscillating gate drive. However the modeled inductor was not adequate for operating with the self oscillating gate drive, presenting a future challenge for power supplies on chip.

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode., Electronics

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode., Electronics

This document describes the design, construction, and testing of a proof-of-concept hardware and software package that combines cognitive radio and autonomous vehicles in a single system whose behavior captures the essential features of both. The result is a low-cost (less than $200) cognitive radio and cognitive engine package suitable for installation in the small experimental UAVs flown by USAFRL. Experiments with the package controlling a small wheeled vehicle demonstrate its ability to explore and learn a multidimensional environment that combines changing RF, location, and mission data and to optimize its mission performance intelligently., The original document contains color images.

In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

The availability of low-powered and cheap microprocessors, radio frequency integrated circuits and the development of new wireless communication techniques, make the wireless sensor networks (WSN) one of todays most promising technologies. Minimizing energy consumption and maximizing the lifetime of the networks are key requirements in the design of sensor network applications. Optimally designed medium access control (MAC) and routing protocols minimize energy consumption and prolong the network life. In this study, we have investigated an energy-efficient adaptive TDMA (EA-TDMA) protocol for railway applications that used in communication between sensor nodes and the cluster-head (CH) placed in a railway wagon. This protocol is suitable for medium traffic applications and reduces energy consumption by shortening the idle period when devices have no data to transmit. We have developed an analytical model for EA-TDMA and compared its performance with conventional TDMA and bit-map-assisted (BMA) protocols.

A granular NiFe thin film with large in-plane magnetic anisotropy and high ferromagnetic-resonance frequency developed for radio-frequency integrated circuit (IC) applications is presented. During the deposition, three-dimensional (3D) growth occurs, yielding NiFe grains (? ? 1.0??m). Nanonuclei (? ? 30–50?nm) are observed in single NiFe grains by atomic-force microscopy (AFM). The in-plane magnetic anisotropy is estimated to be ? 50?mT. The frequency-dependent complex permeability is extracted. By taking the NiFe film as a magnetic core, solenoid-type inductors are fabricated and demonstrated and show a high operating frequency ( ? 5.5?GHz) with a maximum quality factor ( ? 3)., Electrical Engineering, Mathematics and Computer Science

A granular NiFe thin film with large in-plane magnetic anisotropy and high ferromagnetic-resonance frequency developed for radio-frequency integrated circuit (IC) applications is presented. During the deposition, three-dimensional (3D) growth occurs, yielding NiFe grains (? ? 1.0??m). Nanonuclei (? ? 30–50?nm) are observed in single NiFe grains by atomic-force microscopy (AFM). The in-plane magnetic anisotropy is estimated to be ? 50?mT. The frequency-dependent complex permeability is extracted. By taking the NiFe film as a magnetic core, solenoid-type inductors are fabricated and demonstrated and show a high operating frequency ( ? 5.5?GHz) with a maximum quality factor ( ? 3)., Electrical Engineering, Mathematics and Computer Science

Summary form only given. The silicon-on-insulator (SOI) CMOS technology has been attractive for radio frequency (RF) integrated circuits due to its advantages of reduced parasitic capacitance, minimal substrate loss and noise coupling, and monolithic integration of high-Q passive components. However, there are various choices of SOI device structures such as fully depleted (FD), partially depleted (PD) and dynamic threshold (DT) MOSFET's. While the relative merits of the SOI devices in terms of current driving capability, small-signal gain and maximum cut-off frequencies have been extensively studied, the direct comparisons of their noise performance at gigahertz frequencies are very few in the literature. In order to fill the gap, we have performed extensive RF noise characterizations of the common SOI devices together with the effects of scaling, body contact scheme, and operation conditions. © 2002 IEEE.

Summary form only given. The silicon-on-insulator (SOI) CMOS technology has been attractive for radio frequency (RF) integrated circuits due to its advantages of reduced parasitic capacitance, minimal substrate loss and noise coupling, and monolithic integration of high-Q passive components. However, there are various choices of SOI device structures such as fully depleted (FD), partially depleted (PD) and dynamic threshold (DT) MOSFET's. While the relative merits of the SOI devices in terms of current driving capability, small-signal gain and maximum cut-off frequencies have been extensively studied, the direct comparisons of their noise performance at gigahertz frequencies are very few in the literature. In order to fill the gap, we have performed extensive RF noise characterizations of the common SOI devices together with the effects of scaling, body contact scheme, and operation conditions. © 2002 IEEE.

Summary form only given. The silicon-on-insulator (SOI) CMOS technology has been attractive for radio frequency (RF) integrated circuits due to its advantages of reduced parasitic capacitance, minimal substrate loss and noise coupling, and monolithic integration of high-Q passive components. However, there are various choices of SOI device structures such as fully depleted (FD), partially depleted (PD) and dynamic threshold (DT) MOSFET's. While the relative merits of the SOI devices in terms of current driving capability, small-signal gain and maximum cut-off frequencies have been extensively studied, the direct comparisons of their noise performance at gigahertz frequencies are very few in the literature. In order to fill the gap, we have performed extensive RF noise characterizations of the common SOI devices together with the effects of scaling, body contact scheme, and operation conditions. © 2002 IEEE.