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The evolution in the market of cars with electric power trains requires accurate optimization of power management sections. In electric cars, the power is collected and stored in a 400V battery, and then, from this battery, it is downscaled to lower voltage domains like 48V, 12V, 5V 3V, etc employing complex multi-stage switching DC-DC Converters. This operation could result in severe power losses and then topology optimization is mandatory. In this paper, a platform for a fast study and optimization of different DC-DC converter topologies developed in MATLAB environment is proposed. In the platform, basic DC-DC converter building blocks (inductive, and switched-capacitor) are available to compose complex DC-DC converter structures and to evaluate their fundamental limit performance and passive component values. Building block models are validated by circuit-level simulations. As example, the complete example of a DC-DC Converter from 400V down to 3V is proposed.

This paper presents a methodology based on SystemC-AMS and supported by the COSIDE graphical design environment for the development of automatic test-solutions for Integrated Circuits, which optimises the design of test-hardware and the coding of test-programs.The proposed development framework allows efficient design of test-hardware and rapid mixed-signal simulation of test-program sections, offering insight on the analog behaviour of the test-setup and on the interaction between the test-hardware, the Automatic Test Equipment and the Device Under Test, allowing early investigation and troubleshooting of the test-solution.The framework is validated within an industrial test-scenario by investigating solutions for the measurement of a rapidly changing voltage curve and by designing a narrow current pulse generator circuit where active components are used to modulate the native Automatic Test Equipment capabilities. The investigated solutions are integrated in the physical test-board and probe-card of the specific Device Under Test, and bench measurements are performed within the test-program execution.The comparison between simulation results and bench measurements highlights the capability of the presented SystemC-AMS framework in offering an accurate analog representation of the modelled components and properly supporting the development of automatic test-solutions.

This paper presents a digital denoising stage for Proton Sound Detectors, that measures the range (the penetration depth) of clinical proton beams, by sensing the Time-of-Flight (ToF) of the weak acoustic signal emitted at the end of the beam penetration path. Such acoustic signal/pulse is initially fed to a low-noise analog front-end for digitalization and then to the Acoustic Denoising Digital Signal Processing (AcousticDenDSP) stage. The digital acoustic pulse has a noise bandwidth of 1 MHz and a much narrower acoustic bandwidth, centered on different fundamental frequencies (38.5 kHz (300 kHz) for 200 MeV (65 MeV) clinical beams). Thus, the AcousticDenDSP system exhibits 50 kHz/350 kHz programmable center frequency (to manage different beam energy scenarios), performs a stopband noise rejection of 80 dB/decease (4th -order) and minimize phase distortion providing a maximum Time-of- Flight error lower than 0.09% (of proton beam range). The system has been designed in 28 nm CMOS, occupies an area of 0.225 mm2 and has been fully characterized at a behavioral/electrical level (after stimulation by a real proton-induced acoustic pulse). The clock frequency is 100 MHz and the power consumption estimated is 16.9 m W, with a static power contribution of 0.075 mW.

Acoustic sensing through optical transduction represents a promising alternative to the conventional capacitive sensing used in MEMS microphones, especially when aiming at ultralow-noise applications. In fact, the traditional acoustic to electrical transduction stages are decoupled by the intermediate conversion of the signal into the optical domain. As a result, the mechanical design of the sensor has no direct influence on the electrical readout performance, and this allows for a significant reduction of the MEMS transducer noise through aggressive acoustically semi-transparent stator designs that represent one of the limits of the standard capacitive technologies. This article reports the design and the modeling of the sensing elements of a MEMS optical microphone. The basic transduction mechanism is presented, and the main design parameters and challenges are explained and analyzed with advanced modeling techniques; the measurement results are finally compared to the expected performance.

The market and the applications of micro-electromechanical systems (MEMS)-based microphones have been in continuous growth over the last decades. This article presents a promising acoustic-sensing technology that mixes the consolidated MEMS technology with an innovative optical transduction technique of acoustic signals. The proposed method allows to significantly reduce the intrinsic noise of the system and to increase its signal-to-noise ratio (SNR). The designed digital optical microphone reaches an SNR of 71.6 dBA in a 5 x 5 x 2 mm (3) package with an output sensitivity of - 21 dBFS/Pa. This article describes each section of the system-in-package (SiP) microphone, starting from the physics behind the transduction mechanism, covering the application-specified integrated circuit (ASIC) and package design, and the optical stack structure. A final analysis of the obtained experimental results is provided and compared with the state-of-art reported in the literature.

In this paper, a Supply Embedded Communication (SEC) transceiver for automotive networks is proposed. In an SEC approach, power supply and communication take place on the same differential bus and thus the number of required cables is drastically reduced, leading to space, raw material consumption, and cost advantages. The proposed transceiver is realized in 180nm SOI CMOS technology and is capable of implementing 2Mbps high-speed networks. In addition to proving nominal transient operation, some critical aspects for an automotive application are analyzed. Electromagnetic compatibility (EMC) is evaluated by conducting emission tests, and finally, the robustness to external disturbances is tested by direct power injection (DPI) tests.

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This paper presents a fully integrated 55nm CMOS Voltage Reference Generator for audio interface. The reference is made up of a Bandgap voltage reference and a Low-Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. For BG, current consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 70ppm/°C. The LDO has a PSR of around -70dB in the audio band ([20, 20K]Hz) and a current consumption of around 10uA and 5uA for Normal Mode and Low Power mode respectively.

A low dropout regulator (LDO) is designed in 55nm CMOS technology. It is targeted for high-end audio applications, which present continuous-time as well as switched-capacitor building blocks. A multiple loop capacitor-less structure is pro- posed to cope with both high power supply rejection ratio (PSRR) and fast transient response. In particular, a folded flipped voltage follower (FFVF) output buffer presents a fast inner loop, needed to detach the error amplifier (EA) from the load capacitor (CL) and drive this latter under fast transients. A variable resistance and adaptive biasing are developed to guarantee stability under all load conditions, including IL = 0. Moreover, a slower high- gain loop is designed to set the output potential Vout, further reducing the output impedance and improving the PSRR, line and load regulation. The proposed LDO is implemented using IO high threshold transistors and provides an output voltage Vout = 1 V from a 1.2 V 10% supply with a minimum possible dropout (V min drop ) of 80 mV. It achieves a worst-case low-frequency PSRR of -76.2 dB under Montecarlo simulations (MC) and a recovery time of 142 ns when a load spike of 800 ?A is applied. Line and load regulation are 0.001 mV/V and 0.007 mV/mA. Moreover, the quiescent current (Iq ) is less than 20 ?A at maximum IL. © 2024 IEEE.

I sensori basati su sistemi Micro Elettromeccanici (MEMS) sono oggigiorno la soluzione piu usata per costruire microfoni a bassa potenza, occupando area ridotta e dimostrando performance di alto livello. L’integrazione di diversi microfoni MEMS su dispositive smart portatili é necesaria per ottenere alta qualitá di suono e questo impone di scalare il package del microfono, il che é ottenuto sia minimizzando il sensore, sia scalando l’area dell’elettronica di readout. Le soluzioni circuitali attuali per costruire il readout di sensori audio usano tecniche come il Chopping, per ridurre il rumore Flicker che é fortemente presente in applicazioni a bassa frequenza come i sistemi audio, o amplificatori a transconduttanza, che possono raggiungere alti guadagni e alta linearitá a spese di incrementare area e consumo di potenza. In questa tesi vengono presentate diverse soluzioni di design per costruire amplificatori di circuiti di reaodut per interfacce di microfoni MEMS. I design sfruttano una tecnologia scalata CMOS a 55nm, che rappresenta un buon compromesso tra costi di produzione e riduzione di area ottenibile. Le topologie circuitali presentate nella tesi sono due: il Super Source Follower (SSF), in due diverse versioni, una con dispositivo di ingresso PMOS e una con dispositivo di ingresso NMOS, e il Differential Difference Amplifier (DDA). La prima topologia (SSF) é la naturale evoluzione della topologia piu semplice per implementare un readout a carica costante per microfoni capacitivi. La seconda topologia (DDA) aggiunge complessitá al sistema, ma permette di ottenere corrente ridotta e programmabilitá di guadagno, nonostante la linearitá e il livello di rumore ne risentano e debbano affrontare un’ulteriore ottimizzazione per avere performace migliori dei prodotti attuali. Entrambe le soluzioni circuitali presentate in questo lavoro offrono un considerevole vantaggio in termini di area e potenza e risultano essere competitive in termini di performance ri, Micro Electro-Mechanical Systems (MEMS) sensors are nowadays the main solution to build low-power microphones, occupying reduced area though featuring high-level performances. The integration of multiple MEMS microphones on portable smart devices is needed to obtain high sound quality, and this imposes the scaling of microphone package, achieved through both minimizing the sensor and scaling the readout electronics area. Current circuital solutions for audio sensors readout mainly employ switched circuits, to implement techniques such as Chopping, to reduce low frequency flicker noise strongly affecting low frequency applications such as audio systems, or transconductance amplifiers, which can reach high gain and linearity, at the expenses of increased area and power consumption. In this thesis different design solutions to build up sensor interface amplifiers for MEMS microphone readout circuits are explored. The designs exploit a scaled technology 55nm technology node, which represents a fair trade-off between production costs and achievable area reduction. The here presented topologies are two: the Super Source Follower (SSF), in both PMOS and NMOS input device versions, and the Differential Difference Amplifier (DDA). The first circuits (SSFs) are the natural evolution of the most fundamental circuital topology through which it is possible to implement constant charge readout method for capacitive microphone. The second topology (DDA) adds complexity and elegance to the whole microphone system, achieving low current consumption and versatile gain programmability, although linearity and noise have still to face a thorough optimization to perform beyond current products. However, both circuital solutions reported in this work offer considerable area and power advantages, and results to be competitive in terms of performance with respect to current solutions, although exploiting a deep sub-micron technology node as the 55nm could result disadvantageous for the desi

The adoption of convolutional neural network algorithms requires an increasing number of multiply-and-accumulate operations. Compute-in-memory leverages the spatial arrangement of static random access memory (SRAM) cells to increase parallelism and reduce power consumption, overcoming repeated data access and movement from the memory to the computing unit in von Neumann architectures.In the proposed work, an SRAM cell with six transistors is described, explaining how the multiply-and-accumulate operation is performed and how its architecture is suitable for compute-in-memory. As multiple SRAM cells are accessed at the same time, the importance of static noise margin is discussed in the read and hold operations and the 8T Single-Ended SRAM cell presented to overcome read-disturbance issues.The SRAM cells are designed in 16 nm FinFET CMOS process and simulated to calculate the hold and read static noise margins in the nominal and PVT corners. Specifically, the 6T SRAM cell exhibits nominal hold and read static noise margin values of 355.8 mV and 188.0 mV respectively. The 8T Single-Ended SRAM cell has equivalent nominal hold and read static noise margin values of 354.6 mV, overcoming read disturbance and being a feasible candidate for reliable compute-in-memory arrays.

Poeta, scrittore e critico teatrale, Roberto Rebora (1910-1992) è stato una delle voci più pure e isolate del Novecento italiano. A trent’anni dalla morte, questo volume collettaneo ne ricostruisce la figura, portandolo oltre l’etichetta di autore della Linea lombarda cui nel 1952 l’aveva ascritto Luciano Anceschi. Accanto all’attività di poeta, si esaminano di Rebora le traduzioni, gli scritti teatrali e le prose memoriali, generate dall’esperienza di internato nei lager nazisti, dopo il rifiuto di aderire alla Repubblica di Salò. Gli studi qui raccolti, che si valgono anche di materiali manoscritti e inediti, fanno seguito alla prima giornata di studi a lui dedicata, promossa dal Centro di ricerca “Letteratura e cultura dell’Italia unita Francesco Mattesini” e dall’Archivio della letteratura cattolica e degli scrittori in ricerca, dove dal 2018 è costituito il Fondo Roberto Rebora.

Provides society information that may include news, reviews or technical notes that should be of interest to practitioners and researchers.

Optical microphones represent a promising alternative to the conventional capacitive MEMS microphones, especially when aiming at ultra-low noise applications. This paper reports the design and development of a SiP (System-in-Package) digital optical microphone with 71.6dBA SNR in 5×5×2mm3 package with output sensitivity of -21dBFS/Pa. The system concept is introduced, the design and modeling of the main blocks are presented and the measured results are analyzed.

In recent years, the topic of motor inverterization has become increasingly popular as it offers numerous benefits in terms of energy efficiency and control. Central to this topic is the development of gate drivers, which are critical components in controlling the switching of power devices in the inverter-leg. The introduction of high voltage integrated circuits (HVICs) has greatly simplified the inverter system, but has also brought in new challenges in terms of communication between different voltage domains, each isolated from each other up to several hundreds volts. In this paper, the characterization of an integrated high voltage capacitance in silicon-on-insulator (SOI) technology placed between two voltage domains is presented, allowing for a bilateral form of communication at the cost of withstanding high voltage at its terminals. The measurement of this element required a dedicated circuital structure, and the value of the capacitance was measured to be around 127 fF and its breakdown voltage at around 1800 V.

This book is based on the 18 tutorials presented during the 30th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, with specific contributions focusing on analog circuits for machine learning, current/voltage/temperature sensors, and high-speed communication via wireless, wireline, or optical links. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µVRMS of noise power and 50 µVRMS of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µVRMS) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain.

A 130-nm CMOS high-side current sensor (CS) for peak-current dc-dc converters, operating with an input voltage up to 40 V is presented. A loop prebiasing technique is used to prevent the proposed sense-FET-based CS from losing its linear behavior, thus achieving fast response time and, hence, allowing operation of the dc-dc converter with short minimum on-time. The proposed circuit also exploits a feedback resistance emulation technique for preventing the feedback loop to open during the blanking time. The CS has been integrated within a complete 40-V peak-current dc-dc buck converter that achieves 1-mV/A load regulation and 0.1-mV/V line regulation performances, even with a minimum on-time of 51 ns, with a peak efficiency of 92.5%.

A 4-channel front-end electronics chip in 65 nm CMOS technology (ASD65 nm) for muon drift tube chambers at high background counting rates in the ATLAS detector at High-Luminosity LHC and in future high-energy collider experiments is presented. Each channel of the ASD65 nm chip is a mixed-signal processing circuit consisting of a Charge Sensitive Preamplifier (CSP), a two-stage shaper, and a timing discriminator. The CSP exhibits a peaking time of 11 ns and a sensitivity of 1.1 mV/fC. The peaking time of the full analog chain is 14.6 ns. The minimum signal-to-noise ratio of the channel is 15 dB for the minimum input charge of 5 fC, and it rises to 40.5 dB for the maximum input charge of 100 fC. At the output, the time representation of input signal is provided in both, CMOS level as well as low-voltage-differential-signal. Each channel consumes a current of 10.6 mA from a single 1.2 V supply, and occupies an area of 0.235 mm2. The specified performance parameters of the ASD65 nm have been achieved for 60 pF parasitic capacitance of the detector connected the input terminal.

A 4-channel front-end electronics (4 × FEE) system for the muon drift tube in the ATLAS detector in the High-Luminosity LHC is presented. The overall channel architecture is optimized to reduce the power and area of the design. Each channel comprises a charge-sensitive preamplifier (CSP), shaper, discriminator and differential low-voltage signaling drivers. The proposed channel operates with a 5–100 fC input charge and exhibits a linear sensitivity of 8 mV/fC for the entire input charge range. The peaking time delay of the analog channel is 14.6 ns. At the output, the time representation of the input signal is provided in terms of the CMOS level and in scalable low-voltage signal (SLVS). The FEE consumes a current of 10.6 mA per channel from a single 1.2 V supply voltage. The full 4 × FEE design is realized in TSMC 65 nm CMOS technology and its die-area is 2 mm × 2 mm.

Proton Sound Detectors (ProSDs) sense (at low latency, <1 ms) the thermoacoustic signal generated by the fast energy deposition at the Bragg peak of a proton beam penetrating an energy absorber. ProSDs are especially promising for experimental monitoring of high pulse rate (FLASH) hadron therapy treatments working in-sync with the beam. This paper presents a mixed signal detector, capable of sensing and processing high rate (1k beam shots/sec) ionacoustic signals with low latency (<1 ms). The system was validated by measuring the dose deposition of a 20 MeV proton beam in water, achieving 3.43% precision (±2.75 GyRMS) after 50 ms acquisition (77.56 Gy total dose deposition).

Microelectrode-Arrays (MEAs) allow neural recording of thousands of neurons/mm2 by sensing: Extracellular Action Potentials (EAP) and Local Field Potentials (LFP). MEAs arrange several recording sites (or pixels) in a spatial grid/matrix, planarly and capacitively coupled with in-vitro cell cultures (growth above the chip surface) and/or integrated in electrocorticography grids. This paper focuses on Electrolyte-Oxide (C)MOS Field-Effect-Transistors MEAs for cell-level recording. In this type of biosensors, each single row of the matrix is composed of N planar metal electrodes and is scanned synchronously and regularly for N clock cycles, adopting Time-Division-Multiplexing (TDM) schemes. TDM approach generates an analogue output signal for each biosensor row, which includes in a single time track the information acquired by the N electrodes of the matrix. It is therefore of fundamental importance to estimate the noise power of the output signal of the single row because this power defines the minimum detectable threshold of the neuro-potential signal power. Noise in planar MEA is determined by the classical contributions of electronic noise (thermal and flicker, coming from both biological environment and semiconductor devices) and from the spurious corrupting signal due to multiplexing action (which behaves to all effects as a statistical noise signal following a Gaussian probability distribution). This paper presents the complete procedure for designing an (active) biosensor matrix/array (embedding the analog signal processing channels) as a function of a specific Noise Figure requirement (that measures the Signal-to-Noise-Ratio (SNR) degradation and thus is defined as the ratio between the biosensor array input SNR and the output SNR of the analog acquisition channel). This procedure is applied to a single row of the biosensor matrix, can be easily extended to 2D array, and allows to define all the design parameters (including electrode area, gain, bandwidth and

This work presents the development and experimental validation of an ultrasound piezoelectric sensor for thermoacoustic imaging that exploits printed circuit boards technology to define with high precision the sensor active area while minimizing manufacturing complexity and cost. A prototype single-channel sensor with 4x4 mm active area has been manufactured and experimentally validated in electrical and acoustic testbenches.

In this paper an optimisation procedure based on a Behavioural model (developed in MATLAB and Simulink) of a current limiter circuit is presented. Through the behavioural environment a coarse design optimisation is performed, while fine optimisation is later performed at transistor level. The proposed approach reduces design time compared to a full transistor level design procedure. Once the behavioural model reliably fits the transistor level behavior, any optimisation algorithm can be used in the MATLAB environment to adjust behavioural model parameters. The Current limiter case adopted as benchmark in this work demonstrates how control-loop stability can be improved through the parametric study of the loop frequency response and can be optimized by the insertion of an additional zero in the circuit transfer function.

Proton sound detectors rely on sensing the weak thermoacoustic signals emitted by the fast energy deposition at the end of the beam penetration path through the energy absorber. The energy of the ions/protons is first converted into heat, and then, into pressure by a thermodynamic process. The pressure signal propagates through the energy absorber, and it is read by an acoustic sensor, which, in turn, converts the pressure wave into an analog electrical voltage. Such an analog signal is digitalized by the analog front-end. Its digital representation is used for the measurement of the beam depth. This emerging technique attracts attention in both physics experiments and medical applications (hadron therapy). This article investigates the signal-to-noise-ratio performance in proton sound detectors exploring all critical steps that lead to both reduction of the power of the electrical signal and noise power increasing. Nonetheless, this article proposes specific technical solutions to mitigate such signal-to-noise-ratio degradations with particular attention to higher energy (i.e., 200 MeV) proton beams, which are crucial for medical applications, and where the maximum achievable signal-to-noise ratio can be 50/60 dB lower than 20 MeV acoustic pulses.

This article presents a cross-domain model that defines and sets the acoustic signal generation process due to the fast dose deposition induced by a proton beam penetrating an energy absorber. The proposed model reduces the complex iono-acoustic energy transformation process to a simple impulse-response of a linear-time-invariant (LTI) system and is validated by comparing LTI output simulation results (in both time and frequency domain) with experimental acoustic signals emitted by a physical proton beam at 20 MeV and 70-120-ns pulse time width. Thanks to the intrinsic simplicity of the system, it is possible to predict and estimate the effective acoustic power at the sensor and the resultant beam range measurement precision. More importantly, the information coming from LTI simulations provides well-defined methodologies that allow to increase acoustic signal amplitude from +3 up to +9 dB and to improve the measurement precision of the beam range localization (up to +/ - 0.3 mm versus +/ - 0.6 mm state of the art for 200-MeV energy and 75-mGy total dose).

An on-chip solution for health monitoring of semiconductor power switches subjected to thermo-mechanical metal fatigue degradation is proposed. The fatigue detection relies on the correlation between the progress of the main failure mechanism, which is critical to the functionality of the device, and a parallel degradation of a non-critical sensing structure using a different mechanism. Both mechanisms are driven by the same cyclic thermo-mechanical load. This study specifically develops a sensing structure for detecting power metallization aging through electrically detectable ratcheting behavior in the routing metal layer underneath. Experiments have been carried out on a dedicated test structure with electrical sensing of the health monitoring structure. Meanwhile, the main degradation progress was observed via scanning electron microscopy in regular intervals. Results show that the proposed approach will reliably work only for detecting degradation driven by repeated high overload events.

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO2) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers.

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps.

Acoustic sensing through optical transduction represents a promising alternative to the conventional capacitive sensing used in MEMS microphones, especially when aiming at ultra-low noise (i.e. high DR) applications. This paper reports the design and the modeling of the sensing elements of a MEMS optical microphone. The basic transduction mechanism is presented and the main design parameters and challenges are explained and analyzed with advanced modeling techniques.

This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of {G} order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing 7.8 {V}_{RMS and 8.8mu {V}_{RMS input-referred noise power at 1 Hz - 300 Hz (Local Field Potential) and 300 Hz-5 kHz (Action Potentials) bandwidth, respectively. The device consumes 2.4 {W} power and has been designed in 28 nm CMOS technology.

This work presents the design and experimental validation of a low-noise amplifier based on a ultra-low-noise JFET for noise characterization of materials samples for neural interfaces. The JFET LNA amplifies the sample noise power by 46 dB well above a lock-in amplifier noise floor, used as spectrum analyzer for noise characterization. The LNA exploits the high gm and low flicker corner frequency of JFETs to achieve 0.15 dB noise figure. The JFET LNA has been characterized in terms of frequency response and noise power spectrum and experimentally validated by characterizing the noise spectrum of a platinum silicide (PtSi) sample.

Negli ultimi tre decenni l'elettronica delle telecomunicazioni mobili ha subito un grande miglioramento, questo ramo dell'elettronica si è rivelato una delle principali forze trainanti nello sviluppo delle nuove tecnologie CMOS. in tutto il mondo richiedono dispositivi portatili estremamente performanti, più veloci, più affidabili, a basso consumo energetico. Questa situazione è diventata estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni in grado di raggiungere velocità e capacità di memoria prima incredibili. Anche i blocchi di costruzione analogici devono essere integrati in nodi profondamente ridimensionati, al fine di adattarsi ai circuiti integrati digitali . Il primo compito di questo lavoro di tesi è stata l'implementazione e la misurazione di diversi circuiti integrati in due nodi tecnologici profondamente scalati come CMOS bulk a 28 nm e FinFET (Fin Field Effect Transistor) a 16 nm. In particolare, il secondo di questi introduce novità sulla struttura del transistor utilizzato per implementare i circuiti. Ciascun circuito realizzato incontra diverse difficoltà dovute al particolare comportamento di tali tecnologie avanzate, in particolare in termini di basso intrinsic gain e basso output voltage swing come conseguenza della bassa tensione di alimentazione. Ho lavorato nel progetto FinFET16 con il compito principale di realizzare e validare il layout di un filtro analogico Super-Source-Follower fully-differential del 4° ordine. Dopo le misurazioni, il filtro raggiunge 15,1 dBm IIP3 in banda a 10 MHz e toni di ingresso 11 MHz, con un consumo energetico di 968 µW da una singola tensione di alimentazione da 1 V. Il rumore integrato in banda è 85,78 µVrms per una figura di merito complessiva di 162,8 dB (j-1) che supera lo stato dell'arte dei filtri analogici. Ho anche collaborato come layoutista in altri due progetti realizzati con tecnologia CMOS a 28 nm. Il primo è stato il progetto PRIN Brain28nm che riguarda l'implementazio, In the last three decades Mobile Telecommunication (TLC) electronics has undergone a great improvement, this limited branch of electronics proved to be one of the major driving motor in the development of the new Complementary Metal-Oxide-Semiconductor (CMOS) technologies. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. This situation has become extremely favorable for the development of high performance digital devices which are able to reach speed and memory capability previously unbelievable. Also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital integrated circuits (ICs). First task of this thesis work was the implementation and measurement of different integrated circuits in two deep sub-micron technology nodes as 28nm bulk-CMOS and 16nm FinFET (Fin Field Effect Transistor). In particular the second one of these introduces novelty about the structure of transistor used to implement the circuits. Each circuit created faces various difficulties due to the particular behaviour of such advanced technologies, in particular in terms of low intrinsic gain and limited signal swing as consequence of low supply voltage. I worked in FinFET16 project with the main task to realize and validate the layout of a 4^th Order Fully-Differential Super-Source-Follower Analog Filter. After measurements the filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with 968 µW power consumption from a single 1V supply voltage. In-band integrated noise is 85.78 µVrms for an overall Figure-of-Merit of 162.8 dB (j-1) which outperforms analog filters State-of-the-Art. I also collaborated as layoutist in other two projects realized with 28nm CMOS technology. The first one was the PRIN Brain28nm project that concerns the implementation of a neural signal acquisition chain. The goal of this work was the realization of a bi

Audio sensors systems scaling leads to microphone interfaces built in deep sub-micron technologies, which introduces critical aspects in high performance analog cells design. In this paper a Cascode Flipped Voltage Follower interface for Micro Electro-Mechanical System (MEMS) silicon microphones is presented. The pseudo-differential interface architecture suits differential microphones, gaining in linearity performance due to symmetry properties of the system. The device is based on the cascode flipped voltage follower, which allows minimizing chip area and power consumption, while enhancing noise and distortion. A prototype in 55nm CMOS features an A-weighted output integrated noise in audio frequency range of -112 dBV(A) and an Acoustic Overload Point (AOP) of 133dBspl. Power consumption is lower than 225µW from a 1.5 V voltage supply.

The overexpression of aberrantly glycosylated tumor-associated mucin-1 (TA-MUC1) in human cancers makes it a major target for the development of anticancer vaccines derived from synthetic MUC1-(glyco) peptide antigens. However, glycopeptide-based subunit vaccines are weakly immunogenic, requiring adjuvants and/or additional immunopotentiating approaches to generate optimal immune responses. Among these strategies, unimolecular self-adjuvanting vaccine constructs that do not need coadministration of adjuvants or conjugation to carrier proteins emerge as a promising but still underexploited approach. Herein, we report the design, synthesis, immune-evaluation in mice, and NMR studies of new, self-adjuvanting and self-assembling vaccines based on our QS-21-derived minimal adjuvant platform covalently linked to TA-MUC1-(glyco)peptide antigens and a peptide helper T-cell epitope. We have developed a modular, chemoselective strategy that harnesses two distal attachment points on the saponin adjuvant to conjugate the respective components in unprotected form and high yields via orthogonal ligations. In mice, only tri-component candidates but not unconjugated or di- component combinations induced significant TA-MUC1-specific IgG antibodies able to recognize the TA-MUC1 on cancer cells. NMR studies revealed the formation of self-assembled aggregates, in which the more hydrophilic TA-MUC1 moiety gets exposed to the solvent, favoring B-cell recognition. While dilution of the di-component saponin–(Tn)MUC1 constructs resulted in partial aggregate disruption, this was not observed for the more stably-organized tri-component candidates. This higher structural stability in solution correlates with their increased immunogenicity and suggests a longer half-life of the construct in physiological media, which together with the enhanced antigen multivalent presentation enabled by the particulate self-assembly, points to this self-adjuvanting tri-component vaccine as a promising synthetic

In recent years, in the automotive sector, devices that need a regulated DC supply voltage have increased. DCDC switching converters are the best solution in terms of performance, cost, and efficiency. Among DCDC converters, the Step-Down switching converter (or Buck converter) is very important. The high number of these devices installed on a car requires the reduction of the cost for the system, with a very simple implementation, but maintaining comparable performances with a more complex and expensive design. In this article, an Asynchronous Constant TOFF Peak Current Mode Controlled (PCMC) Buck converter, with a maximum output current of 10A, is presented. Thanks to this type of Pulse Frequency Modulation (PFM) control and an integrated high-side current sensing, it is possible to realize an efficient system with over-current protection, duty cycle greater than 50%, without slope compensations, and high efficiency also at low loads. The implementation of the integrated current sense, the high switching frequency and the high stability of constant TOFF reduce at the minimum the number of external components and the used area for IC to lower the price of the buck converter system. The Quasi-Constant switching frequency allows using a cheapest filter for automotive EMI tests. The system works with a switching frequency around 1MHz with a precise output voltage from 1. 8V to 5V with an output current up to 10A.

Crescente domanda di rivelatori ad alta velocità nella moderna fisica delle alte energie esperimenti sta generando molte sfide tecnologiche. In particolare, i rivelatori di particelle utilizzati negli esperimenti di fisica delle alte energie richiedono sistemi elettronici di lettura efficienti in grado di far fronte alle sfide affrontate a causa dell'aggiornamento negli esperimenti di fisica delle alte energie. I circuiti integrati CMOS, tecnologia ampiamente utilizzata, sono una scelta comune per i chip di lettura basati su fattori di affidabilità, riduzione dei costi e miglioramento delle prestazioni. In questa tesi, vengono presentate informazioni generali sull'esperimento insieme alle sfide imminenti dovute all'aggiornamento previsto nell'esperimento e un nuovo sistema elettronico di lettura, mirato a una notevole efficienza energetica, è un design efficiente, con prestazioni promettenti mirate a sostituire l'esistente viene presentata l'elettronica di lettura. L'elettronica front-end è composta da quattro canali simmetrici in cui ogni canale è una struttura di segnali misti. L'architettura del canale è ottimizzata per ridurre la potenza e l'area del design. Ciascun canale comprende un preamplificatore sensibile alla carica, uno shaper per implementare lo schema di sagomatura bipolare, un discriminatore e driver di segnalazione differenziale a bassa tensione. Il canale proposto funziona con una carica di ingresso di 5–100 fC e mostra una sensibilità lineare di 8 mV/fC per l'intero intervallo di carica di ingresso. Il ritardo di picco del canale analogico è di 14,6 ns. All'uscita, la rappresentazione temporale del segnale di ingresso è fornita in termini di livello CMOS e in segnale a bassa tensione scalabile (SLVS). Il consumo energetico di ciascun canale è di 12,8 mW, ovvero il 61,2% in meno rispetto al modello precedente. Ciascun canale occupa un'area di 0,235 mm2, ovvero solo il 58,75% del design precedente. Il design completo dell'elettronica front, Increasing demand for high-rate detectors in modern High Energy Physics experiments is generating many technological challenges. Particularly, the particle detectors utilized in High Energy Physics experiments requires efficient readout electronics systems that can cope with the challenges faced due to the upgrade in High Energy Physics experiments. CMOS integrated circuits, widely used technology, is a common choice for readout chip based on reliability, cost reduction and performance improvement factors. In this thesis, a general information of the experiment along with the upcoming challenges due to expected upgrade in the experiment are presented and a new readout electronic system, targeting a significantly power efficient, are efficient design, with a promising performance targetting to replace the existing readout electronics is presented. Front end electrinics is composed of four symmetrical channels where each channel is a mixed signal structure. The channel architecture is optimized to reduce the power and area of the design. Each channel comprises a charge-sensitive preamplifier , shaper to implement the bipolar shaping scheme, discriminator and differential low-voltage signaling drivers. The proposed channel operates with a 5–100 fC input charge and exhibits a linear sensitivity of 8 mV/fC for the entire input charge range. The peaking time delay of the analog channel is 14.6 ns. At the output, the time representation of the input signal is provided in terms of the CMOS level and in scalable low-voltage signal (SLVS). The power consumption of each channel is 12.8 mW, which is 61.2 percent lower than in the previous design. Each channel occupies an area of 0.235 mm.sq, which is only 58.75 percent of the previous design. The full 4 channel Front end electronics design is realized in TSMC 65 nm CMOS technology and its die-area is 2 mm by 2 mm. The first part of this thesis presents the LHC experiment information and the classical readout electronics, fabric

Il presente lavoro e’ stato svolto in cooperation tra l’infineon e l’Universita’ Milano Bicocca, l’obbiettivo e’ sviluppare il cuore di un convertitore DC-DC Buck Converter ad alta frequenza di commutazione. I convertitori a commutazione offrono un modo semplice ed efficiente per alimentare carichi elettronici. Inoltre, gli alimentatori DC-DC consentono di soddisfare efficacemente molti requisiti di sicurezza delle automobili moderne. Ad esempio è assolutamente necessario che le luci di emergenza, i fari e le luci dei freni mantengano la loro funzionalità in tutte le condizioni, soprattutto durante l'avviamento a freddo, quando la tensione della batteria raggiunge valori molto bassi (anche 4V). Ma in certe condizioni esperimentano tensioni anche superiori ai 30V. Gli alimentatori DC-DC ben si adattano ad ampie e repentine variazioni della tensione di alimentazione, inoltre alla loro relativa semplicità uniscono un’alta efficienza, valori superiori al 90%. Aumentando la frequenza di commutazione si riducono linearmente le dimensioni dei componenti reattivi, permettendo schede PCB più piccole e conseguentemente costi ridotti. Le tecnologie BCD consentono di integrare su un singolo chip (SOC - System On Chip) transistor di potenza, logica di controllo e diagnostica. In questa ricerca sono stati sviluppati tre convertitori Buck che lavorano a tre diverse frequenze 1MHz, 4MHz e 10MHz con una corrente di uscita di 3A. Tra i Buck converter disponibili sul mercato solo quelli più performanti hanno frequenze di commutazione di 2,0-2,5 MHz e correnti nel carico di 2-2,5 A. Poiché l'obiettivo di 10MHz con una corrente di carico di 3A è molto aggressivo, è stata adottata un'architettura del convertitore Buck che minimizza il tempo di transizione dei segnali elettrici ed è stato necessario sviluppare una nuova topologia di driver molto più veloce e potente delle soluzioni adottate finora (patent pending). Al momento in cui scriviamo, i dispositivi da 1 MHz e 4 MHz sono, This work was carried out in cooperation between Infineon and the University of Milan Bicocca, the aim being to develop the core of a DC-DC Buck Converter with a high switching frequency. Switching converters offer a simple and efficient way to power electronic loads. In addition, DC-DC power supplies make it possible to effectively meet many safety requirements of modern automobiles. For example, it is absolutely necessary that emergency lights, headlights and brake lights maintain their functionality under all conditions, especially during cold starting, when the battery voltage reaches very low values (even 4V). But under certain conditions they experience voltages even above 30V. DC-DC power supplies are well suited to large and sudden variations in supply voltage, and in addition to their relative simplicity they combine high efficiency, values of over 90%. Increasing the switching frequency reduces the size of reactive components linearly, allowing smaller PCBs and consequently lower costs. BCD technologies allow power transistors, control logic and diagnostics to be integrated on a single chip (SOC - System On Chip). In this research, three Buck converters were developed that operate at three different frequencies 1MHz, 4MHz and 10MHz with an output current of 3A. Of the buck converters available on the market, only the best performing ones have switching frequencies of 2.0-2.5MHz and load currents of 2-2.5A. Since the target of 10MHz with a load current of 3A is very aggressive, a Buck converter architecture was adopted that minimises the transition time of electrical signals, and a new driver topology had to be developed that is much faster and more powerful than the solutions adopted so far (patent pending). At the time of writing, 1 MHz and 4 MHz devices are being deployed. The wafers are scheduled for release in February 2023. The third Buck converter (10 MHz) is pending deployment. Four patent proposals were submitted during this doctoral work.

In questa tesi, sono state realizzate tre diverse board: un DC-DC per il supply, un control unit per programmare i segnali d'ingresso del driver, un firing unit che contiene il chip principale(driver e GaN). Abbiamo usato il nitruro di galio perché è meglio adatto del silicio ad alte frequenze. L'obbiettivo principale è di raggiungere 50A di picco di corrente con soli 5ns di pulse. Sono stati usati Altium design per il disegno delle board e Ansys per l'evaluazione delle induttanze parassite. Questo ultimo crea diversi problemi e può limitare il raggiungimento del picco di corrente. Quindi bisogna fare il layout tenendo molta attenzione ai parassiti, In our three years of work, we have achieved the realization of a Firing unit board with the GaN and driver in a system in package. Three different boards were realized: A first board with only the resistor, the second one with the resistor and a shunt resistor and a third board with the laser diode and a shunt resistor. A DC-DC was realized for the supply while a control unit was realized for the control of the input signals of the driver.Unfortunately, no measurements of the firing unit have been done yet as we are still waiting for the chip to be completed. The DC-DC and the control unit board have been measured and tested. LIDAR application is the most attractive and efficient solution for this market. The challenges of LIDAR application consist in the development of the electronics generating a current pulse of 50A that lasts for less than 5ns. The technical area of this activity is fully autonomous self-driving car, and in particular what helps an autonomous vehicle to understand the world around it.

Le ultime novita in ambito automotive sono dovute principalmente ai compoenenti elettronici ed elettrici che favoriscono la riduzione dei livelli di emissione e creano maggiore sicurezza e comfort. L’utilizzo di questi componenti sta aumentando sempre di più, ed essendo generalmente connessi tramite dei bus, stanno rendendo il sistema di cablaggio sempre piu complesso fino a renderlo uno dei blocchi piu critici da progettare. Pertanto, si stanno cercando nuove tecniche per ridurre il numero di interconnessioni. In questo lavoro si analizza un nuovo metodo per integrare la comunicazione e l'alimentazione su un unico bus differenziale. Diversamente dai metodi Power over Ethernet (PoE), l'implementazione proposta si basa sull’iniezione di cariche ben definite sul bus di comunicazione, che allo stesso tempo alimenta i vari dispositivi, al fine di generare dei pulsi. Sono proposti due approcci basati su capacità di commutazione: il Charge Alternation (CA) e il Charge Pump (CP). Il metodo CA, a 2Mbps, richiede solo il 50% della potenza di modulazione del carico resistivo, e il CP migliora ancora di più le prestazioni grazie alla capacità di riutilizzare parzialmente la carica immagazinata. Entrambe i circuiti di transmissione sono validati da una scheda dimostrativa e da un test chip in tecnologia 180nm BCD-on-SOI da cui si sono ottenuti risultati eccellenti. Inoltre, un circuito di ricezione é mostrato ed implementato in un test chip che quindi realizza un ricetrasmettitore completo. La tesi é organizzata come segue: l'introduzione e le motivazioni alla base di questa attivitá sono mostrate nel Capitolo 1. Nel capitolo 2 sono analizzati il concetto basico di transmissione e la modellazione del bus differenziale. Il Capitolo 3 sono esaminate entrambe le implementazioni di trasmettitori proposti, andando nel dettaglio della caratteristica dei pulsi, della codifica e del consumo energetico. Una scheda dimostrativa fatta di componenti discreti e i relativi test sono p, The advancements in modern vehicles are mainly due to electrical and electronic components that support an increasing demand for lower emission levels, higher safety and comfort. Increasingly, these components are connected by bus systems, which lead to more complex wire harnesses in modern cars, than ever before. Because of this, the wire harness of a car became one of the most complex building blocks. Therefore, techniques to reduce the wiring overhead are becoming increasingly important. In this work, a new method for integrating the communication and power supply of network participants on one differential bus, is investigated. Different to methods such as Power over Ethernet (PoE), the proposed implementations are using charges to emit defined pulses in to the communication bus, that is also carrying the power supply. Two switched capacitor approaches are proposed, the charge alternation (CA) and the charge pump (CP) method. While the suggested CA mode, operating at 2, requires only 50% of the power of a resistive load modulation that reaches a comparable signal level, the CP mode improves this even further due to the inherent charge-reuse capability of the concept. The approaches are verified with a demonstrator and a transmitter test chip fabricated in a 180nm BCD-on-SOI technology, that both shows the excellent performance of the concept and the silicon implementation. Furthermore, the receiver is discussed and implemented as part of a transceiver test chip, fabricated in the same technology. The reminder of the work is organized as follows: After the introduction and motivation for this research project in chapter 1, basic transmission concepts are described as well as the modelling of the differential bus based on a twisted pair, is analysed in chapter 2. Chapter 3 examines both switched capacitor transmission concepts in detail, regarding pulse shape, encoding, and power consumption. To check the proposed transmission schemes in a real-world environment

Negli ultimi anni si è assistito ad un sensazionale aumento della presenza di sistemi e sensori elettronici all'interno delle automobili, che ha portato il sistema di interconnessioni ad essere uno degli aspetti maggiormenti critici e degni di attenzione durante le fasi di progettazione. E' divenuto quindi necessario studiare nuovi metodi di comunicazione al fine di gestire al meglio tale livello di complessità e favorire lo sviluppo dell'automobile del futuro. Nell'ambito di questa attività di ricerca, è stata proposta la progettazione di un ricetrasmettitore Supply-Embedded Communication (SEC) con caratteristiche tali da fornire vantaggi in termini economici, in semplicità costruttiva e relativamente al peso del veicolo stesso. Infatti nel sistema Supply-Embedded Communication utilizzato, l’alimentazione è unita al bus di comunicazione, portando ad una drastica riduzione del numero d'interconnessioni. Pertanto il metodo di comunicazione proposto si pone l'obiettivo di essere un layer fisico addizionale al Controller Area Network (CAN), il bus attualmente più diffuso nell’industria automotive, permettendo il raggiungimento di una velocità di trasmissione dati di diversi Mbps. Sono stati realizzate due diverse tipologie di trasmettitori basati su capacita di commutazione, implementati in un primo test chip in tecnologia 180nm CMOS SOI. Il prototipo realizzato è stato validato da test di comunicazione svolti in laboratorio, connettendo il chip stesso con una scheda dimostrativa a componenti discreti che funge da ricevitore. Inoltre un circuito di ricezione, basato su due latch StrongArm, è stato proposto ed integrato nella seconda versione del prototipo per realizzare il ricetrasmettitore SEC completo. Paragonato alle soluzioni già disponibili sul mercato, il metodo presentato in questa tesi può raggiungere una velocità di trasmissione di 2Mbps, rendendolo in grado d'implementare reti ad alta velocità come avviene nel bus CAN. Come progetto secondario e, Automotive wire harness has become nowadays a very complex system as the number of electronic systems and sensors inside a vehicle has increased dramatically. To manage this complexity, and to support the automotive systems of tomorrow, new communication methods need to be investigated. In this research activity, a Supply-Embedded Communication (SEC) transceiver for differential automotive networks is developed to provide advantages in cost, complexity, and weight. In a Supply-Embedded Communication system, the power supply is merged on the communication bus and hence the number of interconnections is drastically reduced. The proposed approach is intended to be an effective additional physical layer to the Controller Area Network (CAN) which is the most widespread bus in the automotive industry, and hence transmission speed in the order of some Mbps is desired. Two transmitter topologies based on switching capacitors and their implementation in a first test chip in 180nm CMOS SOI technology are presented. The prototype is validated by communication tests in the laboratory connecting it to a discrete component-based demonstrator receiver board through an unshielded twisted pair cable. A receiver circuit based on StrongArm Latches is designed and integrated into the second version of the prototype to realize a full SEC transceiver. Compared to commercially available solutions, the proposed approach can reach a data transmission rate of 2Mbps making it able to implement high-speed event-driven networks, such as the CAN. As a side project, a second order curvature compensated bandgap reference circuit is proposed. Voltage references are used in almost every integrated circuit and, one of them is also present in the SEC transceiver prototype to furnish the required bias to the circuit. Although the main project is done in 180nm technology, the side project is developed in 110nm technology for educational purposes. The proposed circuit is validated by simulation in a temp

Ionoacoustic detectors sense the weak signal emitted by the fast energy deposition of a proton beam through the energy absorber and exploit this detected signal to spatially measure the beam penetration depth or range, with promising application in hadron therapy treatment monitoring. However, clinical scenarios exhibit very weak acoustic signal power (tens of mPa) in 10 kHz - 1 MHz bandwidth. Therefore, it is of fundamental importance that the front-end amplifiers operate at very low noise levels (few nV/v Hz of in-band noise power spectral density) to minimize the degradation of the Signal-to-Noise Ratio (SNR). The Low-Noise-Amplifier (LNA) proposed in this paper operates in such a critical scenario, exploiting an advanced and dc-stable pseudo-resistor implementation to minimize noise power, achieving 0.26 dB of Noise Figure. The LNA has been designed in 28 nm CMOS technology, has a passband gain of 30 dB, an integrated noise power in the ionoacoustic bandwidth of 7.5 mu V-RMS and 2.4 mW power consumption.

This paper presents an ultra-low power, area-efficient 4-channel front-end electronics for Monitored Drift Tubes (MDT) at Atlas Experiment. The proposed design is composed by low-noise Charge Sensitive Preamplffier (for charge-to-voltage conversion), a continuous-time Shaper/filter for Bipolar Time-Domain Pulses feeding a dynamic (no-clocked) Comparator (for voltage to time conversion). The system is designed to detect an input charge in the range of 5-100fC. The peaking time of Analog channel is 14.6 ns and exhibits a sensitivity of 8 mV/fC. The design has a single mode of operation, time-over-threshold (ToT). At the output the ToT encoding of input charge is provided in low-voltage differential signal, for connecting with TDC board, along with digital CMOS level signal. The design is operated from a single 1.2 V supply voltage. The chip is realized in 65 nm CMOS technology and has a total area occupancy of 4 mm2.

Reverse bandgaps generate PVT-independent reference voltages by means of the sums of pairs of currents over individual matched resistors: one (CTAT) current is proportional to VEB; the other one (PTAT) is proportional to VT (Thermal voltage). Design guidelines and techniques for a CMOS low-power reverse bandgap reference are presented and discussed in this paper. The paper explains firstly how to design the components of the bandgap branches to minimize circuit current. Secondly, error amplifier topologies are studied in order to reveal the best one, depending on the operation conditions. Finally, a low-voltage bandgap in 65 nm CMOS with 5 ppm/°C, with a DC PSR of −91 dB, with power consumption of 5.2 uW and with an area of 0.0352 mm2 developed with these techniques is presented