48 results on '"Yi KAN"'
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2. Intelligent Reflecting Surfaces and Classical Relays: Coexistence and Co-Design.
3. Evaluation Model and Method of Intelligent Level and Ability Level of Command and Control System
4. Task offloading and resource allocation in mobile-edge computing system.
5. QoS-Aware Mobile Edge Computing System: Multi-Server Multi-User Scenario.
6. Embracing the Full Power of TSMC 3DFabric™ Design: Challenges and Solutions
7. Modeling load parameters of ball mill using frequency spectral features based on Hilbert vibration decomposition.
8. Configurable analog routing methodology via technology and design constraint unification.
9. Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits.
10. A New Flexible Algorithm for Random Yield Improvement.
11. Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor.
12. An efficient method for hot-spot identification in ULSI circuits.
13. Temperature-driven power and timing analysis for CMOS ULSI circuits.
14. ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits.
15. Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.
16. iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
17. Chip-Level Thermal Simulator to Predict VLSI Chip Temperature.
18. SAR Image Recognition Based on Parallel Vision
19. Abstract GMM-047: GENOMIC CHARACTERIZATION OF ADULT-TYPE GRANULOSA CELL TUMORS: IMPLICATIONS FOR PATHOGENESIS AND TREATMENT OF RECURRENT DISEASE
20. The Research of C4ISR System Design And Modeling Method Based on Model
21. Abstract DPOC-014: BEYOND CODING MUTATIONS: USING RETROTRANSPOSONS TO PREDICT OVARIAN CANCER DEVELOPMENT
22. Position Control of BLDC Motors.
23. Survivability optimization for the networked C4ISR system structure
24. Timeliness Optimization Model For Network C4ISR System Structure Based on Information Flow
25. Configurable analog routing methodology via technology and design constraint unification
26. Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits
27. Decentralized Integration of Task Scheduling with Replica Placement
28. Integration of Task Scheduling with Replica Placement in Data Grid for Limited Disk Space of Resources
29. DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization
30. A New Flexible Algorithm for Random Yield Improvement
31. Delay metric for networked C2 information system architecture.
32. An efficient full-chip ESD paths resistance value verification flow for large scale designs.
33. Configurable analog routing methodology via technology and design constraint unification.
34. Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits.
35. Coupling- and ECP-aware metal fill for improving layout uniformity in copper CMP.
36. DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization.
37. Dynamic Level Task Scheduling Algorithm based on Risk Estimation Model in Grid Computing.
38. Hierarchical electromigration reliability diagnosis for VLSI interconnects
39. ICET
40. An efficient method for hot-spot identification in ULSI circuits.
41. Fast thermal analysis for CMOS VLSIC reliability.
42. iTEM: a chip-level electromigration reliability diagnosis tool using electrothermal timing simulation.
43. Hierarchical electromigration reliability diagnosis for VLSI interconnects.
44. ICET.
45. Intelligent switch in 42 V DC power net.
46. ETS-A.
47. A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips.
48. Improvement on chip-level electrothermal simulator-ILLIADS-T.
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