10 results on '"Yanagawa, Y."'
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2. On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer
3. Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays
4. 1-Tbyte/s 1-Gbit DRAM architecture with micro-pipelined 16-DRAM cores, 8-ns cycle array and 16-Gbit/s 3D interconnect for high throughput computing
5. Scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems
6. CMOS low-VT preamplifier for 0.5-V gigabit-DRAM arrays.
7. Designing coloration on mixed reality display
8. In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F2 DRAM array operable at 10-fF cell capacitance.
9. 1-Tbyte/s 1-Gbit DRAM architecture with micro-pipelined 16-DRAM cores, 8-ns cycle array and 16-Gbit/s 3D interconnect for high throughput computing.
10. Designing coloration on mixed reality display.
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