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In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F2 DRAM array operable at 10-fF cell capacitance.

Authors :
Yanagawa, Y.
Sekiguchi, T.
Kotabe, A.
Ono, K.
Takemura, R.
Source :
2011 Symposium on VLSI Circuits (VLSIC); 2011, p230-231, 2p
Publication Year :
2011

Details

Language :
English
ISBNs :
9781612841755
Database :
Complementary Index
Journal :
2011 Symposium on VLSI Circuits (VLSIC)
Publication Type :
Conference
Accession number :
80367447

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