19 results on '"Shamiryan, D."'
Search Results
2. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
3. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
4. The metal hard-mask approach for contact patterning
5. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
6. Effect of quartz window temperature on plasma composition during STI etch
7. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration
8. Integration challenges for multi-gate devices
9. Optimization of low-k UV Curing: Effect of Wavelength on Critical Properties of the Dielectrics.
10. Effect of quartz window temperature on plasma composition during STI etch.
11. Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below
12. Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.
13. Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON.
14. Optimization of etching and stripping chemistries for Z3MS/sup TM/ Low-k
15. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
16. Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films.
17. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions.
18. Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films
19. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.