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In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications. Categories and Subject Descriptors [Hardware] Emerging technologies - Circuit substrates General Terms Design, Performance [ABSTRACT FROM AUTHOR]

High-performance Ge nanowire transistors with single-crystalline germanides as Schottky source/drain contacts were fabricated via the solid-state reaction between a single-crystalline Ge nanowire and two Ni contact pads using rapid thermal annealing. The formed high-quality germanides show atomically clean epitaxial interface with the Ge nanowire. The effect of oxide confinement was also studied to control the growth of nickel germanides, and further to passivate the Ge nanowire surface. In addition, a room-temperature ferromagnetic germanide, Mn5Ge3, was formed in the fabrication of Mn5Ge3/Ge/Mn5Ge3 nanowire transistors using a similar approach. Temperature-dependent I–V measurements were performed to extract a Schottky barrier height of 0.25 eV for Mn5Ge3 conducting to p-Ge, which suggested promising spin injection from Mn5Ge3 into Ge nanowires. Our results open up exciting opportunities to fabricate high-performance Ge nanowire transistors and further explore spintronics applications in Ge nanowire heterostructures with high-quality epitaxial interfaces. [ABSTRACT FROM PUBLISHER]

We present a novel method for the evaluation of shot noise in quasi one-dimensional field-effect transistors, derived by means of a statistical approach within the second quantization formalism, which manages to include both the effects of Pauli exclusion and Coulomb interactions. The method has been applied to Carbon Nanotubes and Silicon Nanowire Transistors. We show that noise can significantly differ from that obtained by means of the Landauer-Büttiker’s formula and that the main noise source is represented by the partition noise. [ABSTRACT FROM AUTHOR]