79 results on '"Miyashita, K."'
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2. Recurrence of Acute Exacerbation in Patients with Interstitial Lung Disease
3. Clinical Significance of the Lower-Lobe Interstitial Lung Disease in Patients with Idiopathic Pleuroparenchymal Fibroelastosis
4. Survival Benefit of Corticosteroid and Intravenous Cyclophosphamide Therapy in Acute Exacerbation of Idiopathic Pulmonary Fibrosis: A Propensity Score-Matched Analysis
5. New method for liquid-medication filling systems
6. Control circuit topology of a time-divided torque and suspension force control type bearingless motor
7. New layout dependency in high-k/Metal Gate MOSFETs
8. Design of a time-divided torque and suspension force control type bearingless motor
9. Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond
10. Competitive and cost effective high-k based 28nm CMOS technology for low power applications
11. A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process
12. Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL
13. Advanced DSS MOSFET technology for ultrahigh performance applications
14. 0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node
15. Study on High Performance (110) PFETs with Embedded SiGe
16. Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors
17. A plastic packaged Ku-band LNB with very high susceptibility to supply PLL in 0.18um CMOS.
18. A Ku-band down-converter with perfect differential PLL in 0.18um CMOS.
19. A Map Matching Algorithm for Car Navigation Systems that Predict User Destination.
20. An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS.
21. Coordinating Service Distribution through Cooperative "YuuZuu" Reservations.
22. Doping accuracy requirements of USJ processes for advanced sub-100 nm CMOS devices
23. Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation
24. Advanced CMOS device sensitivity to USJ processes and the required accuracy of doping and activation.
25. RF bipolar transistors in CMOS compatible technologies.
26. In/Sb halo doping and replaced anneal sequence for 80 nm CMOS.
27. A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node.
28. New Guidelines of Optimizing SALICIDE Structure for High Speed CMOS LSI
29. Improved Ti SALICIDE Technology Using High Dose Ge Pre-Amorphization for 0.10um CMOS and Beyond
30. Experimental Study of New Lysholm Supercharger with a Simple Unloading System
31. Silicide Technology in Deep Submicron Regime.
32. Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation.
33. An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE.
34. Learning control knowledge through cases in schedule optimization problems.
35. Using case-based reasoning to acquire user scheduling preferences that change over time.
36. A framework for constructing animations via declarative mapping rules.
37. Growth and properties of tungsten-bronze ferroelectric potassium lithium niobate single crystals.
38. A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions.
39. Non-contact magnetic toroue sensor
40. Highly uniform heteroepitaxy of cobalt silicide by using Co-Ti alloy for sub-quarter micron devices
41. Evolving bipedal locomotion with genetic programming - a preliminary report
42. Simulation-Based Advanced WIP Management and Control in Semiconductor Manufacturing
43. High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
44. Growth and properties of tungsten-bronze ferroelectric potassium lithium niobate single crystals
45. Constant time interval simulation for semiconductor manufacturing
46. 110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application
47. MOSFET design of 100 nm node low standby power CMOS technology compatible with embedded trench DRAM and analog devices
48. A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node
49. A comparison between the powers of the PARBS and the RMBM
50. A CMOS technology platform for 0.13 μm generation SOC (system on a chip)
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