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For the analysis of results of research in a context of non-linearity from the questionnaire for young spouses which was used in research of young family, we had been received 19 interval scales by means of the certain transformations of results of answers to 19 questions. For a substantiation of necessity of studying of the elementary non-linear dependences we shall stop on demonstration of their quantity. If we choose dependences with coefficient of correlation more than 0.6 (our factor of the connection strenght also more than 0.6) such dependences it is observed only 4. While non-linear dependences with factor of the connection strenght more than 0.6 and small coefficient of correlation (at least on the module twice there is less than factor of the connection strenght) we have 14. Thus, the simpliest (dependence with a maximum and a minimum, monotonous, but not linear) non-linear dependences appeared in three and a half of time more, than linear. Specificity of the dependences submitted in the article table following: dependences with a minimum - 8, dependences with a maximum - 3, monotonous, but far from linear, dependences - 3 (1 growing and 2 decreasing). [ABSTRACT FROM AUTHOR]

This study is carried out at Swastik Machine Tools, Pune. The company is vendor of original equipments manufacturers in automobile sector. This study is related to a product cam lever follower. This study is a part of quality improvement study taken in the company for reducing rejections. In the case study we have carried out cause and effect analysis where we want to examine the ‗measurement' category. Here we would like to examine the present system of measuring external diameter. For this we have used 5 reference values and 10 repartitions. We have formulated the regression coefficient and tested linearity and bias using t-test. It is observed that both are insignificant and do not contribute in the rejection. [ABSTRACT FROM AUTHOR]

This paper discusses several radio design issues and presents a systematic approach towards receiver budgeting for LTE standard. IIP3 and noise figure, both showing opposite trends with respect to gain, are the two key parameters considered for budget allocation among the receiver front end modules. 1-dB compression point and IIP3 requirements are deduced from the given LTE specification and trade-offs have been made between linearity and noise requirement to achieve the best possible solution for each sub-system in the receiver. With the approach presented in this paper, we could assign a gain value of 10 dB for LNA which resulted total noise figure of 4.9 dB that is well below the required specification. In addition, 14 dBm is found to be the best feasible value for IIP3 of the mixer and that has also been verified to satisfy the LTE requirements. [ABSTRACT FROM PUBLISHER]

This paper proposes tapping noise suppression with a new phase-based detection. Phase slope of the input noisy signal is compared with an ideal phase slope obtained from an average of intra-frame slopes along the frequency axis. In order to cope with heavily low-pass characteristics of tapping noise spectrum, phase values are weighted with the magnitude at each frequency point. Phase unwrapping problem is alleviated by use of a rotation vector of frequency domain components. Comparison of enhanced signal spectrogram with that of clean speech demonstrates superior enhanced signal quality. [ABSTRACT FROM PUBLISHER]

This paper presents a fully-integrated linear CMOS power amplifier (PA) with an adaptive gate bias circuit in Common-Gate (CG) amplifiers. The bias circuit is proposed to achieve a high linearity with deep class-AB biasing of Common-Source (CS) stage. The proposed single stage PA including the bias circuit is fabricated using 0.18-μm RF CMOS technology. The adaptive gate bias circuit improves the evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) about 7 dB at a mid power region and 2.5 dB at a high power over a constant bias for the same LTE signal. [ABSTRACT FROM PUBLISHER]

We have proposed surface acoustic wave (SAW) duplexer for CDMA/LTE markets. Advancements of the communication system are progressing in accordance with the increase of the data user needs. Technology that uses multi-band and simultaneous communication has been progressing. Effect of mutual interference in the mobile phone increases, deterioration of communication quality is concerned. [ABSTRACT FROM PUBLISHER]

The linearity of the Ozone Mapping and Profiler Suite Nadir instruments' radiometric response is characterized using two onboard LED calibrators with a series of lamp exposures of various times and therefore varying count levels. It is specified that the non-linearity of the nadir sensors shall be no more than 2% of full well, the linear degradation rate of the LED output shall be less than 1% per minute, and the high-frequency LED current variability shall be less than 0.1% RMS. During the on-orbit characterization, we monitor the lamp signal drifts, temperature dependency and nonlinearity sensitivity. The lamp signal variations are compensated prior to the calculation of the sensors' linear calibration coefficients. The calibration coefficients are derived by interpolating between measured count levels and ideal linearized count levels. System nonlinearity is estimated by fitting normalized signal count rates to a second order polynomial function. Additionally, sensor on-orbit dynamic range is verified and thermal impact on nonlinearity sensitivity is analyzed. Our results demonstrate that sensor linearity performance meets the system requirement. [ABSTRACT FROM PUBLISHER]

The Ozone Mapping and Profiler Suite (OMPS), launched on-board the Suomi National Polar-orbiting Partnership Spacecraft (S-NPP) on October 28, 2011, has been in operation for more than one year. It continues 40 years ozone study missions by providing the S-NPP science community with data products of ozone in the Earth's atmosphere. The sensor as well as the associated mission data processing system, the Interface Data Processing Segment (IDPS), necessary to process the Raw Data Records (RDRs) into Sensor Data Records (SDRs) and Environmental Data Records (EDRs), has been extensively calibrated and evaluated during the early orbit check and intensive calibration and validation (ICV). This paper will summarize the provisional SDR performance as well as the modifications of the IDPS SDR algorithm based on needs identified during the EOC and ICV. Examples of the first 18 month's sensor calibration parameters trending will be provided. [ABSTRACT FROM PUBLISHER]

This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “Tsi”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain Av, IP3, maximum oscillation frequency fMAX and dc power consumption PDC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of fMAX, Av and IP3 in DG configuration with power consumption of ∼ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (Ion/Ioff) as specified in current International Technology Road map for Semiconductors (ITRS). [ABSTRACT FROM PUBLISHER]

In this study, the ruthenium dioxide (RuO2) sensing films were prepared by radio frequency sputtering system on the flexible polyethylene terephthalate (PET) and used the screen printer technology to prepare the conducting wires to connect the sensing windows and spread on insulation layer by epoxy which can protect the conducting wires and sensing windows. In the experimental, first, the biosensors were analyzed for the pH value of the hysteresis reaction (5.651 mV). Second, the magnetic beads and glucose oxidase (GOD) were combined with covalent binding, and coated on the sensing windows by Nafion. It was used to measure the linearity and sensitivity, as well as analyzed the different volume ratios of Nafion and GOD and the stability of the glucose biosensors. The results showed that the glucose biosensors exhibit a high linearity (0.987), sensitivity (29.652 mV/mM) by the volume ratio of Nafion to GOD is 3∶4 and present high stability, which can be measured the glucose solution, repeatedly. [ABSTRACT FROM PUBLISHER]

Media convergence has led to a variety of new media formats, genres, and communication patterns, which can be described as the result of a process of hybridization. This new hybrid form is the interactive information graphic that combines elements of graphic design, illustration, photography, digital animation, film, data visualization, and journalism; particularly in online journalism, interactive information graphics have become more and more important for conveying information visually. In this paper, we investigate the interactive information graphic as a hybrid form of visual storytelling through methods of expert interviews, grounded theory, and content analysis. Our study of the state of the art in interactive information graphics yields new insights into the semiotic modes, the structures, the genres, the production process, and the required media skills. The findings provide evidence of the need for an interdisciplinary research methodology and approach to this specific field of visual communication studies. [ABSTRACT FROM AUTHOR]

An on-chip CMOS RF power detector (PD) is described that has internal temperature compensation and the highest reported linearity. The PD generates a DC current that is proportional to the square root of the RF input power by use of a new detection technique that utilizes p-n junction diodes. The generated DC current obtained by subtracting a replicated current produces the real-time temperature compensation. This subtraction method also suppresses the generated-current error caused by the parasitic element, thereby improving the linearity of the PD. The proposed on-chip PD was fabricated in 90-nm CMOS technology and integrated with a power amplifier (PA). The measured input range for a linearity error within ±0.5 dB was 27 dB at 0.824 GHz and 23 dB at 1.98 GHz. The measured results showed that the PD overcomes real-time temperature changes caused by self-heating, which depends on the output power of the PA. The PD consumes 0.3 mW at 0-dBm input power and occupies 0.04 mm2, which are small enough for the PA. [ABSTRACT FROM PUBLISHER]

A 40 nm DAC-based CMOS wideband transmitter (WBTX) for cable applications is presented. It has a 2.2 GHz signal bandwidth and exhibits an in-band IM3 of less than −58 dBc. The WBTX consists of a current-steering DAC with digital sinc equalization and roll-off compensation. By implementing high-speed, feed-forward pipelined digital logic, the DAC sampling rate extends to 5 GHz. The WBTX can deliver up to +11 dBm of output power while consuming only 375 mW. The WBTX occupies 1.65 mm2 of area. [ABSTRACT FROM PUBLISHER]

This paper demonstrated a 5GSample/s track and hold amplifier with 65nm CMOS process. For 6bit ADC application, this work has over 42dBc of SFDR to offer a low distorted signal. The source-degenerated source-couple amplifier with peaking inductance is employed to expand the signal swing and bandwidth, while the power dissipation is maintained as low as possible. The measured power dissipation is 48.8mW at 1.2V of supply voltage. [ABSTRACT FROM PUBLISHER]

In this paper, a 5.25GHz linear CMOS power amplifier (PA) with an integrated diode is presented. The proposed technique improves the linearity of the power amplifier by a diode-connected NMOS transistor. The NMOS diode is effective to suppress both the AM-AM distortion and AM-PM distortion. To verify this concept, the power amplifier is simulated with TSMC 0.13-μm CMOS process. With a power supply of 3.3 V, the proposed power amplifier exhibits a maximum IMD improvement of 25 dB with a PAE of 38.2 % at an output P1dB of 19.6 dBm. [ABSTRACT FROM PUBLISHER]

Based on TSMC 0.18-μm CMOS process, a 5.8-GHz CMOS power amplifier for DSRC application is investigated in this paper. The proposed power amplifier is consisted of two stages which are followed by input, output and inter-stage matching networks. Capacitance compensation technique is employed to improve the linearity of the output stage power amplifier. Simulation results show that the designed power amplifier with low voltage operation of 1.8 V can achieve linear power gain of 16.9 dB, 1dB compression power output of 17.6 dBm, third order inter-modulation distortion (IMD3) of −43 dBc at the output power of 10 dBm, which has about 8 dB improvement compared with the structure without the capacitance compensation technique. [ABSTRACT FROM PUBLISHER]

The lightweight hash function PHOTON has shown excellent hardware compactness which almost reaches the theoretical optimum and brings benefits for on-tag applications. Unlike cryptanalysis which tries to find collisions or build distinguishers on PHOTON, we apply cube attack for secret recovery of PHOTON. We focus on 1 to 3 round of PHOTON-128/16/16 in our experiments. Using cube attack, we show at least half of the message bits can be recovered. When more powerful computing capability is used, it is possible to recover more bits of the message in the same number of PHOTON rounds. [ABSTRACT FROM PUBLISHER]

Based on the capillary pressure curves measured at lab, the pore structures distribution features were analyzed for cores with several permeability. The comparison between methods of the single-line and two-line fitting indicated the multi-fractal characteristics of the heterogeneous pore distribution. The study shows that the fractal dimension could be used to describe such characteristics. The greater the pore structure heterogeneity of a core, the bigger the fractal dimension calculated by single-line fitting, and the larger difference between the two fractal dimensions calculated by the two-line fitting method. [ABSTRACT FROM PUBLISHER]

Source follower based open loop track and hold circuits are commonly employed at front end of pipelined analog to digital converters. Performance of such track and hold degrades at higher operating frequencies due to non linearity arising due to non ideal MOS switches. In present work, conventional open loop track and hold circuit is implemented and its performance is improved by adopting two switch linearization techniques: voltage bootstrapping and gate voltage boosting. Based on these two techniques, another bootstrapped switch is proposed which operates at voltage higher than Vdd. Track and hold with proposed switch produces low distortion and can provide 9 bit static linearity at 500 MHz clock and suitable for high resolution high speed analog to digital converters. [ABSTRACT FROM PUBLISHER]

In this study, we demonstrate a simple fabrication of polymeric diaphragm pressure sensors by utilizing a commercial thin-film strain gauge embedded in the diaphragm. Two different polymeric materials, polydimethylsiloxane (PDMS) and polyethylene terephthalate (PET), are employed to show the feasibility of the sensors by comparing the performances, sensitivity, linearity, and device long-term stability. To characterize the fabricated pressure sensors, we design a dynamic pressure characterization system operating in either compressed air or water environments with a programmable temperature control. Experimental results show that the pressure sensitivity of PET pressure sensors is about 2.5 times better than that of PDMS pressure sensors and the pressure sensitivity in water is similar to that in air for both PET and PDMS pressure sensors. Moreover, significant degradation of the output signal of PDMS diaphragm pressure sensors is observed over time in water operating condition. Finally the proposed pressure sensor is verified for biomedical applications by performing in-vivo test monitoring the rabbit bladder pressure. [ABSTRACT FROM PUBLISHER]

A cross coupled transconductance mixer for 3.6 GHz WiMAX application is presented in this paper. The circuit was designed with TSMC 0.18µm CMOS process. An RF PMOS is used to improve the linearity. The proposed folded mixer has the conversion gain of 0.8dB with LO power at −5dBm. The IIP3 is 9.6dBm, noise figure is 17dB. The total power consumption with output buffer is only 4.3mW under a 1V supply voltage. [ABSTRACT FROM PUBLISHER]

Linear combination is a popular approach in information fusion due to its simplicity. However, it suffers from the performance upper-bound of linearity and dependency on the selection of weights. In this study, we introduce a ‘simple’ alternative for linear combination, which is a non-linear extension on it. The approach is based on the Analytical Network Process, which is a popular approach in Operational Research, but never applied for fusion before. The approach benefits from two major ideas; interdependency between classes and dependency of classes on the features. Experiments conducted on CCV dataset demonstrate that proposed approach outperforms linear combination and other simple approaches, moreover it is less-dependent on the selection of weights. [ABSTRACT FROM PUBLISHER]

A low-cost, high-yield, low-power gyro is presented from which five high performance variants are created by altering operating conditions. Flexible design of the gyro and the excellent dynamic range is explained. The paper details the high performance aspects of each variant with results from large population of dies. Measured results show a start up time less than 3ms and gyro output nonlinearity less than 0.1% of the full scale specification up to at least 20,000°/sec. The gyro has 8–12°/hr Allen deviation performance with white noise of 0.01°/sec/√Hz and bandwidth of 2kHz. [ABSTRACT FROM PUBLISHER]

This paper presents a new gain stage based on the Replica gain enhancement method. The proposed gain stage operates 2.35 times faster than a similar size two-stage gain stage in the same precision, power consumption, and the same load capacitor. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.18µm CMOS technology. HSPICE simulation confirms the theoretical estimated improvements. [ABSTRACT FROM PUBLISHER]

A new operational amplifier based on the conventional TFC op-amp structure is presented. A novel method is used to increase the dc-gain of the triple folded cascode op-amp. This method does not limit the bandwidth, output voltage swing range and the phase margin of the triple folded cascode op-amp. [ABSTRACT FROM PUBLISHER]

This paper proposes a 2.4 GHz SiGe HBT differential power amplifier (PA) with a novel on-chip variable gain active predistorter (PD) for linearity enhancement. The fully differential active PD provides an open collector adaptive bias control which can effectively enhance the linearity while improve power added efficiency (PAE). The PA with active PD achieves an output 1-dB compression (OP1dB) of 20 dBm, a gain control range of 10 dB, a PAE of 30%, and an error vector magnitude (EVM) improvement of 2.4 % under OFDM/64-QAM modulation signal. The fabricated die size including pads is less than 0.74 mm2 and suitable for highly integrated linear PA. [ABSTRACT FROM PUBLISHER]

In this paper, a monolithic 2-stage differential power amplifier (PA) is designed and fabricated in the 0.35 µm IBM 5PAe SiGe BiCMOS technology where the through-wafer-vias (TWVs) are available. A cascode topology is adopted to relieve the voltage stress for the power stage transistors. All components are integrated on-chip for the PA except the input/output baluns. The envelope tracking (ET) technique is applied to this 2-stage PA to enhance the PAE and linearity for high power-to-average-ratio (PAR) Long-Term-Evolution (LTE) signals. The ET-based PA system achieves a linear output power of 20.4 dBm with a gain of 30.5 dB and an overall system PAE of 22%, using an LTE 16QAM 5 MHz signal with ∼7.5 dB PAR at 1.85 GHz. Compared to the 2-stage PA operating with fixed voltage supplies, the ET-based PA system improves the linear output power by 3.2 dB and its system PAE by over 10%. [ABSTRACT FROM PUBLISHER]

This paper presents a fourth-order linear phase low-pass filter for high speed wireless system. A high linearity operational transconductance amplifier (OTA) is proposed, where the characteristics of input attenuators and low source impedance are used to achieve high linearity. By using the proposed OTA as a building block, the fourth-order low-pass filter with the cutoff frequency of 40MHz is implemented. The filter is designed in 0.18-µm CMOS process technology and the HD3 performance is about −53.4dB. The filter works with 1.8V supply voltage and its power consumption is about 14.1mW. [ABSTRACT FROM PUBLISHER]

This paper presents a time delay and integration (TDI) structure for CMOS image sensor (CIS) with adjacent pixel signal transfer (APST). The CCD-like TDI function is achieved in CIS by proposed APST without additional in-pixel device and minimum routing effort. The in-pixel integrated signal is transferred to adjacent pixel and summed up by an off-pixel column-shared unity-gain buffer. A 128×6 pixel array with 6×6µm2 pixel size has been designed and fabricated in TSMC0.18µm 1P6M CIS technology providing 6 TDI stages with fill factor of 23.1%. It achieves a signal to noise ratio (SNR) improvement of 13dB, a transfer efficiency of 99.6%, and a total power dissipation of 4.43 µW per column at 1.6K fps. [ABSTRACT FROM PUBLISHER]

This paper presents a digitally-assisted two-step linearity enhancement technique for a 14-bit current-steering digital-to-analog converter. The static nonlinearity introduced by the wittingly small current sources for the sake of area reduction is firstly calibrated by evaluating and compensating the offset current between the average of 6-bit MSB array and the sum of 8-bit LSB array. An unique dynamic element matching (DEM) algorithm is then applied to suppress the residual nonlinearities without introducing too many transient glitches at the output. A 14-bit 200MS/s DAC is fabricated to verify the proposed scheme and successfully demonstrates a decent linearity of 82.5dB SFDR within an area of 0.45mm2 in a 0.18-µm CMOS process. A good power efficiency is kept at the same time as well. [ABSTRACT FROM PUBLISHER]

The Best Linear Approximation (BLA) is a linearisation of the transfer characteristics of a nonlinear system in a least squares sense. The BLA is known to depend on the statistical properties of the input signal used to identify it. The theory for Gaussian input sequences has been known for several years, but the corresponding theory for binary input sequences has only recently been developed. In this paper, experiments on a physical electronic Wiener system, aimed at verification of predictions made for the differences between BLA's estimated using Gaussian sequences and those estimated using binary sequences, are described. The results were found to be a good match with the theory but difficulties encountered during the experiment highlight a need for further work in extending the discrete-time theory to the continuous-time domain. [ABSTRACT FROM PUBLISHER]

To establish traceability for high current measurements, comparison tests of high current shunts in high power laboratories have been carried out with STL reference shunts since 2005. In this paper, we describe the comparison test results of shunts in high power laboratories in Asia. Test results showed the shunts tested for the comparison tests performed well and most of the differences of the scale factor with the power frequency current between the reference shunt and those tested in participating laboratories were less than 0.5%. [ABSTRACT FROM PUBLISHER]

An often-overlooked but important CMOS device sizing approach that significantly affects circuit noise performance has been discussed theoretically and verified by simulation. It has been demonstrated that sizing a CMOS device using maximum number of gate fingers results in as much as 9dB improvement in circuit noise figure. Furthermore, and as side benefits, parasitic capacitance, linearity, and power consumption are also improved considerably. For the purpose of simulation, Common-Gate Low-Noise Amplifier (LNA) has been utilized as the reference circuit. The simulation has been carried out using 0.12µm CMOS process. [ABSTRACT FROM PUBLISHER]

The aim of this paper is presented A Gilbert mixer with passive balun for 18 GHz application. It was used Taiwan Semiconductor provided by TSMC CMOS 0.18 µm process. We proposed mixer consists of Gilbert Cell, balun and the IF buffer amplifier. Finally, at the operation voltage of Vdd = 1.8 V, RF frequency =18 GHz, LO frequency =17 GHz, the conversion gain is about 8.6 dB, input P1dB and power consumption are about −9 dBm and 41.4 mW. The chip size including all testing pads is 0.76 × 0.59 mm2. [ABSTRACT FROM PUBLISHER]

The aim of this paper is presented A Gilbert mixer with passive balun for 18 GHz application. It was used Taiwan Semiconductor provided by TSMC CMOS 0.18 µm process. We proposed mixer consists of Gilbert Cell, RF and LO stage matching and the IF buffer amplifier. Finally, at the operation voltage of Vdd = 1.8 V, RF frequency =18 GHz, LO frequency =17 GHz, the conversion gain is about 11.676 dB, input P1dB and power consumption are about −15 dBm and 54 mW. The chip size including all testing pads is 0.82 × 0.79 mm2. [ABSTRACT FROM PUBLISHER]

Typically, power sensors are calibrated for input reflection coefficient, calibration efficiency factor and linearity. Some new power sensors also need absolute power calibration. Multiple systems are used to measure each of the parameters. With an appropriately configured VNA, all the measurements can be performed with a single connection and set up. This paper shows how it is done and expected uncertainties. [ABSTRACT FROM PUBLISHER]

A low power ultra wideband very low noise amplifier is presented. The proposed LNA scheme uses two parallel nMOS and pMOS cascode common gate (CG) branches, an active positive feedback and input matching extender. Compared to the CG structure, the proposed LNA results in improved noise figure and input matching over a wide bandwidth with the same power consumption. Circuit level analysis and simulation results are provided to verify the effectiveness of the proposed LNA scheme. Simulated in a 0.18µm RF CMOS technology, the proposed LNA achieves a noise figure of 2.2 to 2.5 dB and input return loss (S11) less than −10 dB over whole bandwidth while consumes only 2.7 mW power from a 1.8 V power supply. The −3 dB power gain (S21) is 19.7 dB and maximum values of IIP3 and IIP2 are −6 dBm and 15 dBm, respectively. [ABSTRACT FROM PUBLISHER]

In this paper a low-voltage low-power Concurrent Dual-Band Low Noise Amplifier (LNA) with linearity improvement technique is presented. By using advantageous of current reuse (CR) topology and forward body biasing (FBB) technique the proposed LNA can operate at a reduce supply voltage and power consumption. The liberalized LNA's is achieved using auxiliary transistor and utilizing derivative superposition (DS) method. Using TSMC 0.18um process, the IIP3 is improved more than 50%, with the cost of decrease 2dB gain for each band. LNA is designed at 2.4GHz and 5.2GHz for IEEE802.11a/b/g application with 2.89mW power consumption and 0.7V supply voltage. [ABSTRACT FROM PUBLISHER]

A simulation based design procedure for supply modulated amplifiers is presented. With the developed design-guide optimum transistor operation under supply modulation can be simulated with arbitrary modulation voltage functions at varying impedance conditions. Alternative supply voltage functions have been investigated for fixed impedance conditions and for an implemented class-F design. [ABSTRACT FROM PUBLISHER]

An analog phase shifter for applications around 140GHz is presented. The MMIC is based on our in-house 100nm InGaAs mHEMT technology and has a chip size of 1mm2. The circuit uses two quarter-wavelength transmission lines and two tunable impedances governed by a control voltage. As a result, the signal phase can be controlled stepless with a maximum shift of about 60°. Over the whole tuning range the gain ripple is less than 0.3dB and the phase shifter has a conversion gain of about −3.5dB. Because of its passive topology the circuit shows a very high linearity. [ABSTRACT FROM PUBLISHER]

A low noise amplifier (LNA) is implemented in this work for ultra wide band (UWB) localization and sensing systems within a wide frequency range starting from 400MHz and up to 10GHz. The topology used is a resistive shunt feedback and a peaking inductance in series with the output transistor to achieve the desired bandwidth and have better noise performance. The LNA is fabricated in low cost 0.25µm 92GHz fmax SiGe-HBT-BiCMOS process technology. The area of the manufactured chip is 0.73mm2. The achieved gain is 12dB with a NF less than 3.7dB over the entire frequency range while the consumed power is only 14.5mW. [ABSTRACT FROM PUBLISHER]

A broadband low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. The proposed LNA utilizes a PMOS and individual stages with common-gate and common-source cascade for second-order and third- order distortion cancellation. The LNA IIP3 is limited by the second-order interaction between the common source and common gate stages. The LNA is designed using standard 0.18μm CMOS technology. The LNA achieves S21 of 12.1 dB and the NF is lower than 3.1 dB over 0.7-2.5GHz.The IIP3 is +8dBm at 1.5GHz. [ABSTRACT FROM PUBLISHER]

This paper presents the development and normalization of a novel sensor system built with low-cost industrial-grade multilayer ceramic capacitors (MLCC). MLCCs play both the roles of force sensing elements and force sustaining elements. With adopting this low-cost industrial component of MLCC (less than 1 cent USD for a sensing component), the time and the cost for producing a high performance force sensor system can be achieved. Practically, industrial-grade MLCCs are produced for capacitor applications but not for a sensing element for force measurement. However, the sensitivity for each independent MLCC presents a large variation for force sensing (coefficient of variation around 0.6). This study successfully overcome this drawback, a simple poling process is demonstrated to both increase the sensitivity and to reduce the variation coefficient of MLCC force sensors. Results indicate that the variation for the MLCCs after re-poling treatment is reduced to 0.02. The effects on the poling voltage and poling time are experimentally investigated. Results show that the MLCC treated with a high poling field can increase sensitivity and also reduce the variation for force sensing. This re-poling treatment is essential for developing a simple and low cost MLCC-based force sensor system that can be used in a wide variety of applications. [ABSTRACT FROM PUBLISHER]

Here, we propose a practical single pole double throw (SPDT)-structured RF-MEMS switch for mobile handsets applications. This RF-MEMS switch has a very low insertion loss of 0.18dB and a high isolation of 32dB, up to 3GHz. And this RF-MEMS switch achieves small size by using through silicon via (TSV) structure (2.5×1.6×0.4mm3). Moreover, in the last of this paper, we show the feasibility of 3 voltage drive by integrating a charge pump IC, since a low-voltage drive is indispensable for mobile handsets applications. [ABSTRACT FROM PUBLISHER]

This paper proposes a new linearity improvement technique using third-order transconductance cancellation. The proposed technique requires a transconductance stage composed of common-source and common-gate stages with source degeneration inductors and eliminates the third-order distortion term through a feed-forward compensation. The analysis of the proposed technique is performed using current equations representing nonlinear distortion. The proposed technique is applied to a CMOS RF mixer based on Gilbert cell. The simulated IIP3 of the proposed mixer is −2.5 dBm which is improved by approximately 7 dB compared with a conventional structure while consuming 4.14 mW from a supply voltage of 1.5 V. [ABSTRACT FROM PUBLISHER]

Different kinds of RF power combiner are studied. Wilkinson and hybrid combiner show very good linearity but low power efficiency. Chireix combiner using stubs at the input shows good efficiency and bad linearity of system. This paper shows that an unmatched chireix combiner without stub used at the output of class-B amplifiers can be optimized in transmission line length in order to obtain the same good linearity of a matched Wilkinson combiner but better efficiency. Analytical, ADS simulation and experimental work are presented to support this work. Excellent agreement between simulations and measurements is obtained in all cases considered. [ABSTRACT FROM PUBLISHER]

In this contribution, a Si-LDMOS transistor is used to design a power amplifier (PA) in a broad frequency band covering a number of modern wireless communications systems. The design, implementation, and experimental results of 4 W wideband Si-LDMOS PA are presented. A method based on source/load--pull characterization has been used to extract optimum source and load impedances over the desired bandwidth. Following this, a systematic approach to design wideband matching network is suggested. In the frequency band 1.7–2.7 GHz, 3.4 – 4.0 W output power and 25 % drain efficiency were achieved. The 3rd-order intermodulation distortion (IMD3) performance of the designed PA is evaluated by providing a two-tone signal to the amplifier. At two-tone output power of 1 W, IMD3 of around −30 dBc was measured over the design band. [ABSTRACT FROM PUBLISHER]

This paper presents a low power, high linearity wideband cascode low noise amplifier (LNA) targeting the GSM/LTE standards and RFID reader applications. The common source (CS) stage is considered to be the dominated nonlinearity source for cascode LNA and the modified derivative superposition (MDS) technology is adopted to improve the linearity of this stage. However, with the operating frequency increases, the nonlinearity influence coming from the common gate (CG) stage increases also. The nonlinearity effect of the CG stage on the cascode amplifier is investigated and an improving method is proposed. This design combines the MDS technique with the proposed method to increase gain and linearity while maintaining a low NF of the LNA. The proposed LNA is implemented in the IBM 0.13um CMOS technology. The NF is 1.4/2.0/2.1dB at 700/900/950 MHz bands, respectively. The LNA has a third order intercept point of +14.6dBm in a wide frequency from 700MHz to 1GHz. [ABSTRACT FROM PUBLISHER]