Fast-settling gain stage using replica amplification for high performance pipeline ADCs.

This paper presents a new gain stage based on the Replica gain enhancement method. The proposed gain stage operates 2.35 times faster than a similar size two-stage gain stage in the same precision, power consumption, and the same load capacitor. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.18µm CMOS technology. HSPICE simulation confirms the theoretical estimated improvements. [ABSTRACT FROM PUBLISHER]