19 results on '"2.5D stacking"'
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2. Failure analysis of a 2.5D stacking using μinsert technology
3. DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.
4. Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond.
5. Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems.
6. Silicon photonic memory interconnect for many-core architectures.
7. Coupling capacitance extraction in through-silicon via (TSV) arrays.
8. A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer.
9. Effects of cleaning process on the reliability of ultra-fine gap for 3D package.
10. A Software-Managed Approach to Die-Stacked DRAM.
11. The application of through silicon vias (or TSVs) for high power and temperature devices.
12. Toward Efficient Programmer-Managed Two-Level Memory Hierarchies in Exascale Computers.
13. NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
14. 3D stacking for multi-core architectures: From WIDEIO to distributed caches.
15. Physical design of the "2.5D" stacked system.
16. A feasibility study of 2.5D system integration.
17. 6.1 memory and system architecture for 400Gb/s networking and beyond.
18. Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?
19. An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application.
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