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A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer. [ABSTRACT FROM AUTHOR]

A multiple-frequency continuous-wave (MFCW) agile radar system has the ability to cope with various physiological conditions of a human subject. Following the mathematic model, a favorable carrier frequency for detection is pursued by analyzing the amplitude and composition of the baseband signal. In Experiment-1, a CMOS dual-band transceiver prototype emulate searching a subject from a distance. The frequencies of the dual-band system are 4.26–4.95 GHz and 17.06–19.79 GHz. During the experiment, the respiratory signal could be detected up to 12 m, and the heartbeat signal up to 6 m. Even with a wooden or a brick barrier in the path, the vital-sign detection remained satisfactory. Later, a concurrent MFCW detection is performed in Experiment-2 for more precise analyses. From the concurrent results, the breathing status can be inferred, and by cross-correlating the results after the ensemble empirical mode decomposition (EEMD) and principal component analysis (PCA), the nonlinear effects of respiratory harmonics or intermodulation tones are reduced, resulting in an accurate heart rate extraction. The receiver front-end and the signal source are manufactured using a 180-nm CMOS process, both packaged on an RO4003C printed-circuit board (PCB). [ABSTRACT FROM AUTHOR]

A 55-71-GHz fully integrated power amplifier (PA) using a distributed active transformer (DAT) is implemented in 90-nm RF/MS CMOS technology. The DAT combiner, featuring efficient power combination and direct impedance transformation, is suitable for millimeter-wave (MMW) PA design. Systematic design procedures including an impedance allocation plan, a compensation line, and a gain boosting technique are presented for the MMW DAT PA. The monolithic microwave integrated circuit (MMIC) performs a high and flat small-signal gain of 26 [+ or -] 1.5 dB from 55 to 71 GHz, which covers a full band for 60-GHz wireless personal area network applications. Using cascode devices and a DAT four-way power combination, the CMOS PA delivers 14.5-and 18-dBm saturated output power with 10.2% and 12.2% power-added efficiency under 1.8- and 3-V supply voltage, respectively, at 60 GHz. The maximum linear output power ([P.sub.1 dB]) is 14.5 dBm. To the best of our knowledge, the MMIC is the first demonstration of a V-band CMOS PA using a DAT combining scheme with highest linear output power among the reported 60-GHz CMOS PAs to date. Index Terms--CMOS, distributed active transformer (DAT), gain boosting, power amplifier (PA), V-band.

A compact and broadband 0.8-77.5-GHz passive distributed drain mixer using standard 0.13-[micro]m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of 5.5 [+ or -] 1 dB from 0.8 to 77.5 GHz with a compact size of 0.67 x 0.58 [mm.sup.2]. The output 1-dB compression point is -8.5 dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption. Index Terms--CMOS, distributed mixer, drain mixer, millimeter wave (MMW).

This letter presents an ultrabroadband power amplifier (PA) with AM–phase modulation (PM) linearizer in a 28-nm bulk CMOS process for 5G millimeter-wave (mm-Wave) mobile communications. To enable the 5G mm-Wave multigigahertz broadband, a pMOS linearizer in power stage is introduced to achieve broadband AM–PM linearization. The proposed linearized PA achieves a 3-dB gain bandwidth (BW) from 19.7 to 38.9 GHz (65.5%) covering multiple 5G bands. The measured OP1 dB is 12.7 dB ± 0.6 dB from 22 to 38 GHz, and the PAE is larger than 25% from 21 to 36 GHz (50%). For 100-MHz 64-quadratic-amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, this PA obtains a linear output power of 8.5 dBm/8.3 dBm/8.8 dBm under error vector magnitude (EVM) of −25 dB with modulated PAE of 11.0%/11.0%/11.9% at 23 GHz/28 GHz/38 GHz, respectively. Moreover, the measured back-off power from OP1 dB to linear output power is 4.7 dB/3.9 dB/3.7 dB at 23 GHz/28 GHz/38 GHz. [ABSTRACT FROM AUTHOR]

A 27–44 GHz subharmonic up-conversion mixer using 65 nm CMOS technology is presented. For subharmonic scheme and wide RF/IF bandwidth, a dual-ring topology is developed in this mixer design. To increase the linearity and conversion gain (CG) without adding additional local oscillator (LO) power, a LO boosting linearization technique is adopted. The subharmonic up-conversion mixer achieves a measured CG of −12 dB ± 1.5 dB from a wide RF frequency of 27 to 44 GHz. The 3-dB IF bandwidth is from dc to 10 GHz. After adopting the linearization technique, the output 1-dB compression point (OP1 dB) of the subharmonic up-conversion mixer can be improved from −12 to −9 dBm at 38 GHz with zero addition dc consumption. [ABSTRACT FROM AUTHOR]

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-[micro]m standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 [+ or -] 1.5 dB and 7.5 [+ or -] 1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications. Index Terms--CMOS, demodulator, direct conversion, millimeter wave (MMW), modulator, sub-harmonically pumped.

A 44-GHz monolithic microwave integrated circuit (MMIC) low-loss built-in linearizer using a shunt cold-mode high-electron mobility transistor (HEMT), based on the predistortion techniques, is presented in this paper. The proposed cold-mode HEMT linearizer can enhance the linearity of the power amplifier (PA) with a low insertion loss (IL < 2 dB), a compact die-size, and no additional dc power consumption. These advantages make the linearizer more suitable for millimeter-wave (MMW) applications. The physical mechanism of the gain expansion characteristics of the proposed linearizer is analyzed. A systematic design procedure for a low-loss linearizer is developed, which includes: 1) insertion loss minimization through a device-size selection and 2) linearity optimization through a two-tone test. To demonstrate the general usefulness of the proposed linearizer, the linearizer was applied to a two-stage 44-GHz MMIC medium PA and a commercial MMW PA module. After linearization, the output spectrum regrowth is suppressed by 7-9 dB. To keep the adjacent channel power ratio below -40 dBc, the output power has been doubled from 15 to 18 dBm at 44 GHz. The error vector magnitude of the 16-quadrature amplitude modulation signal can be reduced from 6.11% to 3.87% after linearization. To the best of our knowledge, this is the first multistage MMW PA with a low-loss built-in linearizer. Index Terms--Linearizer, millimeter-wave (MMW), monolithic microwave integrated circuit (MMIC), nonlinear, power amplifier (PA).

In this letter, we propose an ultralow-power transformer-based V-band receiver front-end using a 65-nm CMOS technology. Forward-body-bias and transformer-based positive-feedback topologies are utilized to enable its operation at a low drain bias of 0.3 V, while still ensuring its gain performance. A resistive ring mixer, with its advantage of zero-dc-power consumption, serves as the frequency down-converter of the system. The proposed receiver front-end demonstrates an 8.5-dB conversion gain and possesses the power-saving ability to use only 0.7 mW of dc-power consumption. [ABSTRACT FROM AUTHOR]

A 40-GHz variable gain amplifier (VGA) with 4-bit digital gain control and low phase variation is designed and fabricated on the 65-nm CMOS process. The digital gain control mechanism is achieved using the presented digital version current steering topology. The measured gain of the VGA is between 22 and 6 dB at 40 GHz with 16 different linear-in-decibel gain states. Using the proposed two-stage digital version current steering VGA phase compensation technique, the measured phase variation is 3.18° within a 16-dB gain control range (GCR) and the root mean square (rms) phase error is 0.89° at 40 GHz. [ABSTRACT FROM AUTHOR]

A transformer (TF)-based folded radial power splitting and binary power combining architecture is developed for fully integrated CMOS PA design in this paper. The proposed folded splitting and combining architecture has advantages of in-phase RF signal splitting/combining scheme, compact size, uniform dc distribution, and symmetric dc current supply/return path. A 5.3-GHz fully integrated PA using the developed splitting/combining architecture is fabricated on a standard 0.18- $\mu \text{m}$ CMOS technology. The CMOS PA transmits saturation power ($P_{\mathrm {sat}}$) of 31.3 dBm, output 1-dB compression point (OP1 dB) of 26.1 dBm, and power added efficiency (PAE) of 22% at 5.3 GHz. The measured small signal gain is 18.3 dB at 5.3 GHz. The EVM has been measured with IEEE 802.11ac WLAN modulated signals. Using the 20-MHz bandwidth OFDM 64-QAM modulated signal, the PA meets the WLAN EVM specification of 5.6% up to 20.4-dBm linear output power. To our knowledge, the CMOS PA achieves the highest $P_{\mathrm {sat}}$ and OP1 dB with decent PAE among other reported fully integrated CMOS PAs around 5 GHz to date. [ABSTRACT FROM AUTHOR]

A 3.5 GHz low insertion loss variation phase shifter has been designed and fabricated on standard 0.18‐μm CMOS process. To achieve over 360° continuously phase tuning range, the phase shifter consists of a switch type phase shifter (STPS) and a reflection type phase shifter (RTPS). The phase‐invertible variable attenuator (PIVA) topology which can provide two states with 180° phase‐shift while maintaining low amplitude imbalance is adopted. The RTPS provides over 189° continuously phase tuning. The experimental results show that the 3.5 GHz phase shifter demonstrates over 360° continuously phase tuning range with low insertion loss variation of 1 dB at 3.5 GHz. The maximum insertion loss is 13.5 dB at 3.5 GHz and the dc consumption is zero. The chip size is 1.08 mm × 0.82 mm. [ABSTRACT FROM AUTHOR]

Increasingly, people around the world embrace the benefits provided by smart phones, smart cars, and smart homes. The key difference between smart phones and traditional mobile phones is the user-defined functionality that enables individuals to transform their phones into music players, movie theaters, or personal workstations. Smart cars with video sensors, lidar sensors, or even millimeter-wave (mm-wave) radar may be autonomously driven. When more and more user-defined functions/sensor capabilities are built into RF integrated circuits (RFICs), they are known as smart RFICs. [ABSTRACT FROM AUTHOR]

Abstract: In this letter, a dual‐band class‐E CMOS power amplifier (PA) in 0.18‐μm CMOS process is presented. By using concurrent dual‐band impedance matching network, the proposed dual‐band PA can achieve high efficiency in a compact chip area. This dual‐band class‐E PA demonstrates the power gain ≥ 8.4 dB, Psat ≥ 21.4 dBm with power added efficiency ≥ 31% in a compact chip size of 0.5 mm2. This dual‐band class‐E PA achieves comparable power area density of 284.5 (mW/mm2) with other state‐of‐the‐art class‐E PAs at higher frequency. [ABSTRACT FROM AUTHOR]

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. [ABSTRACT FROM AUTHOR]

ABSTRACT This article presents a wideband phase-locked loop (PLL) front-end, which consists of a dual-core voltage-controlled oscillator (VCO) and a divide-by-four (D4) frequency divider in 90-nm CMOS technology. The switched inductors and varactor banks are used to enhance the tuning range of VCO. The D4 frequency divider is a body-biased injection-locked frequency divider (ILFD) cascoded with source-injection current mode logic (SICML) for wider locking range and lower power consumption. This PLL front-end demonstrates a 30.2% frequency tuning range (FTR) from 23.6 to 32 GHz and a phase noise of −101.22 dBc/Hz at 5.86 GHz with 1 MHz offset frequency. The output power is higher than −15 dBm among the operating bandwidth. The dc power consumption is 40.8 mW at 1.2 V and 1.5 V supply voltages. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1305-1309, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A K-band differential cross-coupled inductance- capacitance (LC) voltage-controlled oscillator (VCO) is implemented in 0.18-μm CMOS process. To accomplish high quality (Q) factor LC-tank at K-band, a slab inductor with high Q is adopted. The VCO can be tuned from 23.1 to 23.38 GHz and the core dc power consumption is 11.33 mW from 1 V power supply. The phase noise is −109.04 dBc/Hz at 1 MHz offset, and the calculated figure of merit (FoM) is −185.79 dBc/Hz. At low supply voltage mode of 0.65 V, the phase noise is −106.015 dBc/Hz at 1 MHz offset and the FoM is −189.76 dBc/Hz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:362-366, 2017 [ABSTRACT FROM AUTHOR]

A 12–32 GHz divide-by-2 (D2) injection-locked frequency divider (ILFD) is presented in this paper. First, the device ratio of the injection mixer and cross-coupled pair is optimized to achieve a wide locking range (LR). Then, the inductive peaking and forward-body-bias techniques are applied to the injection mixer to boost its transconductance and to enhance injection efficiency for further extension of the LR. Finally, the harmonic suppression technique is introduced to reduce the output harmonics. Using the aforementioned approaches, we successfully demonstrate a D2 ILFD implemented in the 90-nm low-power CMOS technology with a maximum LR of 90.9% at an injection power of 0 dBm. Even with the injection power as low as −10 dBm, the proposed ILFD maintains an LR of 32.9%. This ILFD consumes 2.4 mW with a supply voltage of 0.6 V in a chip size of 0.45 mm2. [ABSTRACT FROM PUBLISHER]

An innovative mixer architecture using gate- and drain-pumped with combining drain terminals of nMOS transistors is proposed to enhance IF and local oscillator (LO) operation bandwidths in 90-nm CMOS for astronomical application. With 0.6 mW of dc power, this mixer achieved peak conversion gains of −6.2, −6.1, −8.6, and −7.2 dB at LO frequencies of 30, 50, 60, and 90 GHz, respectively. At an LO power of 2.3 dBm and an LO frequency of 30 GHz, the IF 3-dB bandwidth is 26 GHz. When the LO power is 4.2 dBm at an LO frequency of 90 GHz, the mixer has an IF 3-dB bandwidth of 16 GHz. The IP1dB (input 1-dB gain compression) is better than 2 dBm from 30 to 90 GHz. The chip occupies an area of 0.389 mm2. Compared with other published works, this mixer demonstrates a breakthrough for extremely wide IF and LO bandwidths in low dc power consumption with high IP1dB. [ABSTRACT FROM PUBLISHER]

An ${{X}}$ -band fully integrated power amplifier (PA) has been designed and fabricated on CMOS technology. Utilizing a transformer-based folded radial power splitter and binary power combiner network, the CMOS PA delivers 29.6 dBm saturation power (${{P}}_{\mathbf {sat}}$) at 11 GHz. The measured gain is 11.2 dB, the output of 1-dB compression point (${{OP}}_{\mathbf {1\,dB}}$) is 28.2 dBm, and the peak power-added efficiency (PAE) is 15.5% at 11 GHz. To our knowledge, the PA achieves the highest ${{P}}_{\mathbf {sat}}$ and the highest ${{OP}}_{\mathbf {1\,dB}}$ among other reported CMOS PAs around ${{X}}$ -band to date. [ABSTRACT FROM AUTHOR]

ABSTRACT A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were −90.88 and −115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1534-1537, 2016 [ABSTRACT FROM AUTHOR]

A radial multiway power divider is used to distribute microwave signals to the next stages located radially around all directions. It has been a challenging task to implement a radial multiway power divider on a planar circuit board without sacrificing the bandwidth performance. In this letter, a radial four-way power divider with the proposed isolation network is presented. The isolation network, composed of several combined RLC and LC networks, plays the crucial role of making the radial layout style easy to realize, and meanwhile improves the output matching and port-to-port isolation. The background principle of the proposed topology and the guideline of designing the isolation network are provided. The fabricated radial four-way power divider results in the measured −20-dB output matching and isolation bandwidths as large as 35% and 65%, respectively, exhibiting the best bandwidth performance among all the published radial power dividers of the same type. [ABSTRACT FROM PUBLISHER]

ABSTRACT A Ku-band 3-bit switch-type phase shifter with low insertion loss, low magnitude variation, and low rms phase error is designed and fabricated on 0.15-μm pHEMT process. For all eight states, the insertion loss is 6.5 ± 1.5 dB from 10-14 GHz and the input return loss is >8.5 dB over 10-14 GHz. The phase shifter achieves a rms phase error of 2.2° and a rms amplitude error of 0.37 dB at 12 GHz with total chip size of 1.5 ×1 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:771-774, 2015 [ABSTRACT FROM AUTHOR]

An X -band half-watt fully integrated power amplifier (PA) using standard 0.18- \mu \text{m} 1P6M CMOS technology is presented in this letter. Utilizing an interweaved three-primary parallel combining transformer, the CMOS PA delivers 27.1 dBm of measured saturation output power ( P_{\mathbf {sat}}$ ) with 22.7% of power-added efficiency at 9 GHz from a 3.3-V power supply. The measured output 1-dB gain compression point (OP1 dB) is 24.2 dBm and the gain performance is 11.2 dB at 9 GHz. The chip size is $1.045 \times 0.84$ mm $^{{\mathbf {2}}}$ . To the best of our knowledge, the PA is the first half-watt CMOS PA with excellent power density at the $X$ -band. [ABSTRACT FROM PUBLISHER]

ABSTRACT In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA-III) applications in 0.18-pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:622-624, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A V-band variable gain amplifier (VGA) with wide gain control range, low phase variation, and low return loss variation is designed and implemented on 90-nm CMOS process. Utilizing a phase compensation capacitor at the common gate transistor and a source degeneration inductor at the common source transistor of the cascode configuration, the VGA achieves gain control range of 15.8 dB with only 6.9° transmission phase variation at 60 GHz via simple control mechanism. The maximum small signal gain is 15.8 dB at 60 GHz. In addition, the input/output return losses are insensitivity at different gain state of the VGA. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1946-1949, 2014 [ABSTRACT FROM AUTHOR]

An E-band high image-rejection sub-harmonic in-phase/quadrature (IQ) modulator for a high-order quadrature amplitude modulation (QAM) signal is designed and implemented on standard 65-nm CMOS technology. To maintain high image-rejection ratio of the IQ modulator over a wide bandwidth for high data-rate application, a load-insensitive analysis and a local oscillator (LO) broadband 45^\circ power splitter are proposed to achieve low amplitude and phase imbalanced structure. In addition, the doubly balanced sub-harmonic Gilbert-cell mixer with the advantages of good LO leakage suppression has been selected in the mixer design. The IQ modulator demonstrates a measured flat conversion gain of 0 \pm 1 dB from 55 to 85 GHz. The image rejection ratio is better than 40 dBc from 64 to 84 GHz. For millimeter-wave communication applications, the IQ modulator is integrated with a four-stage power amplifier to form a direct-conversion transmitter. The measured conversion gain of the transmitter is 33 dB and the measured saturated power is 11 dBm. Via high image rejection and good LO suppression of the modulator, a 1024-QAM modulated signal with a data rate of 500 Mb/s and 1.7% error vector magnitude is successfully demonstrated at 65 GHz. [ABSTRACT FROM PUBLISHER]

An ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed V-band mixer can operate at microwatt power consumption of 453 \mu\W and has an ultra low LO power of -\6 dBm. In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of \ 5.9\pm\ 1.5~\ dB and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and OP1 dB of -\9.2 dBm at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system. [ABSTRACT FROM AUTHOR]

An innovative on-chip 3-D power amplifier (PA) architecture for M-way power-combined CMOS PAs by using the proposed dual-radial symmetric architecture is presented. It provides design freedom of impedance selection of power device in transformer-based millimeter-wave PA design. This idea also makes distinguished breakthrough to the traditional 2-D PA architecture without compromising symmetry and compact size of layout. To demonstrate the feasibility of this idea, a 60-GHz PA is fabricated in 90-nm low-power CMOS process. It is also equipped with multi-mode operation. It achieves an output power of 18.5 dBm and a power-added efficiency of 10.2% with 1.2-V supply voltage. At 6-dB/10-dB power back-off operation, the drain efficiencies of power stage can be enhanced from 5.9%/2.4% to 11.9%/8%, respectively, by enabling the multi-mode operation. [ABSTRACT FROM AUTHOR]

A 57–64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2^\circ at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of +/-8.5 ps and an excellent insertion loss flatness of \pm0.8 dB for a specific phase-shifting state, across 57–64 GHz. For all 32 states, the insertion loss is 14.6 \pm 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86^\circ phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8^\circ at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is \pm0.8 dB over 57–64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the V-band switch-type phase shifter. [ABSTRACT FROM AUTHOR]

A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in \0.18-\mu\ m CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth. [ABSTRACT FROM AUTHOR]

A DC-20-GHz broadband and compact single-pole-quadruple-throw (SPQT) switch for Butler matrix switched beam smart antenna system application has been designed and fabricated on 0.15-μm GaAs pHEMT process. By adopting inductive high impedance transmission lines in series-shunt switch topology, the SPQT switch demonstrates an insertion loss of 1.25-3.53 dB from DC to 20 GHz, and the isolation is higher than 22 dB with a compact chip size of 1.5 mm2. The measured output 1 dB compression point (OP 1 dB) is 16 dBm at 12 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2023-2026, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26993 [ABSTRACT FROM AUTHOR]

Two \mbi V-band low-noise amplifiers (LNAs) with excellent linearity and noise figure (NF) using 90-nm CMOS technology are demonstrated in this paper, employing parasitic-insensitive linearization topologies, i.e., cascode and common source, for comparative purposes. To improve the linearity without deteriorating the NF, the 54–69-GHz cascode LNA is linearized by the body-biased post-distortion, and the 58–65-GHz common-source LNA is linearized by the distributed derivative superposition. Using these parasitic-insensitive linearization methods at millimeter-wave frequency, the cascode LNA can achieve an IIP{\bf 3} of 11 dBm and an NF of 3.78 dB at 68.5 GHz with a gain of 13.2 dB and 14.4-mW dc power. The common-source LNA has an IIP{\bf 3} of 0 dBm and an NF of 4.1 dB at 64.5 GHz with a gain of 11.3 dB and 10.8-mW dc power. To the best of our knowledge, the proposed cascode LNA has up to 11-dBm IIP{\bf 3} performance and the highest figure-of-merit of 156.2, among all reported V-band LNAs. [ABSTRACT FROM AUTHOR]

A new doubly balanced drain-pumped topology for CMOS passive mixer design is proposed in this paper. In the efforts to improve the conversion loss of passive balanced mixers, the CMOS drain-pumped topology is employed. In addition, the doubly balanced architecture with the advantages of good port-to-port isolations has been combined with the CMOS drain mixer design. For the broad bandwidth and the flatness of the conversion loss, a wideband matching technique using a broadband Marchand balun network is analyzed and successfully implemented in the mixer design. This mixer is fabricated in standard 90-nm CMOS technology. According to experiment results, the mixer has a measured conversion loss of \7.5\pm \1.5∼\ dB from 33 to 58 GHz. Based on the double-balanced architecture, the local oscillator (LO)-to-RF and LO-to-IF isolations are better than 42.7 and 51.5 dB, respectively. The mixer consumes zero dc power with a compact size of 0.55\,\times \,0.52 \ mm^2. To the best of our knowledge, this paper presents the first CMOS drain mixer using doubly balanced topology. [ABSTRACT FROM AUTHOR]

In this paper, a pair of broadband, low-LO-power, low-dc-power, and high-speed up/down-conversion ring mixers are presented for multistandard millimeter-wave (MMW) radio applications. By employing a weak inversion biasing technique, the ring mixer can operate at a low LO drive level and low dc power while maintaining reasonable conversion gain performance. In addition, an IF transimpedance amplifier (TIA) buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW wireless Gigabit transmission. Using a 90-nm CMOS low-power process, the up-/down-conversion ring mixers are designed and fabricated based on the presented topology. The down-conversion ring mixer and up-conversion ring mixer exhibit flat measured conversion gain of -\1 \pm \2 dB and \0 \pm \2 dB from 40 to 110 GHz and 40 to 108 GHz, respectively. After biasing the transistors of the ring mixer core at weak inversion region, the presented down-conversion and up-conversion ring mixers can operate at low LO drive power, -2 and 0 dBm, respectively, even up to 100 GHz. For MMW wireless gigabit communication, gigabit binary phase-shift keying modulation signal test is successfully performed through a direct-conversion system in this work. The presented ring mixers are suitable for 60-GHz wireless personal area network, E-band (71–76 GHz, 81–86 GHz, and 92–95 GHz) wireless fiber, and 77-GHz anti-collision radar applications. [ABSTRACT FROM AUTHOR]

In this paper, W-band flip-chip-assembled CMOS chip modules with transition compensation are presented, a three-stage amplifier, a balanced amplifier, and a down-converted Gilbert-cell subharmonic mixer are included in the chip set. The flip-chip process on ceramic integrated passive devices (CIPD) with a bump size of 30 \mum \,\times\,30 \mum \,\times\,27 \mum is developed for millimeter-wave applications. Without the flip-chip transition compensation, the frequency of the return loss of each chip is shifted, which deviates from the bare die measurement results. By applying the compensation network in the transition, the dips of the return loss are tuned back closer to the bare die measurement results. Moreover, a W-band amplifier flip-chip-assembled with a CPW-fed Yagi–Uda antenna on a CIPD and a W-band flip-chip-assembled receiver are presented for SiP integration. The effect of dicing edge variation is also included in the flip-chip model to achieve reasonable agreement between simulated and measured scattering parameters. To the best of our knowledge, this is the first demonstration of a CMOS chip set with flip-chip interconnects in the W-band for a system-in-package. [ABSTRACT FROM AUTHOR]

A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-\mu\ m CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism. [ABSTRACT FROM AUTHOR]

A 53-67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57-64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop system. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1386-1389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25989 [ABSTRACT FROM AUTHOR]

In this paper, low-voltage evolution and high-speed operation mixer design are presented for millimeter-wave (MMW) CMOS in-phase/quadrature (I/Q) modulator and demodulator. The modified Gilbert-cell mixer architecture, which eliminates the three-level transistors stacking in the conventional Gilbert-cell mixer, can operate at a reduced supply voltage while maintaining reasonable performance. In addition, IF transimpedance amplifier buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW gigabit wireless transmission link applications. Using a 0.13-\mum CMOS process, the I/Q modulator and demodulator formed with the modified Gilbert-cell mixers are demonstrated at the MMW. Under 1.2-V standard supply voltage, the modulator and demodulator exhibit excellent conversion gain (CG) flatness of -\3.5 \pm \1.5 dB and -\3 \pm \1.5 dB from 41 to 69.5 GHz and 31 to 69 GHz, respectively. For 60-GHz wireless personal area network applications, \pi/4 differential quadrature phase-shift keying, 16 quadrature amplitude modulation, and binary phase-shift keying modulation signal tests are successfully performed through the direct-conversion system. The results show that the presented monolithic microwave integrated circuits can operate at low-voltage and low-power while providing good CG and high data rate, even up to multigigabit. [ABSTRACT FROM AUTHOR]

In this letter, the bowtie-radial and balanced dual-radial PA architectures are proposed to combine 4-way and 8-way power units. Moreover, they also make breakthrough on the power area density (PAD) performances of N-way combined PAs. These two CMOS PAs can both achieve the highest output power of 26.1 dBm at 23.5 GHz with PAD of 635 mW/mm^2 and 23 dBm at 60 GHz with PAD of 277 mW/mm^2, respectively. [ABSTRACT FROM PUBLISHER]

An ultra-low-power transformer-based K-band receiver front-end is implemented in a 65 nm CMOS technology. For noise and input matching, a gate-to-source transformer-feedback technique is applied to the first-stage of the LNA. A transformer-based gain-boosting feedback technique is adopted in the second-stage of the LNA for further gain enhancement without additional dc power. Several transformers are utilized for inter-stage matching of the LNA and for single-to-differential LO/RF baluns of the ring mixer. By using forward-body-bias technique, the LNA operates at 0.33 V supply. For low-power receiver, a resistive ring mixer is adopted. The receiver demonstrates a 12.5 dB conversion gain (CG) and a 5.7 dB double-side band NF at IF frequency of 100 MHz with LO power of -10 dBm while consuming only 683 \muW. To the best of our knowledge, the receiver demonstrates the lowest dc power consumption among recently reported K-band CMOS receiver. [ABSTRACT FROM PUBLISHER]

A digital-calibrated isolator for radar is proposed to improve transmitter-to-receiver isolation in this letter. The proposed isolator consists of feedforward and digital-calibrated circuits to cancel the transmitter-to-receiver leakage power. The proposed isolator is implemented in 0.18-\mum CMOS technology which shows 27.3 dB isolation while consuming 13.5 mW dc power. The OP1\,dB of the transmitter-to-antenna is better than +13.5 dBm. [ABSTRACT FROM PUBLISHER]

In this letter, a low-voltage and low-power 3.5-GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18-μm MS/RF complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. The complementary current-reused topology is utilized to achieve low dc power consumption while maintaining reasonable gain performance. Consuming 1.38 mW dc power from 0.6 V supply, the LNA achieves a small signal gain of 16.09 dB and a noise figure of 4.702 dB at 3.5 GHz. Compared with previously reported LNA, the MMIC has excellent FOM performance. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:145-147, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26463 [ABSTRACT FROM AUTHOR]

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1~dB of 7.3 dBm from 1.2 V supply. After linearization, the OP1~dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP1~dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB. [ABSTRACT FROM PUBLISHER]