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A 224-448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process.
- Source :
-
Microwave & Optical Technology Letters . Jul2017, Vol. 59 Issue 7, p1750-1755. 5p. 6 Diagrams, 1 Chart, 3 Graphs. - Publication Year :
- 2017
-
Abstract
- A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 08952477
- Volume :
- 59
- Issue :
- 7
- Database :
- Academic Search Index
- Journal :
- Microwave & Optical Technology Letters
- Publication Type :
- Academic Journal
- Accession number :
- 123088139
- Full Text :
- https://doi.org/10.1002/mop.30620