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In this paper, for the first time, a dual-metal double-gate with oxide stack (low-k/high-k) junctionless MOSFET (DM-DG-OS JL-MOSFET) based sensor device has been explored for finding its suitability in detecting charged nanometric biospecies under dry environment condition. The analysis of sensing performance of the device for such detection is made in terms of the absolute and the relative changes in threshold voltage (Vth). The influence of work-function difference of dual metal gate electrodes, along with the position of nanogap cavity, on the sensing metrics has been thoroughly investigated. The impact of the cavity dimensions on sensitivity parameters of the projected device is also studied. An optimum cavity dimension, for channel length (Lch) of 1 µm, is found to be 400 nm × 10 nm in yielding measurable sensitivity parameters for charged nanometric biospecies detection. A device with 1-µm Lch exhibits superior sensitivity performance in terms of percentage improvements in the absolute and the relative changes in Vth for a higher drain-side gate-metal work-function (ϕM2) relative to source-side gate-metal work-function (ϕM1) for source-side cavity (400 nm × 10 nm) compared to the case when ϕM1>ϕM2 and the cavity is located near drain-side. Respective performance enhancements are found to be 30.7% and 74% for detection of negatively charged nanometric biospecies. The sensor devices with Lch of 50 nm show the similar trend. [ABSTRACT FROM AUTHOR]

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for LG = 13 nm corresponding to the (recent) state-of-the-art technology node for the "More Moore" options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (VT), average subthreshold swing (SSavg), OFF-state current (IOFF), ION/IOFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in VT, IOFF, ION/IOFF, and SSavg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of LG (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SSavg, a reduction of about 1 decade and 3 decades in IOFF, and an improvement of nearly 1 decade and 2 decades in ION/IOFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of IOFF, ION/IOFF and SSavg with the lowest possible shifts in VT (∼ 0%) and SSavg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, a pH-sensor using an In0.53Ga0.47As based ion-sensitive-field-effect-transistor (ISFET) is proposed to show its superior sensing performance as compared to its equivalent Si counterpart. Extensive numerical analyses of the proposed In0.53Ga0.47As-ISFET are performed in order to extract various sensitivity parameters, e.g., threshold voltage sensitivity (Vth-sensitivity), ON-current sensitivity (ION-sensitivity), and gate-voltage sensitivity (VGS-sensitivity), followed by the performance comparison with the equivalent Si-ISFET sensor, the experimental data of which are used for calibration of the simulation framework. The obtained results show that the long-channel In0.53Ga0.47As-ISFET sensor exhibits 10, 962%, and 9.75% improvement for Vth-sensitivity, ION-sensitivity, and VGS-sensitivity respectively, compared to the equivalent Si-ISFET-sensor at supply voltage of 0.5 V. Furthermore, our findings reveal that a down-scaled ISFET, for instance, a 40-nm-In0.53Ga0.47As-ISFET sensor shows 26, 213% and 10.5% improvement of Vth-sensitivity, ION-sensitivity, and VGS-sensitivity, respectively at the same supply voltage compared to its equivalent Si ISFET sensor. [ABSTRACT FROM AUTHOR]

The performance of a sub-100-nm gate-length p-channel TFET-based biosensor (pTFET-BS) covering a wide range of protein-molecules is presented, and for the first time the optimized length-range of the nanogap cavity of the biosensor through the modeling of the presence of discrete number of biomolecules, followed by shift-saturation in corresponding transfer characteristics, is reported in this paper. Furthermore, considering a real time process related over-etching effect, a variability study on the random position of the conjugated protein-molecules within the cavity, followed by a corresponding statistical analysis, are carried out. Results show that 85% to 95% (65–85%) of total combinations produce beyond 50% of maximum Vth- (IDS-) sensitivity values, ensuring stability and hence reliability of the proposed sensor device. [ABSTRACT FROM AUTHOR]

In this article, for the first time, the performance of a double-hetero-gated-dielectric-modulated tunnel FET (DHGDM-TFET) biosensor device, having channel length (Lch) of 50 nm, is thoroughly investigated in terms of threshold voltage-(VTH-), subthreshold swing- (SS-), ON-current- (ION-), and OFF-current- (IOFF-) sensitivity parameters, in order to find its suitability in successful detection and identification of different biomolecules. The investigation is further extended to the optimization of the proposed sensor device, against cavity length (LCavity) and misalignment effect between the cavity and high-k dielectric, underneath the cavity of the sensor device. It is found that our proposed biosensor device works at its optimum with LCavity = 10 nm, while the cavity is perfectly aligned with the underneath high-k of the device. Furthermore, a comparison of our proposed device is performed against its equivalent high-k only and SiO2 only TFET-based biosensors. For each aforementioned sensitivity parameter, it is found that our proposed DHGDM-TFET biosensor device outperforms the rest two devices, proving the superiority in sensing action. [ABSTRACT FROM AUTHOR]

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( Lg ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance gm , transconductance generation factor, and voltage gain Av exhibit significant improvement when a spacer of high dielectric constant k , such as 25, and small length L_{\textrm {sp}} , such as 5 nm, are used for both L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower k$ and larger L_{\textrm {sp}} of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes. [ABSTRACT FROM AUTHOR]

We propose a novel hybrid CMOS comprising a Si-channel pMOSFET and an asymmetric InP/InGaAs nMOSFET in the nanometer regime for analog applications. The performance of such a CMOS is evaluated in terms of voltage gain and gain-bandwidth (GBW) product at two different channel lengths ( Lg ), 50 and 30 nm, using extensive device simulations. Our investigations reveal that the maximum gain of the hybrid CMOS inverter is improved by 37.5% and 92.1% for asymmetric In0.75Ga0.25As nMOS devices with InP drain at Lg = 30 nm for W\!p/Wn = 3 and 8, respectively, as compared with an equally sized Si inverter having W\!p/Wn = 3 . In addition, GBW product of hybrid CMOS (HAS3) comprising asymmetric In0.75Ga0.25As nMOSFET with InP source and Si pMOSFET is increased by 148.1% and 260.4% at Lg = 30 and 50 nm, respectively, for Wp/Wn = 3 , compared with its Si counterpart. Furthermore, the HAS3 device yields the highest GBW peak, unity current gain frequency, and maximum oscillation frequency as compared with other hybrid and Si CMOS devices at Lg=30 and 50 nm. [ABSTRACT FROM AUTHOR]

CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25 As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for Dit exceeding 5 × 1012eV−1 · cm−2. [ABSTRACT FROM PUBLISHER]

A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices. [ABSTRACT FROM AUTHOR]

MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance (gm), transconductance-to-drain-current ratio (gm/ID), drain resistance (RO), intrinsic gain, and unity-gain cutoff frequency (fT) are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications. [ABSTRACT FROM AUTHOR]