Search

Convolutional neural networks (CNNs) often extract similar features from successive video frames due to having identical appearances. In contrast, conventional CNNs for video recognition process individual frames with a fixed computational effort. Each video frame is independently processed, resulting in numerous redundant computations and an inefficient use of limited energy resources, particularly for edge computing applications. To alleviate the high energy requirements associated with video frame processing, this article presented similarity-aware CNNs that recognize similar feature pixels across frames and avoid computations on them. First, with a loss of less than 1% in recognition accuracy, a proposed similarity-aware quantization technique increases the average number of unchanged feature pixels across frame pairs by up to 85%. Then, a proposed similarity-aware dataflow improves energy consumption by minimizing redundant computations and memory accesses across frame pairs. According to simulation experiments, the proposed dataflow decreases the energy consumed by video frame processing by up to 30%. [ABSTRACT FROM AUTHOR]

Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a $32 \times 32$ matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor. [ABSTRACT FROM AUTHOR]

Heterogeneous multi-processor system-on-chip (MPSoC) smartphones are required to offer increasing performance and user quality-of-experience (QoE), despite comparatively slow advances in battery technology. Approaches to balance instantaneous power consumption, performance and QoE have been reported, but little research has considered how to perform longer-term budgeting of resources across a complete battery discharge cycle. Approaches that have considered this are oblivious to the daily variability in the user's desired charging time-of-day (plug-in time), resulting in a failure to meet the user's battery life expectations, or else an unnecessarily over-constrained QoE. This paper proposes QUAREM, an adaptive resource management approach in mobile MPSoC platforms that maximises QoE while meeting battery life expectations. The proposed approach utilises a model that learns and then predicts the dynamics of the energy usage pattern and plug-in times. Unlike state-of-the-art approaches, we maximise the QoE through the adaptive balancing of the battery life and the quality of service (QoS) for the duration of the battery discharge. Our model achieves a good degree of accuracy with a mean absolute percentage error of 3.47% and 2.48% for the energy demand and plug-in times, respectively. Experimental evaluation on an off-the-shelf commercial smartphone shows that QUAREM achieves the expected battery life of the user within 20-25% energy demand variation with little or no QoE degradation. [ABSTRACT FROM AUTHOR]

Recent advances in low-power computing enable energy harvesting-powered devices, even in energy scarce conditions. This reduces the reliance on batteries in Internet of Things devices, reducing the cost and enabling new application domains. However, energy scarcity requires devices to operate intermittently, with minimal stored energy and where high-cost radio frequency (RF) communication dominates the power consumption, so transceivers are disabled most of the time. For deployment in challenging environments without high capability neighboring devices, a peer-to-peer topology for intermittently powered devices is required. To remove the requirement for high capability devices, we categorize four receiver types harnessing RF power transfer for a wake-up from other intermittently powered devices. This mesh networking of homogeneous nodes could enable applications where high power coordinators are undesirable or impossible. In this article, we identify the cross-layer challenges of mesh networking with intermittently powered devices and we describe the node receiver hardware required for peer-to-peer networking with intermittently powered devices. We conclude with a case study of transceiver power consumption in this context. [ABSTRACT FROM AUTHOR]

Batteryless energy-harvesting devices promise to deliver a sustainable Internet of Things. Intermittent computing is an emerging area, where the application forward progress, i.e., computation beneficial to the progress of the active application, is maintained by saving the volatile computing state into nonvolatile memory before power interruptions, and restored afterward. Conventional intermittent computing approaches typically minimize energy storage to reduce device dimensions and interruption periods, but this can result in high state-saving and -restoring overheads and impede forward progress. In this article, we argue that adding a small amount of energy storage can significantly improve the forward progress. We develop an intermittent computing model that accurately estimates the forward progress, with an experimentally validated mean error of 0.5%. Using this model, we show that sizing energy storage can improve the forward progress by up to 65% with a constant current supply, and 43% with real-world photovoltaic sources. An extension to this approach, which uses a cost function to trade off the energy storage size against forward progress, can save 83% of capacitor volume and 91% of interruption periods while maintaining 93% of the maximum forward progress. [ABSTRACT FROM AUTHOR]

Emerging applications for Internet of Things (IoT) devices demand smaller mass, size, and cost whilst increasing capability and reliability. Energy harvesting can provide power to these ultra-constrained devices, but introduces unreliability, unpredictability, and intermittency. Schemes for wireless sensors without batteries or supercapacitors overcome intermittency through saving system state into nonvolatile memory before the supply drops below the minimum operating voltage, termed transient, or intermittent computing. However, this introduces significant time and energy overheads. This article presents two schemes that significantly reduce these overheads: entering a sleep mode to avoid saving state and utilizing direct memory access (DMA) when state saves are required. Time and energy previously wasted on state saves can instead be used to perform useful computation, termed “forward progress.” We practically validate the proposed approaches across a range of energy sources and IoT benchmarks and demonstrate up to 46.8% and 40.3% increase in forward progress and up to 91.1% and 85.6% reduction in overheads for each scheme, respectively. [ABSTRACT FROM AUTHOR]

Mobile devices are limited in mass and volume, reducing the viability of active device cooling implementations. This requires the use of less effective passive techniques to maintain device skin temperature levels. Application performance demands on a modern mobile device are driven by sustained performance workloads, such as 3-D games, virtual, and augmented reality. Mobile system-on-chips (SoCs) have corresponding increases in performance through both architectural changes and frequency of operation increases, which has resulted in the peak power consumption exceeding the sustainable thermal envelope defined by device skin temperature requirements. Existing thermal throttling techniques mitigate this by capping the frequency of operation of the SoC. Through experimentation with a modern smartphone platform using sequences from real-world applications, we demonstrate in this letter that frequency capping (FC) can have a significant effect on the performance of interactive applications, increasing the number of frame rate defects by up to 146%. We propose task utilization scaling, a new lever for thermal throttling, which scales performance for critical interactive periods by the same factor as noncritical periods. Experiments demonstrate that the proposed approach can result in a decrease in frame rate defects of up to 18% compared with FC or a skin temperature reduction of up to 2°C. [ABSTRACT FROM AUTHOR]

Modern heterogeneous multicore systems, containing various types of cores, are increasingly dealing with concurrent execution of dynamic application workloads. Moreover, the performance constraints of each application vary, and applications enter/exit the system at any time. Existing approaches are not efficient in such dynamic scenarios, especially if applications are unknown, as they require extensive offline application analysis and do not consider the runtime execution scenarios (application arrival/completion, and workload and performance variations) for runtime management. To address this, we present AdaMD, an adaptive mapping and dynamic voltage and frequency scaling (DVFS) approach for improving energy consumption and performance. The key feature of the proposed approach is the elimination of dependency on offline profiled results while making runtime decisions. This is achieved through a performance prediction model having a maximum error of 7.9% lower than the previously reported model and a mapping approach that allocates processing cores to applications while respecting performance constraints. Furthermore, AdaMD adapts to runtime execution scenarios efficiently by monitoring the application status, and performance/workload variations to adjust the previous DVFS settings and thread-to-core mappings. The proposed approach is experimentally validated on the Odroid-XU3, with various combinations of diverse multithreaded applications from PARSEC and SPLASH benchmarks. Results show energy savings of up to 28% compared to the recently proposed approach while meeting performance constraints. [ABSTRACT FROM AUTHOR]

Transient computing enables application execution to be performed despite power outages. Although it handles the non-deterministic nature of energy harvesting (EH), sensor systems envisioned by the IoT seek more cost- and volume-effective solutions, which are better tailored to application requirements. Additionally, a major drawback of transient computing, keeping track of time, hinders its widespread adoption in the IoT. To overcome these challenges, this paper proposes a control flow for sensor systems by combining two state-of-the-art transient computing schemes in an energy-aware manner, underpinned by a strategy for timekeeping. It enables application execution to be reliably performed even under the most severe EH conditions, with an improved cost and volume efficiency, i.e., smaller energy storage. Benefiting from the combination of the two schemes, dynamic adjustment of system performance is achieved, while the time is accurately tracked. To illustrate the applicability of this flow to actual sensor systems, two case studies: a bicycle trip computer and a step counter, are presented. Empirical results reveal that, even with a tiny amount of energy harvested ($\simeq$ tens of $\mu \text{J}$), our proposed approach can meet application requirements with smaller storage, i.e., 40% and 66% reduction in required capacitance for the presented case studies. [ABSTRACT FROM AUTHOR]

Heterogeneous Mobile System-on-Chips (SoCs) containing CPU and GPU cores are becoming prevalent in embedded computing, and they need to execute applications concurrently. However, existing run-time management approaches do not perform adaptive mapping and thread-partitioning of applications while exploiting both CPU and GPU cores at the same time. In this paper, we propose an adaptive mapping and thread-partitioning approach for energy-efficient execution of concurrent OpenCL applications on both CPU and GPU cores while satisfying performance requirements. To start execution of concurrent applications, the approach makes mapping (number of cores and operating frequencies) and partitioning (distribution of threads between CPU and GPU) decisions to satisfy performance requirements for each application. The mapping and partitioning decisions are made by having a collaboration between the CPU and GPU cores’ processing capabilities such that balanced execution can be performed. During execution, adaptation is triggered when new application(s) arrive, or an executing one finishes, that frees cores. The adaptation process identifies a new mapping and thread-partitioning in a similar collaborative manner for remaining applications provided it leads to an improvement in energy efficiency. The proposed approach is experimentally validated on the Odroid-XU3 hardware platform with varying set of applications. Results show an average energy saving of 37%, compared to existing approaches while satisfying the performance requirements. [ABSTRACT FROM AUTHOR]

Current multicore platforms contain different types of cores, organized in clusters (e.g., ARM’s big.LITTLE). These platforms deal with concurrently executing applications, having varying workload profiles and performance requirements. Runtime management is imperative for adapting to such performance requirements and workload variabilities and to increase energy and temperature efficiency. Temperature has also become a critical parameter since it affects reliability, power consumption, and performance and, hence, must be managed. This paper proposes an accurate temperature prediction scheme coupled with a runtime energy management approach to proactively avoid exceeding temperature thresholds while maintaining performance targets. Experiments show up to 20% energy savings while maintaining high-temperature averages and peaks below the threshold. Compared with state-of-the-art temperature predictors, this paper predicts 35% faster and reduces the mean absolute error from 3.25 to 1.15 °C for the evaluated applications’ scenarios. [ABSTRACT FROM AUTHOR]

Recent research has looked to supplement or even replace the batteries in embedded computing systems with energy harvesting, where energy is derived from the device's environment. However, such supplies are generally unpredictable and highly variable, and hence systems typically incorporate large external energy buffers (e.g., supercapacitors) to sustain computation; however, these pose environmental issues and increase system size and cost. This article proposes Momentum, a general power-neutral methodology, with intrinsic system-wide maximum power point tracking, that can be applied to a wide range of different computing systems, where the system dynamically scales its performance (and hence power consumption) to optimize computational progress depending on the power availability. Momentum enables the system to operate around an efficient operating voltage, maximizing forward application execution, without adding any external tracking or control units. This methodology combines at runtime (1) a hierarchical control strategy that utilizes available power management controls (such as dynamic voltage and frequency scaling, and core hot-plugging) to achieve efficient power-neutral operation; (2) a software-based maximum power point tracking scheme (unlike existing approaches, this does not require any additional hardware), which adapts the system power consumption so that it can work at the optimal operating voltage, considering the efficiency of the entire system rather than just the energy harvester; and (3) experimental validation on two different scales of computing system: a low power microcontroller (operating from the already-present 4.7µF decoupling capacitance) and a multi-processor system-on-chip (operating from 15.4mF added capacitance). Experimental results from both a controlled supply and energy harvesting source show that Momentum operates correctly on both platforms and exhibits improvements in forward application execution of up to 11% when compared to existing power-neutral approaches and 46% compared to existing static approaches. [ABSTRACT FROM AUTHOR]

Energy harvesting sensor systems typically incorporate energy buffers (e.g., rechargeable batteries and supercapacitors) to accommodate fluctuations in supply. However, the presence of these elements limits the miniaturization of devices. In recent years, researchers have proposed a new paradigm, transient computing, where systems operate directly from the energy harvesting source and allow computation to span across power cycles, without adding energy buffers. Various transient computing approaches have addressed the challenge of power intermittency by retaining the processor's state using non-volatile memory. However, no generic approach has yet been proposed to retain the state of peripherals external to the processing element. This paper proposes RESTOP, flexible middleware which retains the state of multiple external peripherals that are connected to a computing element (i.e., a microcontroller) through protocols such as SPI or I2C. RESTOP acts as an interface between the main application and the peripheral, which keeps a record, at run-time, of the transmitted data in order to restore peripheral configuration after a power interruption. RESTOP is practically implemented and validated using three digitally interfaced peripherals, successfully restoring their configuration after power interruptions, imposing a maximum time overhead of 15% when configuring a peripheral. However, this represents an overhead of only 0.82% during complete execution of our typical sensing application, which is substantially lower than existing approaches. [ABSTRACT FROM AUTHOR]

This article investigates the use of many-core systems to execute the disparity estimation algorithm, used in stereo vision applications, as these systems can provide flexibility between performance scaling and power consumption. We present a learning-based runtime management approach that achieves a required performance threshold while minimizing power consumption through dynamic control of frequency and core allocation. Experimental results are obtained from a 61-core Intel Xeon Phi platform for the aforementioned investigation. The same performance can be achieved with an average reduction in power consumption of 27.8% and increased energy efficiency by 30.04% when compared to Dynamic Voltage and Frequency Scaling control alone without runtime management. [ABSTRACT FROM AUTHOR]

Heterogeneous multi-processors are designed to bridge the gap between performance and energy efficiency in modern embedded systems. This is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best setting for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance.We develop a simulation methodology that can 1) isolate the hardware effects of migrations from the software, 2) directly compare the performance of different core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with little performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside buffer that matches performance and efficiency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance benefits without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without affecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or better system operation without having to aggressively share the entire memory system or to revert to migration periods finer than 100k instructions. [ABSTRACT FROM AUTHOR]

Heterogeneous Multi-Processor Systems-on-Chips (MPSoCs) containing CPU and GPU cores are typically required to execute applications concurrently. However, as will be shown in this paper, existing approaches are not well suited for concurrent applications as they are developed either by considering only a single application or they do not exploit both CPU and GPU cores at the same time. In this paper, we propose an energyefficient run-time mapping and thread partitioning approach for executing concurrent OpenCL applications on both GPU and GPU cores while satisfying performance requirements. Depending upon the performance requirements, for each concurrently executing application, the mapping process finds the appropriate number of CPU cores and operating frequencies of CPU and GPU cores, and the partitioning process identifies an efficient partitioning of the applications' threads between CPU and GPU cores. We validate the proposed approach experimentally on the Odroid-XU3 hardware platform with various mixes of applications from the Polybench benchmark suite. Additionally, a case-study is performed with a real-world application SLAMBench. Results show an average energy saving of 32% compared to existing approaches while still satisfying the performance requirements. [ABSTRACT FROM AUTHOR]

Modern mobile and embedded devices are required to be increasingly energy-efficient while running more sophisticated tasks, causing the CPU design to become more complex and employ more energy-saving techniques. This has created a greater need for fast and accurate power estimation frameworks for both run-time CPU energy management and design-space exploration. We present a statistically rigorous and novel methodology for building accurate run-time power models using performance monitoring counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Our robust model formulation reduces multicollinearity, allows separation of static and dynamic power, and allows a 100\times reduction in experiment time while sacrificing only 0.6% accuracy. We present a statistically detailed evaluation of our model, highlighting and addressing the problem of heteroscedasticity in power modeling. We present software implementing our methodology and build power models for ARM Cortex-A7 and Cortex-A15 CPUs, with 3.8% and 2.8% average error, respectively. We model the behavior of the nonideal CPU voltage regulator under dynamic CPU activity to improve modeling accuracy by up to 5.5% in situations where the voltage cannot be measured. To address the lack of research utilizing PMC data from real mobile devices, we also present our data acquisition method and experimental platform software. We support this paper with online resources including software tools, documentation, raw data and further results. [ABSTRACT FROM AUTHOR]

Energy harvesters are being used to power autonomous systems, but their output power is variable and intermittent. To sustain computation, these systems integrate batteries or supercapacitors to smooth out rapid changes in harvester output. Energy storage devices require time for charging and increase the size, mass, and cost of systems. The field of transient computing moves away from this approach, by powering the system directly from the harvester output. To prevent an application from having to restart computation after a power outage, approaches such as Hibernus allow these systems to hibernate when supply failure is imminent. When the supply reaches the operating threshold, the last saved state is restored and the operation is continued from the point it was interrupted. This paper proposes Hibernus++ to intelligently adapt the hibernate and restore thresholds in response to source dynamics and system load properties. Specifically, capabilities are built into the system to autonomously characterize the hardware platform and its performance during hibernation in order to set the hibernation threshold at a point which minimizes wasted energy and maximizes computation time. Similarly, the system auto-calibrates the restore threshold depending on the balance of energy supply and consumption in order to maximize computation time. Hibernus++ is validated both theoretically and experimentally on microcontroller hardware using both synthesized and real energy harvesters. Results show that Hibernus++ provides an average 16% reduction in energy consumption and an improvement of 17% in application execution time over state-of-the-art approaches. [ABSTRACT FROM PUBLISHER]

Applications executed on multicore embedded systems interact with system software [such as the operating system (OS)] and hardware, leading to widely varying thermal profiles which accelerate some aging mechanisms, reducing the lifetime reliability. Effectively managing the temperature therefore requires: 1) autonomous detection of changes in application workload and 2) appropriate selection of control levers to manage thermal profiles of these workloads. In this paper, we propose a technique for workload change detection using density ratio-based statistical divergence between overlapping sliding windows of CPU performance statistics. This is integrated in a runtime approach for thermal management, which uses reinforcement learning to select workload-specific thermal control levers by sampling on-board thermal sensors. Identified control levers override the OSs native thread allocation decision and scale hardware voltage–frequency to improve average temperature, peak temperature, and thermal cycling. The proposed approach is validated through its implementation as a hierarchical runtime manager for Linux, with heuristic-based thread affinity selected from the upper hierarchy to reduce thermal cycling and learning-based voltage–frequency selected from the lower hierarchy to reduce average and peak temperatures. Experiments conducted with mobile, embedded, and high performance applications on ARM-based embedded systems demonstrate that the proposed approach increases workload change detection accuracy by an average 3.4\times , reducing the average temperature by 4 °C–25 °C, peak temperature by 6 °C–24 °C, and thermal cycling by 7%–35% over state-of-the-art approaches. [ABSTRACT FROM AUTHOR]

Embedded systems execute applications with varying performance requirements. These applications exercise the hardware differently depending on the computation task, generating varying workloads with time. Energy minimization with such workload and performance variations within (intra) and across (inter) applications is particularly challenging. To address this challenge, we propose an online approach, capable of minimizing energy through adaptation to these variations. At the core of this approach is a reinforcement learning algorithm that suitably selects the appropriate voltage/frequency scaling (VFS) based on workload predictions to meet the applications’ performance requirements. The adaptation is then facilitated and expedited through learning transfer, which uses the interaction between the application, runtime, and hardware layers to adjust the VFS. The proposed approach is implemented as a power governor in Linux and extensively validated on an ARM Cortex-A8 running different benchmark applications. We show that with intra- and inter-application variations, our proposed approach can effectively minimize energy consumption by up to 33% compared to the existing approaches. Scaling the approach to multicore systems, we also demonstrate that it can minimize energy by up to 18% with 2\times reduction in the learning time when compared with an existing approach. [ABSTRACT FROM AUTHOR]

Transient computing systems do not have energy storage, and operate directly from energy harvesting. These systems are often faced with the inherent challenge of low-current or transient power supply. In this paper, we propose “power-neutral” operation, a new paradigm for such systems, whereby the instantaneous power consumption of the system must match the instantaneous harvested power. Power neutrality is achieved using a control algorithm for dynamic frequency scaling, modulating system performance gracefully in response to the incoming power. Detailed system model is used to determine design parameters for selecting the system voltage thresholds where the operating frequency will be raised or lowered, or the system will be hibernated. The proposed control algorithm for power-neutral operation is experimentally validated using a microcontroller incorporating voltage threshold-based interrupts for frequency scaling. The microcontroller is powered directly from real energy harvesters; results demonstrate that a power-neutral system sustains operation for 4%–88% longer with up to 21% speedup in application execution. [ABSTRACT FROM AUTHOR]

Modern embedded systems execute applications, which interact with the operating system and hardware differently depending on the type of workload. These cross-layer interactions result in wide variations of the chip-wide thermal profile. In this article, a reinforcement learning-based runtime manager is proposed that guarantees application-specific performance requirements and controls the POSIX thread allocation and voltage/frequency scaling for energy-efficient thermal management. This controls three thermal aspects: peak temperature, average temperature, and thermal cycling. Contrary to existing learning-based runtime approaches that optimize energy and temperature individually, the proposed runtime manager is the first approach to combine the two objectives, simultaneously addressing all three thermal aspects. However, determining thread allocation and core frequencies to optimize energy and temperature is an NP-hard problem. This leads to exponential growth in the learning table (significant memory overhead) and a corresponding increase in the exploration time to learn the most appropriate thread allocation and core frequency for a particular application workload. To confine the learning space and to minimize the learning cost, the proposed runtime manager is implemented in a two-stage hierarchy: a heuristic-based thread allocation at a longer time interval to improve thermal cycling, followed by a learning-based hardware frequency selection at a much finer interval to improve average temperature, peak temperature, and energy consumption. This enables finer control on temperature in an energy-efficient manner while simultaneously addressing scalability, which is a crucial aspect for multi-/many-core embedded systems. The proposed hierarchical runtime manager is implemented for Linux running on nVidia's Tegra SoC, featuring four ARM Cortex-A15 cores. Experiments conducted with a range of embedded and cpu-intensive applications demonstrate that the proposed runtime manager not only reduces energy consumption by an average 15% with respect to Linux but also improves all the thermal aspects--average temperature by 14°C, peak temperature by 16°C, and thermal cycling by 54%. [ABSTRACT FROM AUTHOR]

A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power is about to be lost, and then sleeping until the supply recovers. We validate the approach experimentally on a processor with FRAM nonvolatile memory, allowing it to reactively hibernate using only energy stored in its decoupling capacitance. When compared to a recently proposed technique, the approach reduces processor time and energy overheads by 76%–100% and 49%–79% respectively. [ABSTRACT FROM PUBLISHER]

A fundamental challenge in realizing body-worn sensors is in providing an effective and long-lasting power supply. Issues regarding batteries have prompted researchers to investigate powering devices by extracting energy from the inertial movement of the human body. While previous studies have investigated the effect of generator location and wearer activity on harvestable power, they have not considered the orientation of the generator; this is the focus of this paper. Acceleration data collected across a sample population (10 participants) during different activities (walking and running) and generator location (five locations on the body) are presented. These data are processed to analyze the effect of orientation, and we find that it can significantly reduce the harvestable power. Subsequently, we propose and analyze how two degree-of-freedom generators can improve tolerance to rotation; results indicate that it can be improved by one order of magnitude. [ABSTRACT FROM PUBLISHER]

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating. [ABSTRACT FROM AUTHOR]

An energy-harvester-powered wireless sensor node is a complicated system with many design parameters. To investigate the various trade-offs among these parameters, it is desirable to explore the multi-dimensional design space quickly. Because of the large number of parameters and costly simulation CPU times, it is, however, often difficult or even impossible to explore the design space via simulation. This paper presents a response surface model (RSM) based technique for fast design space exploration of a complete wireless sensor node powered by a tunable energy harvester. As a proof of concept, a software toolkit is developed that implements the proposed design flow and incorporates either real data or parametrized models of the vibration source, the energy harvester, tuning controller, and wireless sensor node. Several test scenarios are considered, which illustrate how the proposed approach permits the designer to adjust a wide range of system parameters and evaluate the effect almost instantly but still with high accuracy. In the developed toolkit, the estimated CPU time of one RSM estimation is 25 \mus and the average RSM estimation error is less than 16.5%. [ABSTRACT FROM PUBLISHER]

The design of vibration energy harvesters (VEHs) is highly dependent upon the characteristics of the environmental vibrations present in the intended application. VEHs can be linear resonant systems tuned to particular frequencies or nonlinear systems with either bistable operation or a Duffing-type response. This paper provides detailed vibration data from a range of applications, which has been made freely available for download through the Energy Harvesting Network’s online data repository. In particular, this research shows that simulation is essential in designing and selecting the most suitable vibration energy harvester for particular applications. This is illustrated through C-based simulations of different types of VEHs, using real vibration data from a diesel ferry engine, a combined heat and power pump, a petrol car engine and a helicopter. The analysis shows that a bistable energy harvester only has a higher output power than a linear or Duffing-type nonlinear energy harvester with the same Q-factor when it is subjected to white noise vibration. The analysis also indicates that piezoelectric transduction mechanisms are more suitable for bistable energy harvesters than electromagnetic transduction. Furthermore, the linear energy harvester has a higher output power compared to the Duffing-type nonlinear energy harvester with the same Q factor in most cases. The Duffing-type nonlinear energy harvester can generate more power than the linear energy harvester only when it is excited at vibrations with multiple peaks and the frequencies of these peaks are within its bandwidth. Through these new observations, this paper illustrates the importance of simulation in the design of energy harvesting systems, with particular emphasis on the need to incorporate real vibration data. [ABSTRACT FROM AUTHOR]

Purpose: This article provides rehabilitation professionals and engineers with a theoretical and pragmatic rationale for the inclusion of haptic feedback in the rehabilitation of central nervous system disorders affecting the hand. Method: A narrative review of haptic devices used in sensorimotor hand rehabilitation was undertaken. Presented papers were selected to outline and clarify the underlying somatosensory mechanisms underpinning these technologies and provide exemplars of the evidence to date. Results: Haptic devices provide kinaesthetic and/or tactile stimulation. Kinaesthetic haptics are beginning to be incorporated in central nervous system rehabilitation; however, there has been limited development of tactile haptics. Clinical research in haptic rehabilitation of the hand is embryonic but initial findings indicate potential clinical benefit. Conclusions: Haptic rehabilitation offers the potential to advance sensorimotor hand rehabilitation but both scientific and pragmatic developments are needed to ensure that its potential is realized. [ABSTRACT FROM AUTHOR]

Abstract: Inertial energy harvesting is an emerging technology that can power electronic devices using energy scavenged from the motion of the human body. Owing to the relatively low frequencies associated with body motion (<3Hz), the generated electrical power is typically in the range of a few μW; hence transduction must be optimized. Previous studies have investigated the effect of activity and harvester location on the obtained power; this work evaluates how power is also affected by the harvester''s orientation. Ten participants performed walking and running exercises, while tri-axial acceleration data were sampled at five locations on the body. The results show consistency in the optimal orientation of the harvester between people, but this orientation is not aligned with the axes of the body and limbs. During walking, the power harvested from the upper and lower body differs by an order of magnitude; however, this difference is less significant when running. [Copyright &y& Elsevier]

Vibration energy harvesting systems pose significant modeling and design challenges due to their mixed-technology nature, extremely low levels of available energy and disparate time scales between different parts of a complete harvester. An energy harvester is a complex system of tightly coupled components modeled in the mechanical, magnetic, as well as electrical analog and digital domains. Currently available design tools are inadequate for simulating such systems due to prohibitive CPU times. This paper proposes a new technique to accelerate simulations of complete vibration energy harvesters by approximately two orders of magnitude. The proposed technique is to linearize the state equations of the system's analog components to obtain a fast estimate of the maximum step-size to guarantee the numerical stability of explicit integration based on the Adams–Bashforth formula. We show that the energy harvester's analog electronics can be efficiently and reliably simulated in this way with CPU times two orders of magnitude lower than those obtained from two state-of-the-art tools, VHDL-AMS and SystemC-A. As a case study, a practical, complex microgenerator with magnetic tuning and two types of power-processing circuits have been simulated using the proposed technique and verified experimentally. [ABSTRACT FROM AUTHOR]

Supercapacitors are often used in energy harvesting wireless sensor nodes (EH-WSNs) to store harvested energy. Until now, research into the use of supercapacitors in EH-WSNs has considered them to be ideal or oversimplified, with non-ideal behavior attributed to substantial leakage currents. In this brief, we show that observations previously attributed to leakage are predominantly due to redistribution of charge inside the supercapacitor. We confirm this hypothesis through the development of a circuit-based model, which accurately represents non-ideal behavior. The model correlates well with practical validations representing the operation of an EH-WSN and allows behavior to be simulated over long periods. [ABSTRACT FROM PUBLISHER]

Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems used in wireless sensor nodes. We analyze and benchmark the power consumption between Sleep, Idle, and Run modes. To reduce sensor node power consumption, we develop fine-grained power modes (FGPM) with five states which modulate energy consumption according to the sensor node's communication status. We evaluate the proposed method on a test bench Mica2. As a result, the power consumed is 74.2% lower than that of conventional approaches. The proposed method targets the reduction of power consumption in IoT sensor modules with long sleep mode or short packet data in which most networks operate. [ABSTRACT FROM AUTHOR]

Advances in communication technologies have made the interaction of small devices, such as smartphones, wearables, and sensors, scattered on the Internet, bringing a whole new set of complex applications with ever greater task processing needs. These Internet of things (IoT) devices run on batteries with strict energy restrictions. They tend to offload task processing to remote servers, usually to cloud computing (CC) in datacenters geographically located away from the IoT device. In such a context, this work proposes a dynamic cost model to minimize energy consumption and task processing time for IoT scenarios in mobile edge computing environments. Our approach allows for a detailed cost model, with an algorithm called TEMS that considers energy, time consumed during processing, the cost of data transmission, and energy in idle devices. The task scheduling chooses among cloud or mobile edge computing (MEC) server or local IoT devices to achieve better execution time with lower cost. The simulated environment evaluation saved up to 51.6% energy consumption and improved task completion time up to 86.6%. [ABSTRACT FROM AUTHOR]

Data centers consume lots of energy to execute their computational workload and generate heat that is mostly wasted. In this paper, we address this problem by considering heat reuse in the case of a distributed data center that features IT equipment (i.e., servers) installed in residential homes to be used as a primary source of heat. We propose a workload scheduling solution for distributed data centers based on a constraint satisfaction model to optimally allocate workload on servers to reach and maintain the desired home temperature setpoint by reusing residual heat. We have defined two models to correlate the heat demand with the amount of workload to be executed by the servers: a mathematical model derived from thermodynamic laws calibrated with monitored data and a machine learning model able to predict the amount of workload to be executed by a server to reach a desired ambient temperature setpoint. The proposed solution was validated using the monitored data of an operational distributed data center. The server heat and power demand mathematical model achieve a correlation accuracy of 11.98% while in the case of machine learning models, the best correlation accuracy of 4.74% is obtained for a Gradient Boosting Regressor algorithm. Also, our solution manages to distribute the workload so that the temperature setpoint is met in a reasonable time, while the server power demand is accurately following the heat demand. [ABSTRACT FROM AUTHOR]

State estimation is widely used in various automated systems, including IoT systems, unmanned systems, robots, etc. In traditional state estimation, measurement data are instantaneous and processed in real time. With modern systems' development, sensors can obtain more and more signals and store them. Therefore, how to use these measurement big data to improve the performance of state estimation has become a hot research issue in this field. This paper reviews the development of state estimation and future development trends. First, we review the model-based state estimation methods, including the Kalman filter, such as the extended Kalman filter (EKF), unscented Kalman filter (UKF), cubature Kalman filter (CKF), etc. Particle filters and Gaussian mixture filters that can handle mixed Gaussian noise are discussed, too. These methods have high requirements for models, while it is not easy to obtain accurate system models in practice. The emergence of robust filters, the interacting multiple model (IMM), and adaptive filters are also mentioned here. Secondly, the current research status of data-driven state estimation methods is introduced based on network learning. Finally, the main research results for hybrid filters obtained in recent years are summarized and discussed, which combine model-based methods and data-driven methods. This paper is based on state estimation research results and provides a more detailed overview of model-driven, data-driven, and hybrid-driven approaches. The main algorithm of each method is provided so that beginners can have a clearer understanding. Additionally, it discusses the future development trends for researchers in state estimation. [ABSTRACT FROM AUTHOR]

Wind energy harvesting technology is one of the most popular power sources for wireless sensor networks. However, given its irregular nature, wind energy availability experiences significant variations and, therefore, wind-powered devices need reliable forecasting models to effectively adjust their energy consumption to the dynamics of energy harvesting. On the other hand, resource-constrained devices with limited hardware capacities (such as sensor nodes) must resort to forecasting schemes of low complexity for their predictions in order to avoid squandering their scarce power and computing capabilities. In this paper, we present a new efficient ARIMA-based forecasting model for predicting wind speed at short-term horizons. The performance results obtained using real data sets show that the proposed ARIMA model can be an excellent choice for wind-powered sensor nodes due to its potential for achieving accurate enough predictions with very low computational burden and memory overhead. In addition, it is very simple to setup, since it can dynamically adapt to varying wind conditions and locations without requiring any particular reconfiguration or previous data training phase for each different scenario. [ABSTRACT FROM AUTHOR]