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Advances in the high performance computing (HPC) lead to a new frontier of the fan out wafer level packaging (FOWLP) development. To provide a solution of cost-attractive package for heterogeneous chip integration, FOWLP has recently emerged as an indispensable platform. Herein, we propose novel 2.5D re-distribution layer (RDL) interposer packaging technology including the fabrication of fine-pitch RDL interposer (>560 mm2) assembled with one high-bandwidth memory (HBM) and two ASICs, in order to achieve the TSV-less and cost-effective package. The intrinsic features of the fine-pitch RDL interposer enhances the integrity of the signals and the reliability of the bump joints, and thus integrates multiple chips and accommodates higher I/O counts. With the fine-pitch 2.5D RDL interposer technology, the system-in-package is fabricated in order to substantiate the functions of the HBM, and tested to analyze the characteristics of its performance. The fine-pitch 2.5D RDL interposer package demonstrates up to 3.2Gbps/pin operation with the HBM, and also shows excellent reliability without any failure during the reliability tests (TC1000hr, b-HAST 264hr, u-HAST 264hr and HTS1000hr). The proposed 2.5D RDL interposer technology can be a promising solution for the cost-effective and large size 2.5D packaging in the HPC applications.

As faster data processing and communication gets more demanded for Data Center/Cloud, HPC (High Performance Computing), AI (Artificial Intelligence) accelerator and Network markets, HBM (High Bandwidth Memory) becomes main memory type to meet the required bandwidth performance. HBM integration with logic dies in a system level has been developed on 2.5D SiP (System in Package) Platform with Si Interposer having TSV (Through Silicon Vias) of which fabrication cost is rather high. Therefore, as the low cost solution, alternative 2.5D SiP Platform approaches such as Organic Interposer using Redistribution Layer (RDL) and Glass Interposer have recently been reported. In this paper, RDL Interposer package with 4 HBM and 1 logic is demonstrated as 2.5D package platform based on RDL-First Fan-out Wafer Level Package (FOWLP). The effect of RDL design factors on electrical performances is investigated using the eye diagram method and fine pitch multi-layer RDL structure (2um L/S RDL, 4 Layers) is designed accordingly. Fine pitch RDL process is established followed by the wafer level and unit level assembly processes and RDL Interposer package is confirmed to meet all the reliability requirements.

In our previous studies, we have found that the over-molded structure FOWLP always shows the highest flexure strength. In the work of this paper, we would find out additional factors that affect the FOWLP strength. Two factors investigated are the silicon die to package ratio, and the package size. We find that the flexure strength decreases when the silicon die size increases. The smaller over-molded structure FOWLP has higher flexure strength. The reasons for these are analyzed.

The wafer thinning process and making backside redistribution layer (RDL) process were key technologies for assembling 2.5D and 3D IC the low profile device manufacturing. It was widely studied about temporary bonding material (TBM) for those advanced device packaging. The key issues here were void free, bonding, thermal resistance without having delamination and defect free cleaning after debonding. To minimize the cost effective 3D IC manufacturing, we have developed single layer temperature bonding material designed for room temperature mechanical debonding process. The materials have a high thermal resistance over 230 °C for 4 hours without having any void formation, delamination and no residue on the eWLB device after solvent cleaning.

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2μm line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

A series of new diarylureas and diarylamides possessing 1,3,4-triarylpyrazole scaffold was synthesized and their in vitro antiproliferative activities against A375P human melanoma cell line and NCI-60 cell line panel were tested. Compounds 9, 11, 12, 14, and 17-21 showed superior potency against A375P to Sorafenib. Over the NCI-60 cancer cell line panel, compound 14 possessing a methoxy group, amide linker, and 4-chloro-3-(trifluoromethyl)phenyl terminal ring showed the highest potency and broad-spectrum anticancer activity. Compound 13 showed high selectivity towards leukemia subpanel over other cancer types.

Synthesis of a new series of diarylureas and diarylamides possessing 1,3,4-triarylpyrazole scaffold is described. Their in vitro antiproliferative activities against 9 human melanoma cell lines were tested. Compounds 12, 13, 15, and 21-23 showed the highest potency against A375P melanoma cell line. In addition, compounds 10-15 and 19-24 showed high potency over the NCI 8 tested melanoma cell-lines panel. The IC(50) values for compound 23 were 0.36 μM and 0.84 μM over LOX IMVI and M14 cell lines, respectively. Compounds 21 and 23 showed high, dose-dependent inhibition of ERK kinase. Virtual screening was carried out through docking of compound 21 into the domain of V600E-B-RAF and the binding mode was studied.

Thermocompression bonding of through-layer copper interconnects is of great interest for fabrication of three-dimensional (3D) integrated circuits. We have investigated interactions of Cu films with noneutectic Sn-In at length scales of 1 μm to 5 μm. The effects of bonding time, bonding temperature, and post- bonding annealing temperature on intermetallic compound (IMC) formation, joint microstructure, and shear strength were investigated using scanning electron microscopy (SEM), energy-dispersive x-ray spectroscopy (EDS), x-ray diffractometry (XRD), and shear testing. It is shown that bonding temperature plays an important role in increasing the true contact area, while the postbonding annealing temperature affects the formation of a single IMC, the η-phase [Cu6(Sn,In)5]. Both of these phenomena were found to contribute to the shear strength of the joints. It is shown that two-step bonding processes, involving short bonding times and longer postbonding annealing, can be used to optimize the bond formation for increased throughput.

Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprised of completely of IMC compounds, will fail in a sudden unexpected manner as compared to normal solder joints, which fail in a ductile manner, where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress, during post-formation cooling down to room temperature, increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that, with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also been performed in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance than the samples with the conventional full pad design.

s of Papers ; 231st American Chemical Society National Meeting, ACS: Washington, DC, 2006. 6. Ahn, H.; Choi, T. H.; De Castro, K.; Lee, K. C.; Kim, B.; Moon, B. S.; Hong, S. H.; Lee, J. C.; Chun, K. S.; Cheon, G. J.; Lim, S. M.; An, G. I.; Rhee, H. J. Med. Chem. 2007 , 50 , 6032. 7. Colacino, J. M. Antiviral Res. 1996 , 29 , 125. 8. Horn, D. M.; Neeb, L. A.; Colacino, J. M.; Richardson, F. C. Anti-viral Res. 1997 , 34 , 71. 9. Alauddin, M. M.; Conti, P. S.; Fissekis, J. D. J. Labelled Compd. Radiopharm. 2002 , 45 , 583.10. Alauddin, M. M.; Ghosh, P.; Gelovani, J. G. J. Labelled Compd. Radiopharm. 2006 , 49 , 1079.11. Samuelsson, L.; Langstrom, B. J. Labelled Compd. Radiopharm. 2003 , 46 , 263.12. Conti, P. S.; Alauddin, M. M.; Fissekis, J. D.; Watanabe, K. A. Nucl. Med. Biol. 1995 , 22 , 783.13. Sun, H.; Sloan. A.; Mangner, T. J.; Vaishampayan, U.; Muzik, O.; Collins, J. M.; Douglas, K.; Shields, A. F. Eur. J. Nucl. Med. Mol. Imaging 2005 , 32 , 15.14. Kim, E. J.; Hong, S. H.; Choi, T. H.; Lee, E. A.; Kim, K. M.; Lee, K. C.; An, G. I.; El-Gamal, M. I.; Cheon, G. J.; Choi, C. W.; Lim, S. M.

Synthesis of a new series of diarylureas and amides having pyrrolo[2,3-d]pyrimidine scaffold is described. Their in vitro antiproliferative activities against A375 human melanoma cell line and HS 27 fibroblast cell line were tested and the effect of substituents on pyrrolo[2,3-d]pyrimidine was investigated. The newly synthesized compounds, except N-acetyl derivatives (Id, Ie, and Im), generally showed superior or similar activity against A375 to Sorafenib. Among all of these derivatives, compounds Iq and Ir having imidazole and morpholine moieties, respectively, showed the most potent antiproliferative activity against A375.

Low-temperature hermetic wafer bonding using In/Sn interlayer and Cu/Ti/Au metallization was investigated for microelectromechanical systems packaging application. In this case, the thin Ti layer was used as a buffer layer to prevent the diffusion between solder interlayer and Cu after deposition and to save more solders for diffusion bonding process. Bonding was performed in a wafer bonder at 180 and 150degC for 20 min with a pressure of 5.5 MPa. It was found that bonding at 180degC voids free seal joints composed of high-temperature intermetallic compounds were obtained with good hermeticity. However, with bonding at 150degC, voids were generated along the seal joint, which caused poor hermeticity compared with that bonded at 180degC. After four types of reliability tests-pressure cooker test, high humidity storage, high-temperature storage, and temperature cycling test-dies bonded at 180degC showed good reliability properties evidenced by hermeticity test and shear tests. Results presented here prove that high-yield and low-temperature hermetic bonding using Sn/In/Cu metallization with thin Ti buffer layer can be achieved.

The synthesis of a new series of diarylureas and amides having a 1-substituted-3-(3-chloro-5-methoxyphenyl)-4-pyridinylpyrazole scaffold is reported here. The in vitro antiproliferative activities of these diaryl derivatives against human melanoma cell line A375 were tested and the effect of substituents on the phenyl ring was investigated. Most of the newly synthesized compounds generally showed superior or similiar activity against A375 to Sorafenib. Among these compounds, IId, IIg and IIh showed excellent activity against A375 compared to Sorafenib.

A bonding joint between Cu metallization and evaporated In/Sn composite solder is produced at a temperature lower than 200°C in air. The effects of bonding temperature and duration on the interfacial bonding strength are studied herein. Cross sections of bonding joints processed at different bonding conditions were examined by scanning electron microscopy (SEM). The optimal condition, i.e., bonding temperature of 180°C for 20 min, was chosen because it gave rise to the highest average bonding strength of 6.5 MPa, and a uniform bonding interface with minimum voids or cracks. Good bond formation was also evidenced by scanning acoustic imaging. For bonding couples of patterned dies, a helium leak rate of 5.8 × 10−9 atm cc/s was measured, indicating a hermetic seal. The interfacial reaction between Cu and In/Sn was also studied. Intermetallic compounds (IMCs) such as AuIn2, Cu6Sn5, and Cu11In9 were detected by means of x-ray diffraction analysis (XRD), and transmission electron microscopy (TEM) accompanied by energy-dispersive x-ray (EDX) spectroscopy. Chemical composition analysis also revealed that solder interlayers, Sn, and In were completely converted into IMCs by reaction with Cu. All the IMCs formed in the joints have remelting temperatures above 300°C according to the Cu-In, Cu-Sn, and Au-In phase diagrams. Therefore, the joint is able to sustain high service temperatures due to the presence of these IMCs.

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages

We chose Sn−2.8Ag−20In and Sn−10Bi−10In (numbers are in weight percentages unless specified otherwise) as Pb-free solder materials for intermediate-step soldering. We then investigated how the two solders reacted with the under bump metallurgy (UBM) of Au/Ni (Au: 1.5 μm and Ni: 3 μm) at 210°C, 220°C, 230°C, and 240°C for up to 4 min. All, of the Au UBM was dissolved into the solder matrix as soon as the interfacial reaction started. The reaction formed Au(In, Sn)2 in the case of SnAgIn, and it formed Au(Sn, In)4 and Au(In, Sn)2 in the case of SnBiIn. The formation mechanism of the intermetallic phases is explained thermodynamically. The exposed Ni layer reacted with the solder and formed Ni28Sn55In17 in case of SnAgIn, and formed Ni3(Sn, In)4 in case of SnBiIn, at the solder joint interface. Under the same soldering conditions, the Ni3(Sn,In)4 layer in the SnBiIn/UBM is thicker than the Ni28Sn55In17 layer in the SnAgIn/UBM. Because of the thicker intermetallic compound layer, the SnBiIn solder joint has weaker shear strength than the SnAgIn solder joint.

Since lasers have the most saturated colors, laser display can express the natural color excellently. Laser scanning display has merits of simple structure and high optical efficiency. We designed a new scanning mirror which has a circular mirror plate with an elliptical outer frame and is electrostatically driven by vertical combs arranged at the outer frame. This eye-type mirror showed a larger deflection angle compared to the rectangular and the elliptical mirrors. To increase the driving force twice, stationary comb electrodes are arranged at the upper and lower sides of the moving comb fingers, together. The diameter of the mirror plate is 1.0 mm, and the lengths of the major and minor axes of the outer frame are 2.5 mm and 1.0 mm, respectively. Using this scanning mirror, we obtained an optical scanning angle of 32 degrees when driven by the ac control voltage of the resonant frequency in the range of 22.1 ~ 24.5 kHz with the 100 V dc bias voltages. We demonstrated the full color XGA-resolution video image with the size over 30 inches using an eye-type scanning mirror. The successful development of compact laser TV will open a new area of home application of the laser light.

The reaction between electroless Ni-P and Sn and the crystallization behavior of Ni-P were investigated to better understand the effect of P content on the Ni-P layer. Electroless Ni-P specimens with three different P contents, 4.6 wt.%, 9 wt.%, and 13 wt.%, were used to study the effect of the P content and the microstructure of Ni-P on the subsequent crystallization and intermetallic compound (IMC) formation during the reaction between Ni-P and electroplated Sn. Ni3Sn4 was the major phase formed in all samples heated up to 300°C, which totally transformed into Ni3Sn2 when samples were heated up to 450°C and the Sn layer was 0.5-µm thick. The IMC formed on the nanocrystalline Ni-P showed stronger texture compared to that formed on the amorphous Ni-P. Both the IMC thickness and density decreased with P content in the Ni-P layer, and Ni3Sn4 morphologies varied with P content. Dissolution of Ni into Sn increased with P content, which made IMC size in the bulk Sn increase with P content.

As a result of extensive studies, nearternary-eutectic Sn-Ag-Cu (SAC) alloys have been identified as the leading lead-free solder candidates to replace lead-bearing solders for ball-grid array module assembly. However, recent studies revealed several potential reliability risk factors associated with the alloy system. The formation of large Ag3Sn plates in solder joints, especially when solidified at a relatively slow cooling rate, poses a reliability concern. In this study, the effect of adding a minor amount of zinc in SAC alloy was investigated. The minor zinc addition was shown to reduce the amount of undercooling during solidification and thereby suppress the formation of large Ag3Sn plates. In addition, the zinc was found to cause changes in both the microstructure and interfacial reaction of the solder joint. The interaction of zinc with other alloying elements in the solder was also investigated for a better understanding of the role of zinc during solidification of the nearternary-eutectic alloys.

The electronic industry is making substantial progress toward a full transition to Pb-free soldering in the near future. At present, the leading candidate Pb-free solders are near-ternary eutectic Sn-Ag-Cu alloys. The electronic industry has begun to study both the processing behaviors and the thermo-mechanical fatigue properties of these alloys in detail in order to understand their applicability in context of current electronic card reliability requirements. In recent publications, the solidification behavior of the near-ternary eutectic Sn-Ag-Cu alloys has been reported in terms of the formation of large Ag3Sn plates and their effects on mechanical properties of Pb-free solder joints. Several methods have been employed to minimize the growth of the large Ag3Sn plates in the Sn-Ag-Cu solder joints by controlling the cooling rate during solidification, reducing Ag and/or Cu content, or adding minor alloying elements which reduce the amount of undercooling required for the nucleation of tin dendrites. In the present study, the results of accelerated thermal cycle fatigue tests are reported with the near-ternary eutectic Sn-Ag-Cu alloys of reduced Ag contents. Changes in microstructure and mechanical properties are also discussed by comparing the solder joints before and after thermal cycling.

The microstructure property relations of several Pb-free solders are investigated to understand the microstructural changes during thermal and mechanical processes of Pb-free solders. The Pb-free solder alloys investigated include pure Sn, Sn-0.7% Cu, Sn-3.5% Ag, and Sn-3.8% Ag-0.7% Cu (in weight percent). To reproduce a typical microstructure observed in solder joints, the cooling rate, ingot size, and reflow conditions of cast alloys were carefully controlled. The cast-alloy pellets are subjected to compressive deformation up to 50% and annealing at 150°C for 48 h. The microstructure of Pb-free solders is evaluated as a function of alloy composition, plastic deformation, and annealing. The changes in mechanical property are measured by a microhardness test. The work hardening in Sn-based alloys is found to increase as the amount of alloying elements and/or deformation increases. The changes in microhardness upon deformation and annealing are correlated with the microstructural changes, such as recrystallization or grain growth, in Pb-free solder alloys.

Near-ternary eutectic Sn-Ag-Cu alloys are leading lead-free candidate solders for various applications. These alloys yield three phases upon solidification: β-Sn,Ag3Sn, and Cu6Sn5. Large, plate-like, pro-eutectic Ag3Sn structures can grow rapidly within the liquid phase, potentially adversely affecting the mechanical behavior and reducing the fatigue life of solder joints. This article reports on the formation of such plates in Sn-Ag-Cu solder balls and joints and demonstrates how large Ag3Sn plate formation can be minimized.

Near-ternary eutectic Sn–Ag–Cu alloys are leading candidates for Pb-free solders. These alloys have three solid phases: β–Sn, Ag3Sn, and Cu6Sn5. Starting from the fully liquid state in solidifying near-eutectic Sn–Ag–Cu alloys, the equilibrium eutectic transformation is kinetically inhibited. The Ag3Sn phase nucleates with minimal undercooling, but the β–Sn phase requires a typical undercooling of 15 to 30 °C for nucleation. Because of this disparity in the required undercooling for nucleation, large, platelike Ag3Sn structures can grow rapidly within the liquid phase, before the final solidification of the solder joints. At lower cooling rates, the large Ag3Sn plates can subtend the entire cross section of solder joints and can significantly influence the mechanical deformation behavior of the solder joints under thermomechanical fatigue conditions. In this paper, it is demonstrated that the Ag3Sn plate formation can be inhibited, an important factor in assuring the reliability of solder joints composed of these alloys.

By comparing the activation energy for nucleation of individual intermetallic compound (IMC), the IMC phase that forms first is predicted as the one with the smallest activation energy. This methodology has been successfully applied to observations of IMC phases that form during liquid soldering on Cu and Ni plates.

Interfacial phase and microstructure, solder hardness, and joint strength of Sn–3.5Ag–X (X = Cu, In, Ni; compositions are all in wt% unless specified otherwise) solder alloys were investigated. Considering the melting behavior and the mechanical properties, five compositions of Sn–3.5Ag–X solder alloys were selected. To examine the joint characteristics, they were soldered on under bump metallurgy isothermally at 250 °C for 60 s. Aging and thermal cycling (T/C) were also performed on the solder joint. The interfacial microstructure of the joint was observed by scanning electron microscopy. X-ray diffraction and energy dispersive x-ray analyses were made toidentify the type of solder phase and to measure compositions. Excessive growth of an interfacial intermetallic layer in the Sn–3.5Ag–6.5 In solder joint led to a brittle fracture. In the other four solder joints, ductile fractures occurred through the solder region and the solder hardness was closely related with the joint strength.

The formation and the growth of the intermetallic compound (IMC, hereafter) at the interface between the Sn-3.5Ag (numbers are all in wt.% unless otherwise specified) solder alloy and the Cu substrate were investigated. Solder joints were prepared by changing the soldering time at 250°C from 30 sec to 10 h and the morphological change of IMCs with soldering time was observed. It resulted from the competition between the growth of IMC and the dissolution of Cu from the substrate and IMCs. They were further aged at 130°C up to 800 h. During aging, the columnar morphology of IMCs changed to a more planar type while the scallop morphology remained unchanged. It was observed that the growth behavior of IMCs was closely related with the initial soldering condition.

The epitaxial PbTiO3 thin films of different thickness were prepared on MgO(001) substrates by the reactive direct-current magnetron sputtering. The volume fraction of c domains, α, which was measured by x-ray diffractometry, increased rapidly from zero with the film thickness, being saturated at about 90% above 100 nm. The films were annealed in a PbO atmosphere at 700 °C for 8 h, and they were used to study the composition change in the Pb/(Pb + Ti) ratio and the relaxation of the residual intrinsic stress. The relationship between change of α and composition was weak. The stress state was calculated through the finite-element method. As for the small thickness, the tensile epitaxial stress overwhelmed compressive intrinsic and thermal stresses, and the domain structure was a-domain oriented. As for the large thickness, the compressive intrinsic stress together with the thermal stress overcame the tensile epitaxial stress, and the population turned into c domain.

The binary eutectic Sn-3.5wt.%Ag alloy was soldered on the Ni/Cu plate at 250°C, the thickness of the Ni layer changing from 0 through 2 and 4 µm to infinity, and soldering time changing from 30 to 120 s at intervals of 30 s. The infinite thickness was equivalent to the bare Ni plate. The morphology, composition and phase identification of the intermetallic compound (IMC, hereafter) formed at the interface were examined. Depending on the initial Ni thickness, different IMC phases were observed at 30 s: Cu6Sn5 on bare Cu, metastable NiSn3 + Ni3Sn4 on Ni(2 µm)/Cu, Ni3Sn4 on Ni(4 µm)/Cu, and Ni3Sn + Ni3Sn4 on bare Ni. With increased soldering time, a Cu-Sn-based η-(Cu6Sn5)1−xNix phase formed under the pre-formed Ni-Sn IMC layer both at 60 s in the Ni(2 µm)/Cu plate and at 90 s in the Ni(4 µm)/Cu plate. The two-layer IMC pattern remained thereafter. The wetting behavior of each joint was different and it may have resulted from the type of IMC formed on each plate. The thickness of the protective Ni layer over the Cu plate was found to be an important factor in determining the interfacial reaction and the wetting behavior.

This study has been supported by the Minstry of Science and Technology (MOST) through the Center for Interface Science and Engineering of Materials (CISEM)

Derivatives (Ib)—(Id), and (IIIa)—(IIIc) show the highest potency against A375P human melanoma cell line.

In new applications (such as MEMS, bio-MEMS), vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. Low temperature bonds are thin intermetallic compounds (IMCs) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of IMCs, will fail in a sudden unexpected manner, as compared to normal solder joints, which fail in a ductile manner, where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above TSVs. In this paper, a novel bond pad (which decouples the interconnection from the TSV) has been designed and simulated to reduce the joint stress. Low temperature bonding technology was demonstrated using Au/In/Sn alloy solder at a low temperature below 200°C forming robust IMC joint with high re-melting temperature (> 400°C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Actual bonded samples were built in order to compare the proposed low stress pad design with the conventional pad design. Shear test shows improvement in shear strength with the proposed pad design. Finally, finite element modeling has also been carried out again to understand how the proposed low stress pad design is extensible to the small diameter TSVs. The results show that the proposed pad design with TSV diameter less than 4 µm does not show much stress reduction and therefore may not be required.

The grain morphology of the intermetallic compound (IMC) that forms at the interface between liquid solders and solid-metal substrates was observed at solder joints. Cu6Sn5 grains on Cu substrates were rough or rounded, and Ni3Sn4 grains on Ni substrates were faceted. Through the energy-based calculations, the relationship between the IMC grain morphology and Jackson's parameter α was explained. The Jackson's parameter of the IMC grain with a rough surface is smaller than 2 while it is larger than 2 for faceted grains.

Embedded Wafer-Level Ball Grid Array (eWLB) technology was developed to provide a wafer-level packaging solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. Essentially, eWLB is a fan-out wafer-level packaging in which silicon die is embedded in the mold compound and the redistributed layer can be carried out over both silicon die and mold compound areas. Although many solder joint thermal fatigue models have been published for BGA and WLCSP packages, they may not be applicable for the eWLB packages. In this paper, the board level solder fatigue life modeling for lead-free solder Sn96.5Ag3.0Cu0.5 (SAC305) used in embedded Wafer Level Ball Grid Array (eWLB) packages under temperature cycling test conditions will be presented. Thermal fatigue life models, associated with Anand viscoplastic constitutive model used for the solder material, are first established by curve-fitting the equivalent creep strain and creep strain energy density data, respectively, with temperature cycling test data. A series of numerical parameter studies is then carried out on various design parameters such as material properties, configurations of packages and test boards, and temperature cycling test conditions. The effects of coefficient of thermal expansion (CTE) mismatch and bending stiffness of the eWLB package assemblies on the solder joint lifetime and the shift of critical solder joint locations will be discussed.

Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies.

An IMC based low temperature solder

A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 × 3 mm2 and 8 inch ASIC wafers. The new package design was proposed in order to reduce the parasitic effect by attaching the released MEMS dice directly to the pads on an ASIC wafer. Two different types of MEMS devices having combs structure and a beam structure were used in order to confirm the minimal change in the MEMS functionality before and after D2W bonding. The ASIC wafer consisted of non functional circuit with pads and the daisy chain for measuring the electrical resistance and interconnection lead-out. With the new method by utilizing both the standard pick and place machine and the wafer bonder, ~ 800 numbers of functional MEMS dice were bonded to ASIC by low temperature D2W collective bonding at 200 degC for 2 minutes having an alignment tolerance less than 10% in 150 μm pitch with pad size of 75 μm. In this approach, the bonding time has been reduced by more than 50% in comparison with the conventional D2W bonding with flip chip bonder and performance of the package was improved by direct interconnection and the yield was improved by bonding with Known Good Dice.

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Synthesis of novel amides and esters prodrugs of olmesartan is described. Their in vitro stability in rat plasma was tested. The results showed that the ester derivative IIa with n-octyl substituted dioxolone moiety was rapidly converted into olmesartan within 30 min. The pharmacokinetic parameters of IIa were studied and compared with those of olmesartan medoxomil. Compound IIa is proposed to be a promising prodrug of olmesartan.

The synthesis of a new series of diarylureas and amides having a 1-substituted-3-(3-chloro-5-methoxyphenyl)-4-pyridinylpyrazole scaffold is reported here. The in vitro antiproliferative activities of these diaryl derivatives against human melanoma cell line A375 were tested and the effect of substituents on the phenyl ring was investigated. Most of the newly synthesized compounds generally showed superior or similiar activity against A375 to Sorafenib. Among these compounds, IId, IIg and IIh showed excellent activity against A375 compared to Sorafenib.

Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200˚C forming robust intermetallics (IMC) joints with high re-melting temperature (>300˚C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90˚C (chip/wafer) for 20sec and 180/180˚C for 5mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120~330N (23.5~38.8MPa). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260˚C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.

Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200 °C forming robust intermetallics (IMC) joints with high remelting temperature (≫300°C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180°C for 45sec followed by annealing at 120°C for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400°C by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (≫20MPa) and a low electrical resistance (≪100mΩ). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ∼1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of ∼40 MPa and passed the 3 times reflow test at 260 °C. The IMC joint reliability was examined. After going through the multiple reflows at 260°C, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance.

A low temperature hermetic wafer bonding using In/Sn interlayer and Cu/Ti/Au metallization was investigated for MEMS and sensor packaging application. Bonding was performed in a vacuum wafer bonder at 180°C and 150°C for 20 min under 5.5 MPa. It is found that bonding at 180°C, voids free joints composed of high temperature intermetallic compounds (IMCs) were obtained with good hermeticity and reliability. However, bonding at 150°C, voids were generated along the seal joint which caused poor hermeticity comparing with that bonded at 180°C. After four kinds of reliability tests, i. e., Pressure cooker test, high humidity storage, high temperature storage, temperature cycling test, dies bonded at 180°C showed good reliability properties by hermeticity test and shear tests. Present results proved that high yield and low temperature hermetic bonding can be achieved by using Sn/In/Cu metallization with thin Ti as a buffer layer.

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.

An electrostatic 1 dimensionally (1D) scanning mirror for HD resolution display is introduced. Vertical comb drive was used to tilt the micro mirror. To minimize the moment of inertia and maximize the tilting angle of the mirror having the diameter of 1.6 mm, the rib was patterned on the backside of the mirror surface and optimized. Via the finite element simulation, the dynamic deformation of 45nm was achieved within the reflecting area in operating resonant mode thanks to the optimized rib structure. The actuating part of scanner was also optimized manipulating with several design variables to get maximum tilting angle. As the fabrication result, mechanical tilting angle of ±12.0 degree was achieved with the resonant frequency of 24.75kHz and the sinusoidal driving voltage of 280Vpp. For stable resonant motion of the scanner, the feedback control algorithm was realized in the driving circuit. Rigorous reliability characterization was carried out using statistical analysis on the fabricated samples. As a result, HD-resolution image with 720 progressive horizontal lines was demonstrated.

Flash memory is used at high speed as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make it possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem, the flash memory controller maintains a system software module called the flash translation layer(FTL). In this paper, we propose an enhanced log block buffer FTL scheme, FAST(Fully Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the previous log block buffer scheme.

Laser display technologies have been developed for an excellent expression of natural color, low power consumption and a long lifetime compared to other advanced displays, such as LCD, PDP and other projection type displays. The micro scanner is one of the key devices to make possible the raster scanning type laser projection displays. And the hermetic package of the micro scanner should be required for the protection from the environmental variations so as to keep the driving behavior uniform. Hermetic package can be ensured when the package is sealed hermetically without generating any outgases in the cavity. Thus, the hermetic sealing process was optimized through DOE (Design of Experiment) method using the Sn-In-Ag solder alloys instead of adhesives. And the characterizations of the packages were carried out in terms of hermeticity, shear strength, and interface microstructures. As a result, we’ve got about 2E−9 atm cc/sec He leak rate, which is low enough to pass the standard (MIL-STD-883E). Shear strength was as high as ∼80 MPa. The C-mode SAM images showed the continuous sealing area without any voids. In addition, the interfacial microstructures revealed good adhesion to the both parts, the glass lid and the ceramic package.Copyright © 2005 by ASME