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This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

Solar cell layers technology has achieved global standing in the solar cell layers deposition process, and it covers the innovative methods and techniques in significant applications. Recent solar cell layers technology has an advanced interest in a refined approach to enhance performance and highlights the importance of recent proficient procedures for manufacturing. For example, the application is used to search for novel materials for solar cells' layers to clarify the current energy crisis. The technological process and various types of solar cells depend on climate change. Among them, layers of solar cells and silicon wafer solar cells are very encouraging. Solar cell layers technology has led to solar cells being a more reasonable active option in design and production. The productivities facilitated by new solar cells still need to be enhanced for the various processes involved in the additional enhancement from Copper Indium Gallium Selenide (CIGS) microfilms to solar cell crystal structure dye-sensitized solar cells. The hydrophobic coating works as an anti-dust coating, enhancing efficiency and decreasing the cost of cleaning solar cells. In Saudi Arabia Majmaah City, most solar projects are in dry regions, where the dusty weather reduces solar cell efficiency. Therefore, combining these two properties and applying an anti-reflective and superhydrophobic coating will increase solar cell efficiency by 20%. Solar cells' crystal structure results are substituted with layers or new materials to balance environmental impact and toxic nature.

The goal of this paper is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based HEMTs. To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several WG = 2 mm p-type GaN HEMTs with different LGD or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed-up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 kHz to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on RON compared to off-state stress. Third, by comparing the results on identical devices having shorter LGD, we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer) we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

Scalable modeling and parameter extraction of the millimeter wave GaAs-based PIN diode for W-band switch design are presented in this paper. A direct-extraction method based on the S-parameters on wafer measurement is utilized to determine the extrinsic and intrinsic model parameters without any de-embedding test structures. Under turn-on and turn-off biased conditions, the modeled input reflection coefficients agree well with the measured data in the entire frequency ranges for GaAs-based PIN diode. The scalable normalization rules have been used to design W-band PIN diode switch successfully, good agreements are obtained between simulated and measured data to verify the accuracy of the proposed model.

The effect of the oxidizer present in the etching solution on the surface morphology and microstructure obtained after porosifying a p-type silicon wafer using metal-assisted chemical etching was studied. The morphologies of Si wafers porosified using two different solutions, HF/H2O2 and HF/KMnO4, were compared to establish how either of the oxidizers (H2O2 or KMnO4) should be chosen depending on the desired application. A comparative study revealed that parallel pores with wire-like structures or interconnected pores with cheese-like structures can be obtained when H2O2 or KMnO4 are chosen, respectively. Careful analysis of the SEM images was carried out using ImageJ to establish that the samples prepared using KMnO4 are more porous due to aggressive etching. Additionally, experimental and theoretical Raman spectroscopic studies have been utilized to study the presence of low-dimensional Si nanostructures, which are a few nanometers in size, at the microscopic level in porosified silicon.

This paper reports a MEMS disk resonator gyroscope (DRG) with superior overall performance in terms of bias instability, measurement range, and size. Specifically, a fully filled electrodes MEMS DRG is proposed to improve sensing capacitance to 23.66 pF and drive capacitance to 6.14 pF. The DRG is fabricated using a wafer-level vacuum-package process and is controlled and sensed by a configurable ASIC, enabling a small footprint. The DRG achieves an angle random walk (ARW) of 0.05/h and bias instability of 0.42/h within a full scale of 300/s, making it a very promising solution for angular measurement in high-end industrial applications.

Here, we report measurements made with an external vibration-insensitive single-shot interferometer, which is applicable for on-machine measurement. Previously, we developed a simple single-shot interferometry method in which the optical intensities of interference fringes appear not as sinusoidal distributions but have a sawtooth-like distribution, and the peak distortion direction depicts the slope of the measured surfaces. These properties allow use of this method in vibration-insensitive interferometry. In this study, we have experimentally confirmed this concept through measurement of a quarter of a Si wafer specimen 50 mm in diameter. The vibration source was a motorized linear stage the surface of which fluctuated between ±400 nm in height. The obtained surface profiles of the Si wafer were consistent with measurements made with a commercial interferometer within 30 nm.

This study reports a SiN x channel optical waveguide on a SiO2-covered bulk Si platform. The waveguide shows a low propagation loss of ∼0.6 dB/cm at 1550 and 1310 nm wavelengths. The SiN x film is deposited by reactive sputtering and is free from N–H species, which cause optical absorption loss at ∼1520 nm. No post-deposition high-temperature annealing is required as an increase in sputtering temperature, from room temperature to a moderate temperature of 200 °C, is effective for low-loss propagation. Based on chemical and optical analyses, the quality of the sputtered film at 200 °C is comparable to that prepared by low-pressure chemical vapor deposition at a high temperature of 820 °C. Fabricated fundamental passive optical devices (a multi-mode interferometer splitter and a directional coupler) reveal reasonable device function. A ring resonator shows a thermally stable operation because of the small thermo-optic coefficient for the SiN x , on the order of 10−5 K−1. The results indicate that the SiN x film by reactive sputtering at 200 °C can be favorably applied for photonic integration concerning CMOS back-end processing and hybrid-integration processing with non-CMOS materials. A Si-on-insulator wafer is not necessarily used as the platform, but a low-cost bulk Si wafer is replaced depending on the application. The reduction in the SiO2 under-cladding thickness, as thin as 1.0 µm, is examined regarding the potential in multilayered interconnects.

To meet the increasing demand for denser integrated circuits, feedforward control plays an important role in the achievement of high servo performance of wafer stages. The preexisting feedforward control methods, however, are subject to either inflexibility to reference variations or poor robustness. In this article, these deficiencies are removed by a novel variable-gain iterative feedforward tuning (VGIFFT) method. The proposed VGIFFT method attains: 1) no involvement of any parametric model through data-driven estimation; 2) high performance regardless of reference variations through feedforward parameterization; and 3) especially high robustness against stochastic disturbance as well as against model uncertainty through a variable learning gain. What is more, the tradeoff in which preexisting methods are subject to between fast convergence and high robustness is broken through by VGIFFT. Experimental results validate the proposed method and confirm its effectiveness and enhanced performance.

The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.

Metal-organic frameworks (MOFs) show great potential for various applications, but many of them suffer from the drawbacks of hydrolysis propensity and poor processability. Herein, we employ polymers of intrinsic microporosity (PIMs) with hydrophobic pores to decorate MOFs toward substantially improved water stability and shapeability. Through simple PIM-1 decoration, the sub-5 nm polymer layers can be uniformly deposited on MOF surfaces with almost no deterioration in porosity. Owing to the existence of superhydrophobic coating and the obstruction of water entrance into MOFs, the PIM-1 coated CuBTC exhibits impressive water resistance and excellent pore preservation ability after exposure in water, even in acidic and alkaline solutions. Moreover, polymer decoration improves the processability of MOFs, while various MOF/PIM-1 bulk wafers and oil-water separators can be obtained straightforwardly.

This study aims at investigating the effect of the substrate material on growth mechanism and also microstructure of Ta2O5 thin films. For this purpose, atomic force microscopy, scanning electron microscopy, and interferometry analyses were implemented to reveal the influence of silicon wafer and amorphous BK7 glass substrates on the nucleation and growth mechanisms of Ta2O5 thin films deposited via the radio frequency magnetron sputtering technique. Results indicated that those films with finer morphologies had relatively higher nucleation densities. Compared with BK7 glass substrate, crystals formed on the silicon wafer were shown to be finer and had lower mean areas in more nucleation sites. Moreover, optical properties and morphological characteristics of the films on the silicon substrates had much more endurance after the annealing treatment. It was observed that shift in the transmission spectra of the deposited films after the treatment was insignificant, implying high packing density of the films. However, a 6-nm shift in the transmission spectra indicated low density and high porosity of the films. Finally, atomic force microscopy analysis along with the light scattering measurements confirmed the formation of a low-roughness film on the silicon wafer substrates.

Silicon dioxide is the most important gate oxide dielectric material, and its surface planarization is an important factor in the continuous shrinking of the size of integrated circuits. Developing a novel chemical mechanical polishing auxiliary technique to achieve efficient polishing of oxide wafers is a significant challenge. In this study, a novel in-situ micro-nano bubbles auxiliary method, which used a nano-hydrophobic film to prepare a gas supersaturated slurry that can generate instant in-situ micro-nano bubbles during polishing, was developed for oxide wafers. Compared with conventional slurries, this auxiliary method increased the material removal rate by about 30% and ensured the low surface roughness of the wafer of 0.14 nm. The existence of micro-nano bubbles and the multi-size distribution and zeta potential of the micro-nano bubbles were measured by optical microscope and dynamic light-scattering methods. Then, to investigate the auxiliary mechanism of this in-situ micro-nano bubbles, different analytical methods, such as oxide thickness measurement system, scanning electron microscopy, Fourier transform infrared spectroscopy, and atomic force microscopy, were used to characterize the sample. The results indicated that during the polishing process, the micro-nano bubbles generated in situ have a good cleaning effect. In addition, the free radicals generated after in-situ micro-nano bubbles burst simultaneously modified the surfaces of the wafer and the pad. The improvement of the adsorption between the wafer and abrasives promoted the chemical reaction between them. After conditioning, the rougher and cleaner pad had a higher mechanical effect. Most importantly, this in-situ micro-nano bubbles auxiliary method has the potential to be applicable to all slurries.

This paper proposes a slurryless, highly efficient polishing method called ultrasonic vibration assisted electrochemical mechanical polishing (UAECMP) to realize 4H–SiC wafers with subnanometer surface roughness. UAECMP involves using ultrasonic vibration to simultaneously assist anodic oxidation of the SiC surface and mechanical removal of the generated oxide layer. The performance of UAECMP was evaluated by experiments and theoretical analyses. For a 4H–SiC (0001) surface, UAECMP achieved a material removal rate (MRR) of 14.54 μm/h, which was 4.5 times greater than that of ordinary electrochemical mechanical polishing (ECMP) and 290 times greater than that of mechanical polishing. Ultrasonic vibration increased the anodic oxidation rate by introducing local transient strain to the SiC surface and increasing the temperatures of the polishing area and electrolyte. The effect increased with the amplitude of the ultrasonic vibration. However, increasing the ultrasonic vibration amplitude also increased the surface roughness due to the large fluctuations of polishing marks caused by the grinding stone and SiC surface impact and the increasing residual oxide. Therefore, we propose a high-efficiency and -quality polishing process for SiC wafers that combines UAECMP and ECMP. The proposed polishing process may help simplify the existing manufacturing process for SiC wafers.

The fabrication of piezoelectric ZnO-based MEMS acoustic sensor has been reported. The sensor structure consists of a piezoelectric ZnO film deposited between two Al electrodes on a thin silicon diaphragm. A microtunnel is fabricated in the sensor structure using novel approach. This microtunnel is used to protect the diaphragm and determine the lower cut-off frequency of device. The approach presented in this paper completely removed a serious problem of microtunnel blockages during fabrication of sensors. In the developed process, the acoustic sensor fabricated using SOI and the Pyrex glass wafers are diced separately with same chip dimensions. Finally, both Pyrex glass and acoustic sensor chips are fitted in a jig for alignment and then anodically bonded. In reference to microtunnel blockages, the yield of the present technique is obtained as almost 100%. The developed technique can also be used in manufacturing of similar devices where the microtunnels are required in device structure. The technological development is supported by extensive AFM, FESEM, Raman spectroscopy and XRD studies of ZnO film; glass-to-silicon bond strength measurement; resonance frequency measurement by LDV; response characterization of the fabricated sensor, and SEM microscopy of microtunnel mouth to demonstrate the feasibility and yield of the process.

Chemical mechanical polishing (CMP), a wafer surface planarization method, is critical in the semiconductor industry because uniform and scratch-free processing is required for a highly integrated circuit on the wafer surface. Thus, the prediction of aggregated particle size during CMP helps achieve stable and precise processing during experimental circumstances. Herein, silica nanoparticle aggregation simulation during CMP process-based Quadrature Method of Moments (QMOM) was first described using ANSYS Fluent as a computational fluid dynamics (CFD) tool. Experiments were also implemented in a 10,000 class cleanroom using a CMP polisher actually used in the semiconductor industry. Moreover, a comparison of experimental particle size measured through zeta-potential and particle size analyzer and simulated Sauter mean diameter (D32) showed that the experimental data agreed well with the simulation results.

Accurate measurements of high-pressure are demanded urgently in the fields of ocean sciences, industrial controls, and oil explorations. However, conventional piezoresistive high-pressure sensors suffer from serious temperature drifts and eventually result in compromised accuracies. Herein, this paper presents a resonant high-pressure sensor with the pressure range of 30 MPa. This sensor composes of a glass wafer for vacuum package and an SOI wafer with integrated dual resonators and diaphragm structures to alleviate the temperature effect on sensor. High-pressure under measurement bends the pressure sensitive diaphragm, producing frequency shifts of suspended resonators. Finite element analyses were conducted to promote the structural strength of the sensor and optimize the pressure sensitivities and the temperature sensitivities to improve the accuracy of the sensor. Fabrication of the sensor was realized using the SOI-MEMS process. Characterization results showed the pressure sensitivities of the resonators were quantified as 0.43 kHz/MPa and 0.16 kHz/MPa with linear coefficients of 0.9999, respectively. The temperature sensitivities of the resonators were reduced from 44 Hz/°C to -1 Hz/°C. In addition, the accuracy of the sensor was higher than 0.02 %FS in the temperature range of -10°C to 60°C and the pressure range of 0.11 MPa to 5 MPa by using a polynomial algorithm. Simulative and experimental results indicate that the sensor may be a potential candidate in the field of high-pressure sensing.

openaire: EC/H2020/826588/EU//APPLAUSE The wafer-level Solid Liquid Interdiffusion (SLID) bonds carried out for this work take advantage of the Cu-In-Sn ternary system to achieve low temperature interconnections. The 100mm Si wafers had μ-bumps from 250μm down to 10μm fabricated by consecutive electrochemical deposition of Cu, Sn and In layers. The optimized wafer-level bonding processes were carried out by EV Group and Aalto University across a range of temperatures from 250°C down to 170°C. Even though some process quality related challenges were observed, it could be verified that high strength bonds with low defect content can be achieved even at a low bonding temperature of 170°C with an acceptable 1-hour wafer-level bonding duration. The microstructural analysis revealed that the bonding temperature significantly impacts the obtained phase structure as well as the number of defects. A higher (250°C) bonding temperature led to the formation of Cu3Sn phase in addition to Cu6(Sn,In)5 and resulted in several voids at Cu3Sn|Cu interface. On the other hand, with lower (200°C and 170°C) bonding temperatures the interconnection microstructure was composed purely of void free Cu6(Sn,In)5. The mechanical testing results revealed the clear impact of bonding quality on the interconnection strength.

A de-embedding technique for high-Q or high-cutoff frequency ( $f_{{T}})$ one-port structures such as metal-oxide-semiconductor (MOS) varactors and Schottky diodes for millimeter- and submillimeter-wave applications is proposed to mitigate the limitation of vector network analyses of structures with a large ratio between the |reactance| and resistance (| X|/R). A subarray with a fewer number of cells of the device under test that has a lower | X|/R is used instead of an ultrahigh-Q OPEN structure for de-embedding. This technique provides more accurate measurements of cutoff frequency ( $f_{{T}})$ . The resulting average of %-variations of measured $f_{{T}}$ and series resistance over the measurement frequency range (50-55 GHz) are decreased by 30%-45%. More importantly, the %-variation range of $f_{{T}}$ for the proposed method over samples and frequencies is less than ~20% which is ~50% smaller than the de-embedding using a conventional ultrahigh-Q OPEN structure.

Wafer fabrication (Wafer Fab) involves state-of-the-art, expensive, and highly complex processes, and only little is known about its change qualification, a process that follows a strict guideline to ensure that changes will affect neither the process flow nor the quality and reliability of the final saleable wafers. This paper proposes a five-stage change qualification framework in semiconductor manufacturing. We conceptualize our framework based on a stage-gate model and define suitable stages and gates for effective decision making. Afterward, we demonstrate its robustness via a case study, which provides an elaborate example that guided a requestor who successfully went through all stages of the change qualification process in reducing the occurrence of tool alarms. Our framework is proven to be complete and ready for deployment in the industry as a standard process flow in manufacturing technology management.

We are presenting here fabrication of silicon (Si) nanowires (NWs) arrays by using Si (1 0 0) wafer as substrate, by metal assisted chemical etching (MACE) method. The Si-NWs growth on the Si wafer has been done by using etching time of 45 min in etching solution of hydrogen fluoride and hydrogen peroxide. X-ray diffraction (XRD) has been used for the structural analysis of NWs to estimate the crystalline size, micro-strain, dislocation density of fabricated nanostructures. The surface morphology of Si-NWs array has been studied through field effect scanning electron microscopy (FE-SEM). The optical properties like energy band gap of fabricated Si-NWs has been carried out through UV–Vis diffuse reflectance spectroscopy (UV DRS) and photoluminescence (PL) spectroscopy.

This paper proposed the high sensitive linear and rotational based differential capacitive inertial sensor. The designed sensor consists of a proof of mass, which resides in an air medium — the acceleration measured along with a change of displacement and the differential capacitance. Sensor modeling and simulation have done with CoventorWare software. SOIMUMPS fabrication process has described because it allows pattern on both sides of an SOI wafer. Solid mechanics and electrostatic analysis have applied for measurement of acceleration. The high sensitivity of 981.28fF/g has observed. The simulated results have tabulated. Finally, performance and future scope of the inertial sensor has discussed.

This study uses silicon wafer as the substrate, on which a multi-layered structure is formed. This structure includes a 50-nm indium tin oxide (ITO) film, ZnO films with variable thickness and ZnO nanorods of various radii and height on the top. This kind of coating can enhance solar cell productivity at omnidirectional angles because there is a gradual declination of the refractive index. The multi-layered structure were designed and tested using Finite-difference time-domain (FDTD) simulations, and this reduced it reflectance to

We report the gas sensing properties of a type of new materials, Na1/2Bi1/2TiO3 (NBT)-based ceramics. After the NBT-based ceramics were asymmetrically reduced and coated with Au electrodes, the materials exhibit relatively large electrical responses when exposed to oxygen and some oxidizable gases at a relatively low temperature (≤300 °C). An electric voltage ∼60 mV is measured in the mixture of O2 and N2 (1% O2). In oxidizable gases, a negative response can be obtained. The measured voltages are −45 mV and −98 mV in the mixtures of H2/air (1000 ppm H2) and C2H5OH/air (1000 ppm C2H5OH), respectively. The electrical responses are proportional to the logarithm of the concentrations of the analyzed gases. Also, the electrical responses to oxygen and oxidizable gases have opposite signs, and the model of mixed-potential is proposed to explain the gas sensing phenomenon. This study provides a new material and a simple design for gas sensors. The proposed gas sensor comprises a reduced NBT-based ceramic wafer with the same electrodes on the opposite surfaces. Additional components in traditional gas sensors, such as sensing or reference electrode, are unnecessary.

Titanium dioxide (TiO2) thin films are prepared on various substrates like glass and silicon wafers by spray pyrolysis method. The spray solution is prepared by dissolving titanium-tetra isopropoxide (TTIP) in ethanol. Optical, structural and dielectric properties of these films are studied by the transmittance spectra, X-ray diffraction (XRD), atomic force microscopy (AFM), capacitance–voltage (C-V) characteristics, respectively. TiO2 metal oxide semiconductor (MOS) capacitors are fabricated using TiO2 as a dielectric medium. C-V plots are analyzed to determine the dielectric constant (er) of TiO2 film. The dependance of er of the TiO2 films with the substrate temperature has been investigated.

Monocrystalline silicon is currently one of the most used materials in the semiconductor industry. However, being hard and brittle, a silicon wafer commonly suffers from machining-induced subsurface damage (SSD). Detecting SSD is important for optimizing the machining process in order to improve the surface integrity of a machined wafer. Among the various detection methods, the polarized laser scattering (PLS) method has a huge potential in highly efficient detection. However, the surface scattering mechanism is not fully understood so far, which impedes the optimization of the PLS detection processes. This study resolves surface scattering based on the electromagnetic scattering theory. It is found that the depolarization caused by surface scattering increases with the surface roughness and the incident angle. With the consideration of the subsurface scattering characteristics and the distribution of the SSD, this study provides a solution for the PLS detection that comprises of the use of a horizontally polarized laser with vertical incidence to minimize the influence of surface scattering. This study provides a theoretical analysis of both surface and subsurface scattering to facilitate an optimized PLS detection.

Photoluminescence spectra have been measured at 80 K in Czochralski-grown silicon wafers annealed at 450 °C, causing thermal donor and oxygen-precipitate generation. Six subbandgap luminescence peaks were identified after the annealing. One peak, centered at 1206 nm, was found to increase with a similar time constant to the thermal donor concentration measured by changes in the resistivity. We propose that the other five peaks are related to the formation of oxygen precipitates (OPs), or their nuclei. These peaks remain after a thermal donor annihilation (TDA) step, while the 1206 nm peak disappeared. This is consistent with our previous observations that the growth of OPs occurs concurrently with the growth of thermal donors at low temperatures. The annihilation of the thermal donors leads to an incomplete recovery of the interstitial oxygen concentration, consistent with the formation of precipitates. Recombination-active ring-defects formed during the annealing also remain after TDA.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

Complementary metal-oxide-semiconductor (CMOS) image sensors have widely been used in internet of thinking (IoT) devices such as smartphones, smart watch and personal computer tablets [1] . The consumer market strongly requires higher sensitivity and higher speed image data processing to realize high functional CMOS image sensors such as three dimensionally stacked back-side-illuminated CMOS image sensors (3D-CIS) [2] . However, there are some serious technological issues in the fabrication of advanced CMOS image sensors as shown in Fig. 1 .

A synthesis and patterning process of luminescent graphene quantum dots (GQDs) is highly desirable in applications to industrial- and bio-fields. In this paper, a novel strategy to obtain GQDs is proposed and demonstrated by an ion-beam assisted chemical vapor deposition (CVD). Ion-beam irradiation provides catalyst sources for the GQD creation. The luminescent GQDs are generated using a Fe-implanted Si wafer by a two-step annealing process: i) A formation step of nano-sized Fe catalyst particles and ii) a synthesis step of GQDs by a CVD method. Under the 1st annealing step of the Fe-implanted Si wafer, Fe nanoparticles (FeNPs) are created by the diffusion and aggregation of Fe atoms. Due to the high temperature atmosphere in the 2nd annealing step, FeNPs are then completely removed, and thus only high-purity and -quality GQDs are finally produced. In our work, patterned GQDs were fabricated by using a metallic mask during the ion-beam irradiation. Furthermore, various GQD patterns were also demonstrated by combining the conventional semiconductor manufacturing process and our ion-beam assisted CVD technique.

A multicrystalline silicon solar cell was analyzed using Raman microspectroscopy. We measured the prominent Raman modes of silicon, nanocrystalline silicon and silver oxide in various regions of the solar cell to generate insights into the process and material quality of the finished device. First, by comparing the distribution of the transverse optical (TO) phonon peak position and full-width-at-half-maximum (FWHM) of the solar cell with a single crystal silicon wafer, the quality of the multicrystalline silicon surface was ascertained. Second, a similar analysis of the remnant saw marks on the device surface showed a discernably higher and wider distribution of TO phonon peak position and FWHM compared to a multicrystalline silicon surface. This indicated the presence of residual compressive stresses in the saw mark region. Third, by observing the silver fingers and bus bars, a residual silver oxide layer was identified, up to 25 μm away from the line edges. This was attributed to the screen printing of the silver paste and the subsequent firing process. Finally, Raman mapping on an embedded inclusion showed the presence of nanocrystalline silicon phase. The multicrystalline silicon region surrounding the inclusion was under tensile stress. A nondestructive, confocal Raman analysis of the inclusion provided a 3-D visualization of the defect, both inside and above the surface of the multicrystalline silicon wafer.

Over the last decade, lasers have been gradually employed for Si wafer dicing to replace blade dicing. Laser dicing has the potential to replace blade dicing as the future generation ultrathin wafer singulation method as it enables higher cutting speed, lower damage, and smaller kerf width but various technical challenges still remain to be resolved. In this article, laser ablation and dicing of Si wafers are reviewed in terms of the physics of laser-material interaction based on nanosecond, picosecond, and femtosecond pulse durations. The effects of various laser settings, dicing process parameters, and material factors on ablation rate, ablation precision and quality, and die fracture strength are discussed in detail. With the increasing usage of Cu stabilization layer on the backside of ultrathin Si wafers, we also review laser-material interaction in Cu and elaborate on recent findings on the effects of laser dicing through Si and Cu simultaneously on the microstructural and fracture strength properties of the die. Various approaches to improve the ablation rate, ablation quality, and die fracture strength are discussed.

Rail grinding is a widely-used method to eliminate surface damages on railway tracks. The grinding chips are closely related to the grinding parameters and the grinding quality. Therefore, the investigation on the characteristics and the formation mechanism of chips from rail grinding is beneficial for the optimization of rail grinding process. In the present study, the grinding chips from the real rail grinding in the field and from the rail grinding experiments in the laboratory were analyzed in terms of their morphologies, microstructural evolution and chemical characteristics. The results showed that flowing, knife, slice and spherical chips were generated during rail grinding. The formation mechanism of flowing, knife and slice chips was plastic deformation by forces from abrasive grains with oxidation in air by grinding heat. Primary and secondary shear zones and central zones were generated. In the primary shear zone, cracks were generated in knife and slice chips. In the secondary shear zone, obvious plastic deformation was formed in knife and slice chips and a significant white etching layer (WEL) was generated in knife chips. The formation mechanism of spherical chips was melting of small powdery grinding debris by the high temperature and the subsequent solidification, accompanied with severe oxidization in air. The oxides produced in chips consisted of FeO, Fe3O4, Fe2O3 and AlFe2O4. The grinding quality could be predicted through observing the grinding debris. The larger percentage of flowing chips represented the better grinding quality (smaller surface roughness, slighter surface burn and thinner WEL on ground rail), which could be the goal for the grinding parameters choice.

Rare earth (RE) doped oxides have demonstrated great potential for photonic applications and have also appeared as promising candidates for quantum memory devices and microwave to optical transducers. Here, we investigate the potential of Chemical Vapor Deposited (CVD) europium-doped Y2O3thin films on silicon as a new platform for integrated quantum devices. We aim at improving the optical properties of such thin films by carefully controlling the RE ion's environment. In particular, we study the effect of annealing post treatments and demonstrate that a significant source of broadening of the optical transition arises from interfacial reactions with the silicon substrate. We thus propose to encapsulate RE ions between undoped high-quality thick layers in order to limit the impact of interfacial reactions on their properties during thermal annealing. Using this approach, we succeeded in measuring a narrow inhomogeneous linewidth of 18 GHz and an ultra-narrow homogeneous linewidth of 5 MHz inferred from spectral hole width. These results are promising towards the use of these engineered RE doped thin films for the development of a scalable nanostructured spin-photon interface. In addition, our strategy could be applied to a large variety of oxide films for a broad range of applications. Paper published in Materials Advances.

With the demand for manufacturing large (e.g., 450 mm) wafers, problems arise due to temperature increases associated with the chemical mechanical polishing (CMP) process. Various methods have been employed to stabilize the in-situ polishing temperature. The use of a high-temperature slurry can improve the removal rate, but a degradation in surface morphology occurs during the copper CMP procedure. To explain this mechanism, the effects of temperature on the slurry, CMP pad, and copper wafer were separately investigated. A temperature of approximately 40 °C was demonstrated to be a suitable choice when considering polishing efficiency and quality, thereby facilitating the rapid production of semiconductors. Particle aggregation was also observed with a rise in temperature. The work presented here may allow for a reduction in defects during low-hardness material polishing.

We present results from a characterisation of bulk defects in CdTe wafers, and their role in the degradation of charge transport performance of CdTe radiation detectors. Sub-bandgap IR microscopy and X-ray Lang topography have been used to characterise material quality prior to device processing. IR microscopy clearly identifies extended defects such as tellurium precipitates in the material bulk, whilst Lang topography characterises stacking faults, crystallite boundaries and other crystallographic features in the near-surface region. After fabrication of contacts onto the material, ion beam induced charge imaging is used to investigate the correlations between material defects and charge transport. Digital ion beam induced charge imaging is used to produce high resolution maps of charge signal amplitude, carrier drift time, and carrier drift mobility.

This article presents a 96 μm x 106 μm sized single-crystalline silicon (SC-Si) /Au thermopile infrared (IR) detector, with the thermopile and IR absorber located at different layers of a double-deck micromechanical structure for improving detectivity. In order to enhance IR-heat absorption within such a tiny device size, an umbrella-shaped SiN IR absorbing membrane instead of traditional plane IR-absorbing film occupies the whole area of the top layer structure. The umbrella-shaped IR absorber is suspended on top of the IR-detecting thermopile layer, with a central umbrella-stick to support the suspending and conducting the absorbed IR-heat to the bottom thermopile layer. The bottom thermopile layer consists of six pairs of spiral-shaped SC-Si/Au thermocouples that feature several times higher Seebeck coefficient compared to the traditional polysilicon/metal thermocouples. By combining surface-micromachining technique with a specific bulk-micromachining process performed in (111) silicon wafer, the double-deck structured IR-detector is successfully fabricated only from the front side of a single (111) silicon wafer for IC-foundry compatible low-cost manufacturing. Testing results show that this device of about 100-μm scale achieves an ultrahigh IR detectivity of 1.01 x 10⁸ cm·Hz $^{{1/2}}·$ W⁻¹, which is two times improvement compared to the recently reported thermopile IR detectors, though the counterparts had larger device area. Featuring tiny size and batch fabrication capability, the proposed high-performance IR-detector is promising in both single-point detection and multipixel arrayed temperature imaging applications.

We report on SiC pn-junction diodes with a high blocking voltage over 3 kV. Although SiC radiation sensors have been developed with a Schottky barrier type due to a simple fabrication process in the early stages, pn junction structures are advantageous due to lower sensitivity of the surface defects. Thus, this system provides an ideal condition to investigate the effect of bulk crystal defects on the characteristics of the radiation sensor. The pn diodes were designed with a device simulator and fabricated with a 4-inch 4H-SiC wafer. The epitaxial layer was grown on an n-type substrate with sufficiently low doping concentration of Nd-Na =~ 5 × 1014 cm..3 and an average thickness of 52 μm. Fabricated pn diodes with a relatively large leakage current still show a clear peak of the Landau distribution in the charge spectrum, suggesting their practical availability as minimum ionizing particle detectors. The estimated electron-hole pair creation energy is consistent with the published studies and we expect good radiation tolerance. Feasibility based on the wafer processing indicates that the prototype devices are a good candidate for the muon beam monitor application in the coherent muon-to-electron transition experiment (COMET) at J-PARC.

In this paper, an evaluation of machine learning classifiers to be applied in wafer defect detection is described. The objective is to establish the best machine learning classifier for Wafer Defect Detection application. k-Nearest Neighbours (k-NN), Logistic Regression, Stochastic Gradient Descent, and Support Vector Machine were evaluated with 3 defects categories and one non-defect category. The key metrics for the evaluation are classification accuracy, classification precision and classification recall. 855 images were used to train, test and validate the classifier. Each image went through the embedding process by InceptionV3 algorithms before the evaluated classifier classifies the images.

A cluster tool consists of several single-wafer processing chambers and a wafer handling robot. A wafer has to wait within a chamber after being processed there until it is unloaded by the robot. Such wafer delays may cause wafer quality degradation or variability due to residual gases and heat in the chamber. The tool operation schedule has to maintain identical timing patterns or schedules for each cycle so as to keep wafer delays constant for every wafer. However, at the beginning of the tool operation, the tool is in an empty state and hence we need to make the tool reach such steady schedule by loading wafers into the tool. In this article, we develop a method of scheduling the robot tasks during the start-up period of a cluster tool to reach a target steady schedule quickly as possible. To do this, we model the behaviors of a cluster tool using timed Petri nets and linear system matrices in the max-plus algebra. By analyzing the matrices, we first identify a class of steady schedules which can be reached from the empty tool. We develop the matrices that explain the schedule evolution of the start-up period before reaching the steady period. By examining the matrices, we develop a method of choosing the most desirable one from such class of reachable steady schedules that can be achieved in the minimum time. We also prove that the schedule also minimizes the time duration of the close-down. Finally, we present computational experiments.

The effect of cavities on recrystallization growth of amorphous SiC induced by a high fluence He implantation was investigated. 300 keV He ions were used to implant the 6H-SiC (0001) wafer to a fluence of 4.4 × 1017/cm2 at room temperature. A buried amorphous layer with a width of approximately 468 nm was formed. Moreover, many spherical bubbles with diameters over 25 nm were observed by transmission electron microscopy. Recrystallization of the buried amorphous layer was visible after 900 °C annealing for 30 min. Some irregular cavities were found in the damaged layer. The recrystallization started from the amorphous/crystalline interface, and the formed cavities retarded the epitaxial growth. Nanocrystalline SiC was formed in the cavity layer. Extended defects were also characterized by transmission electron microscopy. The research results will give an insight into the recrystallization process in amorphous SiC.

Cast multicrystalline silicon (mc-Si) requires high quality at low cost, while fully-melted seed-assisted growth has a reasonable utilization rate but urges better initial grain control. An electrophoretic deposited quartz nucleation layer is introduced to obtain a uniform and oriented nucleation layer. Carrier recombination characterization, including photoluminescence and carrier lifetime mapping, shows that the density of recombination-active structural defects is reduced due to better grain distribution. The average conversion efficiency values of silicon particle, sprayed quartz, and deposited quartz assisted wafers are 20.52%, 20.48%, and 20.68%, respectively Moreover, deposited quartz assisted mc-Si can obtain oriented grains, which offers a potential to apply alkaline texturing on mc-Si wafers.

Close integration of transducer arrays with supporting electronic circuits is essential in achieving efficient and compact ultrasound systems. An integral part of hybrid integration of 2D CMUT array to CMOS electronics is the introduction of through-glass-via (TGV) interconnects in glass substrates as an integral part of the 2D CMUT array fabrication. Micro-cracks around via locations, via discontinuity, and poor coplanarity between the vias and glass substrate are some of the challenges with laser-drilled, paste-filled copper-through-glass-via (Cu-TGV) interconnects. This study provides a detailed fabrication process for making $32\times 32$ -element 2D CMUT arrays on a composite glass substrate incorporating silicon-through-glass vias (Si-TGV) as interconnects using sacrificial release approach. On one column of a fabricated 2D CMUT array, we measured a mean resonant frequency of 5.6 MHz in air and an average device capacitance of 1.5 pF. With the introduction of a buried top electrode in the device structure, we achieved a collapse voltage of 93 V, which is considerably lower than the collapse voltage measured in our previously demonstrated 2D CMUT arrays with top electrode on top of the nitride plate. The fabricated array is flip-chip bonded on a custom-designed driving integrated circuit to demonstrate the complete system operation. We measured a peak-to-peak pressure of 1.82 MPa at 3.4 MHz, and 5 mm from the array surface in a 0.33 mm focal spot size. [2021-0101]

The heterojunction (HJ) solar cell is one of the best possible options to upgrade the conventional single homo-junction c-Si solar cell. In this work, a single HJ solar cell based on crystalline silicon (c-Si) wafer with zinc oxide (ZnO) is designed to reduce the loss of power conversion owing to the reflection of incident photons by the top surface of silicon. A PC1D simulation is used to evaluate the optimum numerical value of key photovoltaic parameters for HJ-based c-Si solar cells. The average reflectance for ZnO/Si HJ-based c-Si is 7.65% in the wavelength range of 400-1000 nm. The highest efficiency (η = 24.8%) of the ZnO/Si HJ-based c-Si solar is obtained with a 400 μm base thickness, 20 μm emitter thickness, doping concentration of 1.1 × 1017 cm−3 in the base and a doping concentration of 5.1 x 1016 cm−3 in the emitter. The proposed ZnO/Si HJ-based c-Si solar cell with high efficiency would be one of the best possible alternative HJ device to the conventional single homo-junction c-Si solar cell.

Ultrasonic vibration-assisted inner-diameter (ID) sawing (UVAIDS) has been proved as an effective slicing process for mono-crystalline silicon in improving the surface quality of wafers. The sawing force is regarded as one of the most critical refers to evaluate the sawing performance. Modeling sawing force is significantly helpful to understand the influence of sawing variables on the sawing process. Currently, there is no publication on the sawing force model for the UVAIDS of hard and brittle materials. This investigation presents a mechanistic model for the normal force in the one-dimensional ultrasonic vibration-assisted ID sawing hard and brittle materials. Based on brittle fracture mode in material removal mechanism, the sawing force model is developed beginning from the analysis of a single diamond abrasive grain. A series of experiments on sawing mono-crystalline silicon are performed to verify this model. The experimental results show that the measured sawing forces agree with the theoretical sawing forces calculated by this model. Besides, the influence of sawing variables including ultrasonic vibration amplitude, feed rate, spindle speed, cutting-edge thickness, abrasive size, dimensions of the saw blade, and workpiece on the sawing force are also analyzed and discussed. This mechanistic model can be used to predict the normal force in the UVAIDS of hard and brittle materials.

In semiconductor foundries, wafer map defect analysis is crucial to prevent yield excursion. However, traditional manual inspection can hardly meet the high throughput demand. Deep learning based automatic defect detection shows promising efforts to achieve high accuracy and efficiency, yet the current approaches’ performance is limited by the imbalanced dataset and lack of interpretability. In this paper, we propose a Variational Autoencoder Enhanced Deep Learning Model (VAEDLM) for wafer defect imbalanced classification. It is light-weighted and effective in wafer defect pattern recognition on imbalanced dataset. It used variational autoencoder and decoder to generate similar wafer defect maps and a refined deep convolutional neural network for feature learning. We demonstrate the method using an authentic wafer map dataset, WM-811K. The performance is not only significantly improved after data augmentation, but it also beats the state-of-the art methods, reaching 99.19% accuracy, 99.10% recall, 99.23% precision, 99.96% AUC and 99.16% for F1-score. It clearly demonstrates the method’s efficacy to deal with the imbalanced defect pattern. Our study using saliency map and t-SNE further leads to enhanced interpretability.

The demand for high-performance grinding wheels is gradually increasing due to rapid industrial development. Vitrified bond diamond composite is a versatile material for grinding wheels used in the backside grinding step of Si wafer production. However, the properties of the vitrified bond diamond composite are controlled by the characteristics of the diamond particles, the vitrified bond, and pores and are very complicated. The main objective of this study was to investigate the effects of SiO2–Na2O–B2O3–Al2O3–Li2O–K2O–CaO–MgO–ZrO2–TiO2–Bi2O3 glass powder on the sintering, microstructure, and mechanical properties of the vitrified bond diamond composite. The elemental distributions of the composite were analyzed using electron probe micro-analysis (EPMA) to clarify the diffusion behaviors of various elements during sintering. The results showed that the relative density and transverse rupture strength of the composite sintered at 620 °C were 91.7% and 126 MPa, respectively. After sintering at 680 °C, the glass powder used in this study exhibited a superior forming ability without an additional pore foaming agent. The relative density and transverse rupture strength of the composite decreased to 48.2% and 49 MPa, respectively. Moreover, the low sintering temperature of this glass powder protected the diamond particles from graphitization during sintering, as determined by X-ray diffraction and Raman spectrum. Furthermore, the EPMA results indicate that Na diffused and segregated at the interface between the diamond particles and vitrified bond, contributing to the improved bonding. The diamond particles can remain effectively bonded by the vitrified bond even after fracture.

Lithium niobate LiNbO3 (LN) on insulator wafers (LNOI) representing a submicron-thick LN film bonded to a SiO2 layer deposited on a thick LN substrate have been manufactured recently by ion slicing. Today, LNOI is one of the most promising materials for fabrication of various integrated optical devices, including waveguides, electro-optical modulators, and wavelength convertors, due to their high drop in refractive index at the interface between the film and the SiO2 layer. Creation of the stable domain structures with submicron periods in LNOI will improve the properties of nonlinear optical devices. Periodically poled LN with periods below 300 nm can be used to implement an optical parametric oscillator in the backward configuration. We have studied experimentally the ways to create the stripe domains and periodical domain structures in LNOI with a dielectric layer under the film by local switching. The identified scenarios of the domain evolution were attributed to the ineffective screening of depolarization field. We have shown that stripe domains and periodic domain structures can be produced by scanning with a biased tip only at temperatures above 80 °C. Periodical stable domain structures with periods down to 300 nm have been created.