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We studied about the strength characteristics of the FRP bonding method due to reduce accident on the oceans and protect life for my people. We test tension and bending strength of butt joint, lap joint, V-scarf joint, X-scarf joint. The result of test, it's pattern is similar both tension and bending strength. Tension strength and bending strength was excellent in order to X-scarf-butt joint-V-scarf-lap joint. The tension strength is the best properties X-scarf showed a 57% strength rate of the basic material, and bending strength showed a 77% strength rate of the basic material. Overall, the X-scarf 12t joint has most excellent properties of tension and bending strength. The lap joint has worst properties of tension and bending strength. We have to test having different over-lay of V-scarf and X-scarf joint each 12t, 16t, 20t. V-scarf of 20t over-lay has excellent character of tension and bending strength. But X-scarf of 12t over-lay has excellent character of tension and bending strength. The results are shown to the contrary. The ship is received a lot of stress. it's hard to compare a direction both actual and test. But we can acknowledge material basic characteristic of strength through tension and bending test. We give the four repair method; butt joint, lap joint, V-scarf joint, X-scarf joint and the reduced ratio in comparison with basic material; In addition give the separated data for V-scarf and X-scarf characteristic of 12t, 16t, 20t overlay length. For our study repair man can select good repair method in his work station.

This paper presents a mode to solve visibility issue of touch panel by regulating border profile of sensor pattern. The pattern profile can be effectively optimized by adjusting soft-bake process parameter, mainly temperature and time. This process method is more convenient and lower-cost than the selecting and fabrication of IM layer.

In this study, we have developed high performance TFT (thin film transistor) and a 7.4-inch high resolution LCD (liquid crystal display) panel of full color WSXGA (1600 × RGB × 1024, 257 ppi, 43% aperture ratio) format using ‘sequential lateral solidification (SLS)’ laser crystallization process [Y.J. Kim et al., Grain boundary effect on the characteristics of the high-performance poly-Si TFTs crystallized by SLS Technique, AM-LCD (2005) 249–251]. The gate and data driver circuits were integrated on panel and the integrated drivers comprise a sequential analog sampling data driver and a dual logic gate scanner for redundancy. In addition, we have improved key process for fine image quality. Metal lines used Cu/MoX (5000 A/300 A) for uniform data transfer and array on BM (black matrix) structure for lager aperture ratio was adopted.

By the integrated drive circuitry with laser crystallization process, the gate and data driver circuits required for full color WVGA(800 × RGB × 480) LCD are integrated on panel. The integrated driver comprises a sequential analog sampling data driver and a dual logic gate scanner for redundancy. The characteristics and uniformities of the LTPS (low temperature polycrystalline silicon) devices have been remarkably enhanced by applying stacked SiO2 and SiNx buffer layers and surface treatment.

By the SOP (system-on-panel) technology with laser crystallization process, all the driver circuits required for 6-bit color QVGA (320 × RGB × 240) LCD are integrated on panel. The integrated data driver comprises a new ramp-driven 6-bit DAC. The characteristics and uniformity of the LTPS (low temperature polycrystalline silicon) has been remarkably enhanced by applying multi-shot ELA (excimer laser annealing) process and surface treatment. The characteristics of the poly-Si TFTs for integration of driver circuits are following: (1) in NMOS, V th ∼ 1 V and mobility ∼ 240 cm 2 /V s, (2) in PMOS, V th ∼ −1.8 V and mobility ∼ 100 cm 2 /V s.

In this letter, a novel five-mask low-temperature polycrystalline-silicon (LTPS) complementary metal-oxide-semiconductor (CMOS) structure was proposed to improve cost competitiveness of CMOS products on the market and was verified by manufacturing test samples using the five-mask LTPS CMOS process. Selective contact-barrier-metal formation process was first introduced to solve the high-contact-resistance problem encountered between indium-tin-oxide and doped poly-Si source/drain. The five-mask CMOS devices showed comparable device performances to CMOS devices with conventional structure, i.e., 1.32 V of threshold voltage and 267.6 cm2/Vmiddots of maximum field-effect mobility for NMOS, and those of -1.24 V and 125.2 cm2/Vmiddots for PMOS, respectively.

6Mask CMOS process in low temperature polycrystalline silicon thin film transistors (poly-Si TFTs) has been developed and verified by manufacturing a 6Mask CMOS panel. The 6Mask CMOS structure is suitable for the panel operation with line inversion, where a novel process is adopted to substitute for the storage doping of conventional structure without an additional mask step.

A novel fivemask low temperature polycrystalline silicon LTPS complementary metal oxide semiconductor CMOS structure was verified by manufacturing the thin film transistor TFT test samples using the proposed fivemask LTPS CMOS process. In integrating the fivemask CMOS structure, a selective storage area formation process was developed, without additional photo mask steps, to solve the sputtering damage encountered inevitably in the contact between polycrystalline silicon pSi and storage metal. In addition, the selectively thin dielectric layer increased capacitance per unit area, and thus, increased the aperture ratio of AMLCD panel by reducing the capacitor area without reducing GI thickness in TFT