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The evolution of 3D depth-sensing technology enables various applications in mobile devices, from conventional photography enhancement (e.g., autofocus and bokeh effect) to new applications such as augmented reality and 3D scanning. Usually, 3D depth sensors operate with RGB color sensors for image fusion; the spatial resolution of depth sensors should be compatible to that of RGB sensors for better image fusion quality, which requires mega-pixel depth sensors. Among different depth-sensing techniques, only indirect time-of-flight (ToF) sensors can generate higher resolution depth maps with smaller system cost and power [1,2]. Recent indirect ToF sensors have achieved continuous improvements in depth performance [1–4]. However, one of the issues with indirect ToF sensors is peak current during exposure time [1,2]. To solve the issue, current spreading can be adopted by driving each column group in a different time point; the resulting column fixed-pattern phase noise (FPPN) is compensated by time-interleaving two opposite-directional delay chains [2]. However, this approach suffers from demodulation contrast (DC) degradation around the edge of the pixel array, by combining two different phase signals at the pixel level [2]. Another issue for indirect ToF sensors is multi-user interference [5]. When multiple ToF cameras with the same modulation frequency shine light onto the same object, the reflected light signals interfere each other, which may distort depth information. In this work, a mega-pixel indirect ToF sensor is reported with the solutions for the two issues: 1) peak current mitigation with minimal side-effect, and 2) multi-user interference cancellation.

A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- of high full-well capacity (FWC) per a tap is obtained by employing a supplementary MOS capacitor. 36% of high quantum efficiency (QE) has been achieved by backside scattering technology (BST) and thick silicon process. In addition, demodulation contrast (DC) is improved to 86 % by additional deep photodiode doping process for static potential gradient in a photodiode.

This paper presents an implementation of a CMOS image sensor with a 65 nm CMOS process. The pixel array consists of 13 Mp with 1.12 μm pixel pitch. The fabricated sensor uses 10-bit column-parallel single slope analog-to-digital converters (ADC) based on a low-power readout architecture. Furthermore, a low-power built-in self-test (BIST) is proposed to avoid test over-kills. The proposed image sensor achieves a frame rate of 30–120 frames/s, a temporal random noise of 2 e− rms , a dynamic range of 65.2dB, peak integral non-linearity of 0.18 % and peak differential non-linearity of 0.26 least-significant bits. It consumes only 99.7mW at 30 frames/s.

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.

To evaluate the efficacy of intravitreal ranibizumab with and without pneumatic displacement for the treatment of submacular hemorrhage secondary to neovascular age-related macular degeneration.We retrospectively reviewed the medical records of 93 treatment-naive patients (93 eyes) with submacular hemorrhage secondary to neovascular age-related macular degeneration. All patients were treated with an initial series of 3 monthly intravitreal ranibizumab injections, followed by as-needed injections. For the patients treated with pneumatic displacement, expansive gas was injected at the time of the first ranibizumab injection.Mean submacular hemorrhage area was 8.2 ± 5.8 disk areas, and mean symptom duration was 8.2 ± 5.2 days at baseline. Twelve months into treatment, the mean logarithm of the minimum angle of resolution of best-corrected visual acuity of all subjects significantly improved from 1.19 ± 0.55 (20/309) at baseline to 0.96 ± 0.39 (20/182, P = 0.007) at 12 months. The mean central foveal thickness also significantly improved from 473 ± 223 μm at baseline to 279 ± 134 μm (P0.001) at 12 months. However, no significant difference in best-corrected visual acuity and mean central foveal thickness between ranibizumab monotherapy (58 eyes) and combination therapy groups (35 eyes) was observed at 12 months.Intravitreal ranibizumab injections with and without pneumatic displacement are viable treatment options for submacular hemorrhage secondary to neovascular age-related macular degeneration.

The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1–3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4, 5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.

High performance lateral diffused MOSFETs on a CMOS platform have been developed for handset power applications. The LDMOS, with 0.3 /spl mu/m physical gate length and 7 nm gate oxide, shows high f/sub T/ and f/sub Max/ values up to 32 and 26 GHz, respectively, as well as low on-resistance of 3.1 ohm-mm and high saturated current of about 450 /spl mu/A//spl mu/m. The breakdown voltage is measured to be 14 V. More than 70% efficiency at 900 MHz is demonstrated in a unit power cell with a gate width of 1.92 mm.

An empirical large signal model is presented to have good accuracy for all the device operating regions up to 20 GHz. Skin effects of combining structures, non-reciprocal capacitance, and non-quasi-static effect are considered in this model. A power transistor of 1.92 mm gate width is modeled and compared with measured data. P1dB of 20 dBm, 19 dB gain and 62 % PAE at P1dB in P/sub in/-P/sub out/ properties are exactly predicted by the model.

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. The major source of leakage current on NMOS and PMOS devices was different pathways, and it was controlled by reduction of gate poly-Si oxidation thickness and the optimization of LDD implantation process. The load PMOS lifetime under the HEIP stress was over 10 years at 3.5V of operation voltage. The SNM margin was obtained in subthreshold operation region by increase the current of load transistor and compensated for the process variation. Finally, SRAM cell of 0.84 /spl mu/m/sup 2/ of size with 0.1 /spl mu/m design rule was successfully fabricated.

We have demonstrated a fully integrated 64 kb MRAM using 0.24 /spl mu/m CMOS technology. We found that the etching of magnetic tunnel junctions (MTJ) was likely to bring about an electrical short between the top and bottom of an MTJ, and capping MTJs after etching was very effective in preventing the short. Besides, we performed a lot of magnetic transport measurements of magnetic tunnel junctions during the development and found that the magnetization reversal was affected by some geometrical factors of an MTJ.

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.

With respect to the operation of a Phase-change Random Access Memory (PRAM or PcRAM), we studied the effect of the contact between the electrode metal and the chalcogenide glass, N2 doped Ge2Sb2Te5 in this report. We investigated a change of the resistance-programming current pulse (R-I) curve varying the contact size and the electrode material. Also we tested the surface oxidation of the electrode. We found that the programming current, the resistance of the programmed state (“RESET”) and the erased state (“SET”) were highly dependent on the above parameters. These results are presented and a more effective way to the high density PRAM will be proposed.

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.