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The traditional SOMA cube is a solid dissection puzzle and an educational toy. However, to complete assembly SOMA cube is a difficult challenge for most children and even adults. In this paper, we developed smart electronic intelligent SOMA (iSOMA) blocks that can self-detect each other’s position and contact surface. We also have developed an interactive gaming system based on virtual interactive technology. This interactive gaming system can quickly teach children how to quickly assemble iSOMA blocks and let them learn math and geometry problems through the game. This technology, in addition to being used in assembling puzzles, can also be used in the assembly of real objects in life.

SUMMARY This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.

This work investigates a power line communication (PLC) in a DC power management system comprising master-slave control networks. Microcontroller-based master and slave units are designed with serial ports for communication with a controller and a transmission port to couple the signal to modems at both ends. However, coupling data signals to power line through modulation interfacing circuits is a challenging task. In this work, we used time-division multiplexing (TDM) technique to divide into two timings, Powering Time and Communication Time, on the DC power line and can reduce the complexity of the master-slave network and noise effect on the power line.

This paper presents a FlexRay Transceiver (FRT) with Bus Guardian (BG) used in an in-vehicle network compliance with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. The FRT includes two major parts in the physical layer design: the data transmission part, i.e., Bus Driver (BD), which is used to generate and recognize the electrical characteristics on the bus; the control part, including Bus Driver Controller and Bus Guardian (BG), which is in charge of data path, security, safety, and supervising Communication Controller (CC) in FlexRay communication systems. The proposed FRT with BG design in this work is implemented using a typical 0.18 μm CMOS process. The total core area is 0.88 × 0.84 mm2 and the power consumption is 53.04 mW at a 80 MHz system clock by physical on-silicon measurement.

This paper presents a FlexRay Transceiver (FRT) used in an in-vehicle network compliant with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among ECUs (electronic control unit) installed in a vehicle. FRT at least comprises two major blocks in the physical layer design: the data transmission block, i.e., Bus Driver (BD), which is used to generate signals on the bus and recognize the signal electrical characteristics on the bus; and the control block, i.e., Major Controller, which is in charge of data path, security, and safety. The proposed FRT design in this work is implemented using a typical [email protected] CMOS process. The total core area is 1.01x0.894mm^2 and the power consumption is 76.62mW at a 80MHz system clock.

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2xVDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M 0.18@mm CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184mm^2, while the power supply range is up to 5V. Since the internal reference voltage is 1.0V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.

This brief presents an all-digital frequency synthesizer based on the flying adder (FA) architecture. The FA is a fascinating architecture for frequency synthesizer designs due to its simplicity and effectiveness. The FA-based frequency synthesizer can simply use a set of multiple phase reference signals to generate a desired frequency to achieve fast frequency switching. In the proposed work, the frequency synthesizer adopts an all-digital phase-locked loop to provide a steady reference signal for the FA. The proposed frequency synthesizer is implemented in a standard 0.18-μm CMOS cell-based technology, and the core area is 0.16 mm2. The output frequency range is 39.38-226 MHz, and the peak-to-peak jitter is less than 130 ps.

This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).

This paper presents an in-car networking transceiver front end that is compliant with FlexRay automotive electronic standards. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. In order to resist process and temperature variation, a 20-MHz clock generator with process, supply voltage, and temperature compensation is proposed in this paper. A prototype system as well as a chip implemented by using a typical 0.18 ?m single-poly six-metal CMOS process is reported in this paper. The proposed prototypical transceiver front end has been tested by the thermo chamber and a FlexRay development board to certify its operation in the [-40°C-+125°C] temperature range and FlexRay standards. The power consumption of the whole chip is 43.01 mW at a 10 Mbit/s throughput. The core area of this design is 0.117 mm2. The maximal throughput of the proposed prototypical transceiver front end can reach 40 Mbit/s.

This paper presents the architecture as well as the circuit implementation of a wireless personal area networks (WPAN) modulator/demodulator using 2.45GHz band compliant with the physical layer standard of IEEE 802.15.4. A noncoherent demodulation scheme is employed to resolve the complexity and power dissipation problem, where a phase-shift down sampling method is adopted to detect the maximum phase accumulation which is the location of the correct data. A prototypical system on silicon with core area of 0.39mm^2 has been realized by using 0.18@mm CMOS process. The packet error rate (PER) is measured to be

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads' power dissipation compared to the prior works.

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the VTH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V ).

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also provided in this work. The output of the addition of two 8-bit binary numbers is done in two cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. The data transition detection circuit is used to monitor the state switching of input data. Not only is it proved to be also suitable for long adders, the power consumption is drastically reduced by at most 50% at every process corner.

This paper presents a design of a 72.7ps peak-to-peak (p2p) jitter, 80MHz, phase-locked loop (PLL) circuit for digital video broadcasting over terrestrial (DVB-T) receivers. A step-down voltage regulator is utilized to suppress the coupled supply noise. A zero offset charge pump is employed to eliminate the static phase offset caused by the charge offset when the PLL is in lock. The measurement results on silicon using the TSMC (Taiwan Semiconductor Manufacturing Company) [email protected] 2P4M CMOS process show that the proposed PLL achieves as low as 72.7ps p2p jitter on silicon when the output frequency is 80MHz and the power consumption is merely 10.5mW given a 3.3V power supply.

According to Global Asthma Report 2014, asthma may affect as many as 334 million people today and prevalence. While symptoms and severity vary from person to person, asthma can be deadly in some circumstances. Asthma can be controlled by medicine. However, one of the hardest parts of controlling asthma is making sure patients are getting the right does of medicine through their inhaler based on doctor's instructions. However, the patients, especially children, frequently miss doses or even forget to use it. In this study, our proposed electronic dose counter directly attached to pressurized metered dose inhaler without modification original inhaler structure, that is used to record the times and timestamps of doses actuated by patients. The dose information automatically uploads and displays in an inhaler APP ran on a smartphone. Moreover, the inhaler APP also reminds the patients when they forget to use it in right time. Overall cost of the electronics dose counter is ∼$5. Our low-cost smart inhaler counter with inhaler APP could be lowered healthcare cost and saved lives.

This work proposes a sensor network using the power line communication (PLC) technique in master-slave sensor/control network applications especially using in DC power systems. In the accustomed microcontroller-based master-slave sensor/control network are designed by the serial communication topology and communicates with a controller and coupled the signals with modems in the both ends used the transmission port, nevertheless, coupling modulated digital data signals through modulation circuits to the power line is a challenging task in noising cancelation. Therefore, the time division multiplexing (TDM) technique to separate the timing into two phases, Powering Phase and Communication Phase, on the DC power line was proposed in this work. This method can easily resolve the complexity and the noise effect of the master-slave sensor/control network.

This work demonstrates a real-time bridge structure health monitoring device (HMD) with using three 1-axis accelerometers, Gateway, and analog to digital converter (ADC). The proposed HMD achieves the features of low cost and data synchronization of three 1-axis accelerometers. Furthermore, we develop a packet acquisition program to receive the data from remote sensors and then classify it based on time and date. Compared with 3-axis accelerometer, our proposed 1-axis accelerometers based device achieves 59.59% cost saving with high sensitivity 2000 mV/g.

Our proposed scour monitoring system utilized low-cost commercial sensors, hall-effect sensors (unit price < $1) that is capable of real-time measuring bridge pier scour with resolution of ca. 2.5 cm, and overall cost for single sensor node of our work is at least 40% less expensive than existing work. The hall-effect sensor is evaluated under controlled conditions in a laboratory flume. After scour event, the typical voltage change of the hall-effect sensor is ∼ 300 mV, and the system achieves signal-to-noise ratio performance of 60 dB. Finally, we also provide an equation to predict the time variation of scour depth around pier model. Moreover, our system adopts master-slave architecture has scalability and flexibility for mass deployment. We believe that our system has the potential for further widespread implementation in the field.

This paper presents the first-ever single-inductor programmable-output (SIPO) DC-DC Converters. A SIPO converter is comprised of a DC-DC converter and a Phase-locked Loop (PLL). Based on the input frequency generated internally, the PLL provides the reference voltage for the converter to generate the desired voltage levels. To demonstrate the SIPO design concept, a voltage-mode boost DC-DC converter with a constant duty-cycle pulse control technique is implemented. For an input voltage of 1.5V, the boost converter is programmed to boost the output voltages to 2V to 4V over 90% power efficiency for the load currents ranged from 50mA to 300mA.

This paper proposes a portable three-dimensional (3D) heterogeneous system integration platform with reusable sockets, namely, morphing package Cube (MorPACK Cube). The architecture of MorPACK Cube platform achieves the features of miniaturization and portability without a carrier board. Our proposed MorPACK Cube integrates accelerometer sensor, gyroscope sensor and electronic compasses sensor and then exhibits on Andriod platform through Bluetooth wireless communication. Furthermore, we develop an Mobile APP, namely SigView, to display and analysis the collected data from these sensors. The proposed MorPACK Cube is used for sensor applications to demonstrate the effectiveness, compared with the total area 434cm2 obtained by implementing MorPACK Cube platform with a carrier board, the results show that there are 91.14% area cost reduced by the MorPACK Cube platform without a carrier board. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance than the use of the conventional RCA. The proposed CLA-like 64-bit encoder achieves 1.73 ns which is approximately 20% faster than the use of the conventional CLA.

The paper presents the design of a fast voltage-mode hysteretic buck converter with adaptive ripple controller. The conventional hysteretic converters have the merit of fast response and yet stable operation. However, the output voltage ripple is always higher than the fixed window of the hysteretic comparator. The adaptive ripple controller is a circuit which automatically generates a virtual hysteresis window for the hysteretic comparator such that the output voltage ripples are stable within the fixed hysteresis window according to the load conditions. The hysteretic comparator with the adaptive ripple controller has been designed and implemented with the TSMC .35 CMOS process.

This paper presents a high speed transceiver design with fault detection circuit compliant with FlexRay standards V2.1. An LVDS-like transmitter is utilized to drive the twisted pair of the bus. A current detector is included in the transceiver to detect the operating current so as to prevent over-current hazard. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition in the receiver of the bus. A bus line short-circuit detector is also included in the proposed receiver design.

This investigation presents a low power wake-up detector design to monitor wakening signals in a FlexRay-based car network. The detector is required to wake up the bus driver that is operated in the idle low power mode provided that a wakening signal appears. The proposed detector utilities two low-power comparators with hysteresis function to carry out the required wake-up function and state recognition at the receiver end of the FlexRay bus.

This paper presents a DC-DC step-down converter, which can accommodate the range of input voltage from VDD to sub-3×VDD voltage. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M 0.18 µm CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area is less than 0.184 mm2, while the VDD range is up to 5 V. Since the internal reference voltage is 1.0 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a system chip to provide multiple supply voltage sources.

This paper presents a power-aware signed digital multiplier design by taking advantage of a 2-dimensional bypassing method dedicated for local multiplications widely used in FFT/IFFT operations of video/image processing. The proposed low power multiplier is carried out by Baugh-Wooley algorithm using novel 2-dimensional bypassing cells. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero.

This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to V DD -V thn to enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm CMOS process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm2 and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

This paper presents the physical layer design comprising the Bus Guardian (BG) and Bus Driver (BD) used in an in-vehicle network compliant with FlexRay standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. The Bus Guardian is one of the most important components in charge of security and safety for the FlexRay standards. The Bus Guardian proposed in this work is implemented by hardware description language (HDL) and co-verified with our prior FlexRay transceiver using a typical 0.18 um mixed-signal CMOS process.

A complementary all-N-transistor (CANT) comprising the ANT logic and a novel inverted ANT logic is proposed in this paper. The threshold voltage of the transistors in the ANT logicpsilas N-block is variable depending upon the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-block is raised to VDD - Vthn such that the drain current therein is increased to enhance operation speed. In the pre-charge phase, the bulk voltage of those transistors in the N-block is reduced to its normal voltage level such that the subthreshold leakage current is dropped to reduce power consumption. By utilizing such a variable bulk voltage scheme in the CANT, a 32-bit CLA is designed to justify the low power and high speed performance. The power dissipation is 143 mW at 5.4 GHz clock rate given the worst PVT (SS, 1.08 V, 75degC) condition.

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8times8 multiplier design is reduced by more than 13.8% compared to prior designs.

This paper presents a bus guardian design used in an in-car network compliant with FlexRay standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. An 8051-compatible microcontroller was used to implement the system controller. Most important of all is that the bus guardian (BG) in charge of security and safty is proposed and implemented. This work was implemented by hardware description language (HDL) and verified by Xilinx field-programmable gate array (FPGA).

This paper presents a transceiver design compliant with FlexRay standards. An LVDS-like transmitter is proposed to drive the twisted pair of the bus. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition at the receiver of the bus.

A low-power sensorless inverter controller is designed for brushless DC (BLDC) motors without using any Hall sensor. A back-EMF (back-electromotive force) estimation method is adopted to detect the commutation moment for rotation control of the brushless DC motors. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points. The proposed controller is low power and low cost because of not using expensive power consuming Hall sensors. The proposed sensorless inverter controller is integrated in a standard mixed-signal single-poly, and six metal 0.18-mum CMOS process.

A handheld DVB-T TV with a 3.5" LCD panel for mobile entertainment is presented in this work. A dual-board design is used in such a TV receiver. An MPEGII hardware decoder is included to decode the received signals and generate crystal clear terrestrial broadcast DVB-T DTV programs. In addition, an automatic antenna signal detection method is proposed to determine which of the build-in telescopic antenna or an external antenna is selected to deliver the received signal depending on the quality of the received signals individually. Field trials proved that the TV receiver works perfectly at a signal strength -80 dBm with a moderate mobile speed.

This paper presents a novel design for double-edge triggered flip-flops (DETFF). Detailed analysis of the transistors used in the DETFF was presented to find out those on the critical path. Therefore, the proposed DETFF employs low-Vth transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-Vth transistors can be resolved at the same time. The proposed DETFF, thus, fully utilizes the multi-V th scheme provided by advanced CMOS processes without paying the price of large area, slow clocking frequency, and poor noise immunity. The proposed design is implemented using TSMC 0.18 mum 1P6M CMOS process. Post-layout simulation results reveal that the proposed DETFF saves at least 33 % power and 39 % power-delay product (i.e., the dissipated energy) at all PVT (process, supply voltage, temperature) corners

This paper describes the design and implementation of a sequential access memory (SAM) in the OFDM demodulator of DVB-T receivers. The SAM decoder is based upon a ring counter to reduce the transistor count as well as the number of transitions per memory access. The SAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. The power consumption of memory access is then reduced. A 2-Kb SAM is carried out by 0.18 mum 1P6M CMOS process to verify the proposed design. The average power dissipation of the address decoder is 41.97 muW, while the average power dissipation of the overall SAM is 4.11 mW given a 20 MHz clock rate

This paper presents a low power 8 /spl times/ 8 digital multiplier designs by taking advantage of a 2D bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2D bypassing architecture. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 75% compared to the prior design with obscure cost of delay and area. A physical implementation of the proposed design using a standard 0.35 /spl mu/m 2P4M CMOS process is also presented to justify the functionality as well as the low power performance of the 2D bypassing method.