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Energy-Efficient Double-Edge Triggered Flip-Flop
- Source :
- Journal of Signal Processing Systems. 61:347-352
- Publication Year :
- 2010
- Publisher :
- Springer Science and Business Media LLC, 2010.
-
Abstract
- This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).
- Subjects :
- Imagination
business.industry
Computer science
media_common.quotation_subject
Clock rate
Transistor
Dissipation
Theoretical Computer Science
law.invention
CMOS
Hardware and Architecture
Control and Systems Engineering
law
Modeling and Simulation
Embedded system
Signal Processing
Electronic engineering
business
Cmos process
Critical path method
Flip-flop
Information Systems
media_common
Efficient energy use
Subjects
Details
- ISSN :
- 19398115 and 19398018
- Volume :
- 61
- Database :
- OpenAIRE
- Journal :
- Journal of Signal Processing Systems
- Accession number :
- edsair.doi...........5912c48c84cc43f43ddb061eae3976b3