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Fanout Wafer Level Packaging (FoWLP) is a very attractive solution for microelectronics applications requiring optimized performance, smaller form factor, and low cost. By utilizing such an approach where system integration is done to multiple chips on a single package frame, the need to ensure much higher levels of process integrity, quality, and reliability becomes absolutely critical, especially if the total product volume lies in the range of tens of millions of units. A single defect type may negate the benefits of such an approach because the cost of losing one FoWLP unit results in the loss of multiple devices. Thus, yield, quality, and reliability optimization using such a package solution is critical for successful large scale manufacturing. In this talk, the issue of defectivity and its impact on quality and reliability on Wafer-Level (WL) devices with regards to the issue of Die Edge Delamination (DED) and Chip Mechanical Integrity (CMI) is discussed. Through this discussion and the resulting solutions found to improve WL quality and reliability, better understanding on how to assess the quality and reliability of a given FoWLP solution for large scale production will be demonstrated.

SRAM physical unclonable function (PUF) provides a low-cost security key to address hardware attacks such as cloning as well as for reliability tracking of ICs in the field. In this work the quality and aging reliability of 28 nm high-K metal gate planar and 16 nm FinFET based SRAMs are discussed in detail with regards to their use in PUF. Data indicates that 16 nm FinFET process has a better SRAM PUF quality without any design modifications compared to the 28 nm planar process. In addition, the aging-induced bit instability is shown to be a reasonably small percentage of the overall bit counts.

The photothermal displacement technique has been used to measure the out-of-plane thermal diffusivity in free-standing polymer thin films. The technique can be applied to a single sample as well as a collection of samples of different film thickness. Polymers are well suited for this method because they usually possess a large vertical coefficient of thermal expansion and readily absorb UV laser radiation. In particular, this method yields a value of the thermal diffusivity for polymer films with thickness ranging from 125 to about 10 μm. Different polymers have been studied with particular attention paid to UPILEX-S (biphenyl tetracarboxylic dianhydride-p-phenyl diamine) polyimide whose thermal diffusivity has been determined to be 0.0025±0.0005 cm2/s. Our study shows that the measurements are not strongly affected by uncertainties in the optical absorption coefficient of the polymer as well as photothermal displacement contributions from the backside of the free-standing film. Furthermore, neither the e...

A three-dimensional analytical solution as well as experimental verification of the thermoelastically induced deformation in a substrate-constrained thin polymeric film have been developed. In this model, the elastic deformations of the two layers are treated separately since the typical polymer has a much smaller Young’s modulus but a much larger out-of-plane coefficient of thermal expansion than a silicon wafer. Results from measurements of biphenyl tetracarboxylic dianhydride-p-phenyl diamine thin films on silicon wafers agree very well with calculations based on this analysis, especially by using the sensitive frequency modulation method as outlined in part I of this two-part series. Thus, this development of a two-layer thermoelastic deformation model and measurement has advanced this technique to a thinner thickness scale with improved precision. This method is also amenable to studies of the interfacial thermal resistance Rt, and numerical analysis shows that typical interfacial thermal resistances...

Back-end-of-Line (BeoL) Reliability has been a major concern at least since electromigration (EM) was first identified in the late 1960s as a critical failure mechanism within integrated circuits. Typically, reliability concerns arose because simple technology scaling placed larger current density demands on the metallization system. To slow down the erosion of reliability margin with scaling, Cumetallization using Dual-Damascene (DD) integration was introduced around the 180/130nm node. In addition, low-kdielectrics (2.5

Electromigration (EM) reliability was investigated for Cu/porous low k interconnects. The porous low k dielectric was a methylsilsesquioxane (MSQ) based spin-on organosilicate material with k of 2.2. The activation energy for EM failure was found to be about 0.9 eV for Cu/porous MSQ between 208 and 367 °C, which is commonly associated with mass transport at the Cu/SiNx cap-layer interface. The threshold product of current density and line length (jL)c for Cu/porous MSQ was found to be 2500–3000 A/cm. The reduction in EM lifetime compared with Cu/oxide interconnect can be attributed to smaller back stress, due to less thermomechanical confinement of Cu/low k interconnects. Most interconnects failed by voiding at the cathode. Some lateral Cu extrusion followed by interfacial breakdown was also observed near the anode.

The impact of low-k dielectrics on the reliability of advanced Cu interconnects is of growing importance. As a first step to understanding this impact, we have investigated the effect of two types of polymeric low-k materials on the electromigration (EM) behavior of multilevel Al(Cu) interconnects. The two polymers used as interlevel dielectrics in this work are a fluorinated polyimide and a poly(aryl) ether. Joule heating experiments and microstructural analysis were both conducted on Al(Cu) to ensure that there were no significant microstructural or thermal differences between the polymer samples and their oxide counterparts. The resulting EM behavior can then be directly attributed to differences in the mechanical properties of the low-k and oxide interlevel dielectrics. We have observed that the low-k samples had a higher steady-state drift rate and did not reach saturation, resulting in shorter EM lifetimes. These results indicate that the short length is greatly modified with the incorporation of me...

Electromigration tests at temperatures between 340 and 400 °C and current densities between 1.0 and 3.0 MA/cm2 have been performed to determine the temperature dependence of the critical length effect in 0.5-μm-wide Cu/oxide dual-damascene interconnects with 0.1 μm silicon nitride (SiNx) passivation. A focused-ion-beam-induced contrast imaging technique is used to locate failure sites of critical length test structures. Statistical analysis [E. T. Ogawa et al., Appl. Phys. Lett. 78, 18 (2001)] yields a threshold-length product (jL)c, of 3700 A/cm, and a temperature dependence is not observed within the temperature range 340–400 °C.

Electromigration results have provided clear evidence of a short or “Blech” length effect in dual- damascene, Cu/oxide, multilinked interconnects. The test structure incorporates a repeated chain of Blech-type line elements and is amenable to failure analysis tools such as focused ion beam imaging. This large interconnect ensemble provides a statistical representation of electromigrationinduced damage in the regime where steady-state interconnect stress is manifest. Statistical analysis yields a critical length of 90 μm for interconnects with line width 0.5 μm at j=1.0×106 A/cm2 and T=325 °C.

This letter describes measurement of the biaxial modulus, coefficient of thermal expansion (CTE), and moisture uptake characteristics of hydrogen silsesquioxane (HSQ) thin films. The biaxial modulus and CTE were determined using a bending beam method, and moisture uptake was studied using a quartz crystal microbalance method. The biaxial modulus and CTE of a 0.5 μm HSQ film were measured on Si and Ge substrates and found to be 7.07 GPa and 20.5 ppm/°C, respectively. The value determined for the diffusion constant of water in a 0.7-μm-thick HSQ films is 3.61×10−10 cm2/s at room temperature.

On April 15-19, 2012, the 50th Annual IEEE International Reliability Physics Symposium was held in Garden Grove, CA, USA, commemorating a significant milestone for IRPS as the preeminent conference in the area of microelectronics reliability. The technical program included 29 invited talks, in addition to 75 contributed talks and 70 posters, and was witnessed by 408 attendees. Unique to this conference, all prior 49 years of symposium materials were shared with the attendees in a newly digitized format. The papers at The Symposium showcased a range topics, covering fundamental reliability of transistors, interconnects, back-end dielectrics, and packaging. State-of-the-art developments in reliability of memory devices, circuits (including but not limited to BTI, ESD, and latchup and soft errors), product qualification, failure analysis, process and integration impact on reliability, compound semiconductors, high voltage, and thin-film devices used in commercial, industrial, and harsh or unusual environmental conditions were shown. Applications of reliability assessment pertinent to those found in space, automobiles, renewable energy sources, and medical applications were also highlighted. While it is difficult to properly sample such a wide variety of technical contents, this Special Issue features four extended papers based on the original Symposium submission. In each case, the impact of intrinsic reliability failure mechanism(s) on device or circuit reliability is described, topics that should be of ongoing and lasting interest to the reliability community. An overview of the technical articles is given.

Electromigration (EM) statistics and critical current-density line-length product (jL)/sub c/ were investigated for Cu interconnects integrated with oxide, CVD low k, porous MSQ, organic polymer dielectrics. The EM activation energy was found to be about 0.8 to 1.0 eV, which is commonly associated with mass transport at the Cu/SiN/sub x/ cap-layer interface. The lower EM lifetime and threshold product (jL)/sub c/ can be attributed to a smaller back stress due to less thermomechanical confinement in the low k structures. The confinement effect can be expressed in terms of an effective modulus B to account for EM behavior and threshold products of low k structures. For all the ILDs studied, (jL)/sub c/ showed no temperature dependence but for the organic polymer, j dependence was observed.

Electromigration (EM) characteristics were evaluated on multi-level Al(Cu) test structures with polymeric low k and standard oxide interlevel dielectrics. The two polymers used as interlevel dielectrics in this work are a fluorinated polyimide (FPI) and a poly(aryl) ether(PAE). Joule heating experiments and microstructural analysis were both conducted on Al(Cu) to insure that that there were no microstructural or other differences between the polymer samples and their oxide counterparts. The results show that the integration of polymeric low k dielectrics has a significant impact on EM performance of interconnect structures.

Electromigration (EM) lifetime characteristics and failure mechanism were investigated for Cu/porous-low-k interconnects and compared to Cu/oxide. The porous low-k dielectric was JSR LKD-5109TM, an MSQ-based spin-on organosilicate material with k = 2.2. The activation energies for EM failure were found to be 0.9 - 1.0 eV for the porous MSQ and 0.8 eV for oxide while the current density exponents for both materials were found to be similar, 1.2 - 1.3. This range of activation energies are commonly associated with mass transport at the Cu/cap-layer interface and suggest a similar mass transport mechanism; interfacial diffusion. Porous MSQ structures showed the same distinct failure morphology as observed in other Cu/low-k interconnects: voiding at the cathode and lateral Cu extrusion at the anode under the cap layer, which seems to be related to the thermo-mechanical properties of Cu/low-k interconnects. The shorter lifetime characteristics of Cu/low-k interconnects comparing to Cu/oxide can be attributed to a smaller back stress, due to less thermomechanical confinement. Results of this study indicate that thermo-mechanical properties of low-k interconnects are important parameters in controlling EM reliability of Cu/low-k interconnects.

Electromigration (EM) tests have been performed to determine early failure statistics in submicron dual-damascene Cu/oxide interconnects. Monte Carlo simulation, based on the “weakest-link” model, was developed to characterize and determine the failure modes from the cumulative distribution function (CDF) of multi-link test structures. The existence of two district failure modes (weak and strong) in our test structures was identified, where the weak mode is responsible for early failures. The weak mode is found to be void formation within the dual-damascene via, while the strong mode is associated with voiding that occurs in the dual-damascene trench. The weak mode (early failure) activation energy is found to be 1.0±0.05 eV and seems consistent with void formation that is controlled by interface diffusion between the Cu metal and its Ta diffusion barrier.

Electromigration (EM) characteristics were evaluated for multilevel copper test structures embedded in a CVD SiOC low k inter-metal dielectric. After electromigration stress testing, Cu extrusion along the interface between SiOC and the SiN dielectric diffusion barrier was revealed as the primary cause of EM failure. No evidence of cracking or mechanical weak points was observed in the bulk SiOC film; thus improved EM lifetime is expected from enhancement in the adhesion strength of SiN to SiOC. The calculated EM activation energies for 0.35 /spl mu/m via chains and 0.5 /spl mu/m via chains are 0.82 eV and 0.93 eV, respectively. The current density exponent (n) was measured to be about 1, which is consistent with the void growth mechanism in Cu. The critical length was found to decrease with increasing current density, and the j/spl middot/L/sub c/ product was determined to be approximately 7500 A/cm.

An electromigration study has determined the lifetime characteristics and failure mode of dual-damascene Cu/oxide interconnects at temperatures ranging between 200 and 325 °C at a current density of 1.0 MA/cm2. A novel test structure design is used which incorporates a repeated chain of “Blech-type” line elements. The large interconnect ensemble permits a statistical approach to addressing interconnect reliability issues using typical failure analysis tools such as focused ion beam imaging. The larger sample size of the test structure thus enables efficient identification of “early failure” or extrinsic modes of interconnect failure associated with process development. The analysis so far indicates that two major damage modes are observable: (1) via-voiding and (2) voiding within the damascene trench.

In this paper, we present some results of the newly developed on-wafer photothermal measurement. To study thermal anisotropy, the out-of-plane thermal diffusivity measured from this technique is compared with the in-plane thermal diffusivity by measured by ISTS [1]. In addition to the thermal properties, the agreement with mechanical [2] and optical properties are also shown. The significance of different thermal performance between low K dielectric medium materials and SiO2 suggests that greater attention should be paid to thermal properties for integrated devices with low K materials.

The adhesion of Al(Cu-Si) line structures on thin films of BPDA-PDA with different surface preconditioning were examined by measuring the deformation energy of the metal and interface. The properties of BPDA-PDA/Al(Cu-Si) were examined with atomic force microscopy (AFM). Although different sputtering treatments profoundly affect the adhesive properties, the sputtering does not appreciably change the topology of the BPDA-PDA. We also found evidence that even though the thickness of the interface can be very small (3–5 nm), the polymer/metal interface can greatly affect the deformation behavior of the entire system.

The shrinking line-to-line spacing in interconnect systems for advanced integrated circuit technology and the use of lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual-ramp-rate voltage-ramp-to-breakdown methodology is presented and used here to extract important dielectric-breakdown parameters accurately for minimum-spaced metal lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organosilicate material tested, indicated a very low apparent zero-field activation energy (0.14±0.02eV) and an apparent field-acceleration parameter γ=4.1±0.3cm∕MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown m...