Search

We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260°C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.

As patterning for advanced processes becomes more challenging, designs must become more process-aware. The conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of runtime for designers, and also requires the release of highly confidential process information. Therefore, a more practical approach is required to make the In-Design process-aware methodology more affordable in terms of maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair (PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information. Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and released to check and fix subsequent designs. This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process hotspots in a design, specifically through the use of pattern matching and routing repair.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

In this study, we implemented an auto-correction method for layout of 45 nm standard cells to get design-for-manufacturability (DFM) friendly design. The proposed method avoids lithography hotspot and particle defect, which are the source of systematic and random variation, by utilizing litho simulation and critical area analysis during optimization. In addition, to achieve maximum benefit of standard cell optimization, most of the recommended rules (RR) are applied to the standard cells. To assure the consistency of the optimization result, priority was given for each rule and the optimization is performed based on the priority. Using the proposed method, optimization time decreased tremendously compared to manual correction; therefore, the proposed layout optimization can handle thousands of standard cells with reasonable runtime. Verification results with manufacturing checking deck showed that DFM-friendly index improved by over 4.3% on optimized cells when compared to the original cells.