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A low electromagnetic susceptibility voltage-controlled oscillator (VCO) utilizing a four-leaf-clover-shaped inductor is demonstrated at 5 GHz by 0.18-µm CMOS. A novel chip-level near-field coupling measurement setup resembling the modern 3D stacked packaging scheme is proposed using the integrated passive device (IPD) technology. The IPD coil embedded in the test carrier can generate EM interference on the flip-chip bonded VCO to verify the proposed high EMI immunity VCO. Compared to a VCO with the conventional spiral inductor, a significant improvement over 30 dB in a wide frequency range (maximum of 32.2 dB) in susceptibility is demonstrated by the VCO with the four-leaf-clover-shaped inductor.

A fully integrated CMOS active probe for characterizing conducted electromagnetic interference (EMI) in the gigahertz range is presented. Based on the direct coupling method of International Electrotechnical Commission standard, the active 1- $\Omega $ current probe is designed and realized by a standard 0.18- $\mu \text{m}$ CMOS technology to overcome a large insertion loss of 34.2 dB in the conventional passive probe. A high-precision on-chip 1- $\Omega $ resistance is implemented at the input, followed by a high gain and wideband amplifier in the proposed EMI probe. The measured insertion loss is significantly reduced to $\sim 18$ dB with a bandwidth up to 3 GHz. Also, the conducted emission of a microcontroller unit is tested, which demonstrates that the proposed active probe could capture very low-level high-frequency interference overlooked by the conventional passive probe.

A single-crystal-island (SCI) technique is demonstrated using low thermal budget pulse laser process to fabricate single-crystal islands for monolithic 3D back-end-of-line (BEOL) FinFET circuits. The single-crystallinity are verified with SECCO etch, HREM, TEM, and EBSD. BEOL FinFETs fabricated in the designed single-crystal Si islands exhibit excellent electrical performance and low intra-island variability. To mitigate the effects of island-to-island device variation due to random island crystal orientations, crystal-orientation-tolerant voltage regulator is further proposed by allocating power gating (PG) cells among multiple Si islands, and 42% power noise suppression can be achieved.

For the first time, ultrafast laser annealed BEOL gate-all-around (GAA) transistor and FeFET memory were demonstrated with monolithic 3D near-memory-computing (NMC) circuit. The GAA MOSFETs employing ultrafast picosecond visible laser dopant activation exhibit record-high Ion (nFETs=407 uA/um, pFETs=345 uA/um). The BEOL FeFETs memory exhibits large memory window ΔV th = 1.2V, more than 106 cycle endurance. Moreover, the 3D stackability of the GAA MOSFETs and FeFET memory bit cell enable reduces the area of the NMC circuitry and improve the readout throughput.

A wide-bandwidth V-band quarter-mode substrate-integrated waveguide (QM-SIW) antenna using integrated passive device (IPD) process and flip-chip technology is proposed in this paper. The proposed antenna mainly comprises of four QM-SIW formed by flip-chip cavity structure surrounded a series-type power divider network to achieve circularly polarized radiation. The cavity size is of ${3.2\ \times\ 3.2\ \times\ 0.1}\ {\text{mm}^{3}}$ . The proposed antenna is well suited for compact high-integrated millimeter-wave beam forming wireless communication systems.

The IC stripline, an IEC radiated electromagnetic susceptibility (EMS) method, is utilized for evaluating the injection pulling and locking effects of the voltage-controlled oscillator (VCO). An IC stripline with the bandwidth of 2.5 GHz is realized and the test setup is built. A commercial VCO is tested for demonstration. Another IEC conducted EMS test, direct power injection, is also performed for comparison. The results show the effectiveness of characterizing injection pulling and locking of VCO by using the proposed solution.

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (10 2 ~10 5 ) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.

A high performance X-band quadrature voltage-controlled oscillator (QVCO) is presented. The transformer feedback topology is proposed to combine with the interactive self-switching current bias technique, which can achieve a low phase noise while maintaining low power consumption simultaneously. The measured phase noise is −123.84 dBc/Hz at 1-MHz offset with a 10.56 GHz carrier frequency and the IQ phase error is less than 1.9°. Under a power consumption of 2.4 mW, the proposed QVCO in 0.18- $ {\mu }\text{m}$ CMOS achieves an excellent FoM up to −200.5 dBc/Hz, which is among the best compared with previous works using a similar technology.

A $V$ -band wide-beamwidth left-handed circularly polarized wire-bond antenna is presented in this paper. The proposed design, which is implemented by using integrated passive device process, consists of a 1:4 series-type ring-shaped microstrip power divider and four bond-wire radiators. The design of bond-wire radiator with wide-beamwidth characteristic is described. The design method of power divider is also explained in detail. The proposed antenna has been fabricated and measured. The area of the fabricated antenna is of $2.2 \times 2.2\,\,\textrm {mm}^{2}$ . The simulation and measurement regarding antenna reflection coefficient, radiation pattern, peak gain, and axial ratio are conducted for design validation. The measured results show that the antenna can operate in $V$ -band and the impedance bandwidth with $| {S_{11} } |$ less than −10 dB is from 51 to 67 GHz or more (>28%). The measured peak gain is −0.8 dBi at 58 GHz. The measured axial ratio is less than 3 dB 55 to 65 GHz. The simulated 3-dB antenna beamwidth is more than 180°.

A low-power (LP) $K$ / $K_{a}$ -band mixer with configurable capability is proposed in this paper. The mixer integrates a broadband transconductor stage, bondwire resonators, a broadband local oscillator balun, and a broadband switching stage. The bondwire resonators not only work as a balun for single-ended to differential conversion between the transconductor stage and the switching stage, but they can also be configured to have two or three resonators by controlling the number of bonding bondwires during the chip packaging process. These two and three resonators intentionally designed to have weak and strong magnetic couplings with each other, enable the mixer to exhibit narrowband and broadband frequency responses, respectively. Realized in a 65-nm LP CMOS technology, the mixers configured to have two and three resonators that show the measured conversion gains of 17.2 and 15.5 dB while giving 3- and 5-dB bandwidths from 22.5 to 28.5 and 21.5 to 32.5 GHz, respectively. The measured input third-order intercept points, noise figures, and port-to-port isolations of the mixers with two and three resonators are better than −2.7 and −1.9 dBm, 11.2 and 11 dB, and 25.6 and 25.7 dB, within the bandwidths, respectively. The mixer only consumes 7.1 mW from a 1.2-V supply.

In recent years, several new methods for IC-level electromagnetic compatibility (EMC) testing have been introduced. Therefore, a handy vehicle for IC-EMC testing is required to validate the effectiveness of the new IC-EMC testing methods. This paper proposes an 8051 MCU for IC-EMC testing platform with in-system programming (ISP) and decoupling capacitor (decap) functions. In order to reduce the EMI and improve the EMC properties for the 8051 MCU, decoupling capacitors (decaps) are added to the integrated circuit (IC) design flow. Chip-level design and fabrication technology are fundamental and cost-effective solutions to this issue. A cell-based design flow is used for chip implementation; specifically, TSMC 90-nm technology is used to implement the present chip via the National Chip Implementation Center. This study will implement two 8051 MCU chips: one that internally comprises a large number of decaps, and another that comprises no decaps. We also implemented an IC-EMC testing platform composed of a multifunction test board and several off-board probes that were fabricated according to IEC 61967 and IEC 62132 standards. The platform demonstrates a method for using the proposed two 8051 chips in EMC testing, and we reveal the results of its EMC performance. Finally, this study simulates the EMC properties, compares the two 8051 MCU chips, conducts static or dynamic analyses for the chips in a power network, and measures the EMC improvements.

A 1Ω probe for EMI test is implemented by using a flip-chip integrated passive device (IPD) resistor and a commercial amplifier. Comparing with the conventional 1Ω probe composed of only the passive resistors (a 1-Ω plus a 49-Ω resistor), the proposed 1Ω probe exhibits better gain and noise performance. With the improved sensitivity, it could be helpful for detecting the suspicious EMI of a packaged IC.

A compact 77 GHz 4 × 4 patch array using backside metal grounded GaAs-based integrated passive device (IPD) is realized in this paper. The efficiency of patch array is 83 % with size of 6.6 × 6.3 mm2. The proposed array system is well suited for millimeter-wave high-gain beam forming wireless communication systems.

In this paper, a millimeter-wave (mmW) through-reflect-line (TRL) calibration technique is developed and demonstrated by measuring an integrated passive device (IPD) antenna. The measured and simulated $\vert{S_{11}}\vert$ of AUT are highly consistent from 50 GHz to 100 GHz band. The mmW TRL calibration can provide the high reliability for on-chip antenna measurement environment.

This paper presents a dual-band dual-polarization stacked dielectric resonator antenna (DRA) element design. Two mutually perpendicular bonding wire structures are used for realizing wide bandwidth feeding network. The DRA is implemented in low-cost integrated passive device (IPD) envirnoment. This millimeter wave DRA exhibits wide bandwidth, wide beamwidth and high gain characteristics. It is suitable for dual polarized millimeter wave scanning antenna array system application.

A novel on-chip measurement technique for characterizing conducted electromagnetic emission of integrated circuits in the gigahertz frequency range is proposed. The International Electrotechnical Commission (IEC) direct coupling method is reviewed, and the considerations on improving the applicable bandwidth of the testing probes are discussed. Design of the most critical resistive components for the probes is elaborated to achieve the required accuracy and bandwidth. With the compact chip probes realized by the integrated passive device (IPD) technology, the measurement bandwidth can be significantly extended compared with the conventionally used surface mounted device resistors. The probes are verified to comply with the IEC 61967-4 standard, and an excellent bandwidth up to 15 GHz can be achieved. By connecting the flipped die under test with the probes embedded in IPD substrate (core sizes of the 1- $\Omega $ current probe and 150- $\Omega $ voltage probe are $0.55~\text {mm}\times 0.77$ mm and $0.83~\text {mm}\times 1.49$ mm, respectively), the conducted emission measurement of a 58-MHz oscillator integrated circuit is demonstrated up to 3 GHz.

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as –11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal–oxide–semiconductor technology. The measured voltage conversion gain is –1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

Designing an efficient emitter design is an important step for achieving a highly efficient TPV conversion process. Wavelength-selective emissivity, spectra match between the emitter and TPV cells, and high thermal stability are three main characteristics that must be considered before implementing the emitter. In this work, an indium tin oxide (ITO)/sapphire emitter structure is investigated for TPV application over the temperature range from 200°C to 1000°C. A 1-µm-thick ITO layer is deposited on a 650-µm-thick sapphire substrate. In addition, 50-nm-thick SiO2 is deposited on top of the ITO to enhance the performance of emitter at high temperatures. High-temperature emissivity and absorptivity measurement of the emitter samples are obtained using FTIR and a Hitachi U-4100 spectrophotometer, respectively. The resultant SiO2/ITO/sapphire/stainless-steel planar emitter structure has selective emission with high emissivity of ∼0.8 in the 1–1.6 µm wavelength regime at 1000°C. This emission range lies at the bandgap edge of silicon TPV cells and thus can be used to harness the true potential for making a low-cost thermophotovoltaic system.

A 60 GHz high-gain millimeter-wave (mmW) left-handed circularly polarized dielectric resonator antenna (DRA) array in silicon substrate integrated passive device (IPD) technology for unlicensed V-band (57-64 GHz) application is presented. In the proposed array structure, a 1-to-4 series-type ring-shape microstrip power divider is connected with four bondwire structures feeding four dielectric resonators (DRs). The results show that the antenna can operate in V-band, and the impedance bandwidths with $\vert \vert$ less than -10 dB are from 51.6 to 64.1 GHz. The gain are 9 dBi at 60 GHz. The axial ratio is less than 3 dB from 57.2 GHz to 63 GHz. The proposed antenna is well suited for millimeter-wave high-gain beam forming wireless communication systems.

For the earth observation mission, there are some critical environmental requirements including low-light condition, fast moving objects, high scanning rate. In order to meet these requirements, the Time-Delay-and-Integration (TDI) technique is critical and essential for the sensor part to improve the Signal to Noise Ratio (SNR) performance. National space organization (NSPO) collaborates with National Chip Implementation Center (CIC) on the next generation image sensor. In order to increase SNR under the light-starved condition, a 32-stages digital-accumulator Time-Delay-and-Integration (TDI) CMOS image sensor is adapted to improve the image quality. Besides, it could successfully take several pictures under different TDI stages on a dynamic test bench. The experimental results verified that the 32-stage TDI CMOS image sensor could function well.

A fully integrated low dropout regulator (LDO) with decoupling capacitors (decaps) for high electromagnetic immunity is designed in the standard $\mathbf{0.18} \mu \mathbf{m}$ CMOS technology. The decaps composed of MOS and MoM capacitors are utilized to decouple the high frequency interference. The characteristic of electromagnetic susceptibility (EMS) of the LDO is performed by the direct RF power injection (DPI) measurement up to 18 GHz. The measured results demonstrate the immunity of LDO with decaps is superior to that of LDO without decaps (maximum improvement of 11.6 dB). Also, the wideband DPI measurement is shown to be capable of characterizing the EMS of ICs.

A $\pmb{150-\Omega}$ probe which fully complied with the IEC standard 61967–4 is proposed for the conducted emission testing at IC level. The $\pmb{ 150-\Omega}$ direct coupling method is reviewed, and the concern of precise measurement and the property of easy to use is discussed. The $\pmb{ 150-\Omega}$ network is implemented by the integrated passive device (IPD) process instead of surface-mount devices (SMDs). With the reduced parasitic effect, the proposed $\pmb{ 150-\Omega}$ probe is verified to fulfill the specifications of IEC standard which make the characterization of EMI at IC level guarantee the high precision and high repeatability.

This paper describes the non-fifty ohm X-parameter model measurement system for nonlinear amplifier application so that RF designers can utilize the X-parameter model to design a nonlinear amplifier in a non-fifty impedance situation.

A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 $^{\circ}$ . The EIRP can be further raised to 9.5 dBm as the supply $V_{ DD}$ is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 ${\hbox {mm}}^{2}$ . All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.

This letter presents a new tool of constant loss contours for matching network loss evaluation. With a certain source impedance, the contours illustrate the matching loss while an arbitrary load impedance is matched to the source impedance. The contours are also applied to millimeter-wave circuit design to help designers consider the circuit topologies, transistor sizes, and layout effects. A millimeter-wave CMOS low-noise amplifier has been optimized by using the constant loss contours. The measured results show a low noise figure of 4.85 dB and a gain of 21.0 dB at 79.5 GHz while only consuming 8 mW from a 1.0 V supply.

A dual-band millimeter-wave (mmW) dielectric resonator antenna (DRA) in silicon based integrated passive device (IPD) technology for unlicensed V-band (57–64 GHz) and E-band (71–86 GHz) applications is proposed in this paper. In the proposed structure, dielectric resonator (DR) was fed by using vertical coupling feed architecture to improve the antenna efficiency and gains. The simulated results show that the antenna can operate in V-band and E-band, and the impedance bandwidths with |S 11 | less than −10 dB are from 57.6 to 62.1 GHz and from 77.1 to 81.2 GHz, respectively. The simulated gains are 5.1 dBi at 60 GHz and 5.9 dBi at 80 GHz, respectively. The proposed antenna is well suited for dual-band millimeter-wave high-gain wireless communication systems.

A DC bias board with 9 separate output voltages is proposed for high precision and noise sensitive measurements. The measured results demonstrated an improved baseband noise up to 30 dB at 20 kHz compared with the laboratory power supplier. A voltage-controlled oscillator (VCO) in CMOS is used to benchmark the impact of power supply noise on circuit performance. The proposed bias board achieves a great agreement with the signal source analyzer (SSA) built-in DC source for phase noise measurement at the frequency offset from 3 kHz to 10 MHz, while results based on the typical power suppliers directly show significant spurs and noises as expected. The proposed technique provides an effective and practical solution for the characterization of noise sensitive integrated circuits with the need of multiple biases.

A high-gain flip-chip packaged dielectric resonator antenna (DRA) for THz imaging applications is proposed in this work. The THz DRA is composed of a high-resistivity silicon dielectric resonator fabricated in an integrated-passive-devices (IPD) technology and a feeding patch realized on a 0.18-μm CMOS chip. The DR is flipped and thermo-compressively bonded to the chip by gold microbumps. With a 625-μm thick DR, a higher-order mode of TE δ, 1, 9 can be excited, which greatly enhances the antenna gain. The simulated antenna gain can be 5.9 dBi while providing radiation efficiency of 53% at 340 GHz. A comparison method is proposed to characterize the DRA performance. The measured maximum gain improvement of the proposed DRA over an on-chip CMOS patch antenna can be as high as 4.9 dB at 322 GHz. A CMOS imager with the proposed DRA is also successfully employed to demonstrate a THz transmissive imaging system at 322 GHz.

A high performance X-band quadrature phase voltage controlled oscillator for direct-conversion transceivers in 0.18-μm CMOS is demonstrated. By using the novel 8-shaped transformer topology, the proposed quadrature phase VCO can be operated at reduced dc power consumption while maintaining low phase noise with suppressed EMC (Electro-Magnetic Compatibility) issues Consuming a dc bias current of 5.45 mA with the supply voltage of 1.8V, the QVCO has a frequency tuning range of 570 MHz, a phase noise of −121.12 dBc/Hz at 1MHz offset frequency away from the 10.5 GHz carrier frequency, and an FoM up to 191.9 dBc/Hz.

Two on-chip electromagnetic compatibility (EMC) solutions realized in the standard 0.18 μm CMOS technology are proposed. A slew rate controller for electromagnetic interference (EMI) reduction is demonstrated by increasing the rise and fall time of signal to lower the harmonic energy on FFT spectrum. Besides, a MOS plus MOM decoupling capacitor for both EMI and electromagnetic susceptibility (EMS) issues is proposed to provide a 17.6 % added capacitance than the conventional decoupling capacitors under the same area. The experiment results prove that the proposed EMC strategies are effective and can be utilized in the chip design with low design complexity.

A dual-band antenna-in-package for millimeter-wave (mmW) applications is presented in the paper. The proposed antenna, which consists of a radiating slot and an air-filled cavity, is fed by a microstrip loaded with two tuning open-circuited stubs through a coupling C-shape aperture to achieve dual-band characteristics. The air-filled cavity, which is formed by the space between CMOS chip and integrated passive device substrate after flip-chip assembly process, can reduce loss and improve antenna gain. Simulation and measurement regarding antenna reflection coefficient, radiation pattern, and peak gain are conducted for design validation. The measured results show that the antenna can operate in V-band and E-band, and the impedance bandwidths with the reflection coefficient less than -10 dB are 6.1% and 5.8%, respectively. The measured gains are -2 dBi at 58 GHz and 0.3 dBi at 77 GHz, respectively. The proposed antenna is well suited for dual-band mmW high-data-rate wireless communication systems.

A low-cost broadband bondwire interconnect is proposed for heterogeneous system integration. Transmission lines are incorporated with bondwires to form a two-path structure, which can effectively reduce the bondwire effect. Theoretical analysis is provided using a graphical method and it shows that the interconnect can give widest operation bandwidth from dc up to a maximum frequency fmax if the length of the transmission lines is designed at an optimal electrical length θmax. In particular, θmax only depends on the characteristic impedance of the transmission lines. The achievable fmax is limited by the bondwire inductance, i.e., smaller bondwire inductance is preferred to have wider operation bandwidth. An interconnect from a 0.18-μm CMOS chip to a glass-integrated-passive-device carrier is designed to verify the proposed concept. Measured results show that the insertion loss and the return loss can be better than 3.0 and 13.4 dB, respectively, from dc to 84 GHz. The proposed interconnect shows around 3.2 times bandwidth of a single bondwire alone. To the best of authors' knowledge, this work demonstrates the bondwire interconnect with the widest operation bandwidth for heterogeneous system integration by using system-on-package reported thus far.

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm 2 .

This paper presents a broadband and high-efficiency integrated CMOS-integrated passive device (IPD) power amplifier (PA) with heterogeneous integration of active devices that are fabricated using 0.18 μm CMOS technology and passive components that are fabricated using IPD technology. The passive components that are fabricated using IPD technology have the advantages of high-Q, low-loss performance, and low cost. By replacing the conventional series resonant output matching network of class-E PA with a broadband Ruthroff-type transmission line transformer (TLT), the proposed PA exhibits broadband characteristics. It performs efficiently owing to the benefits of the low-loss TLT and the switching mode operation of the class-E PA. The measurements demonstrate an output power of more than 25.64 dBm and a power-added efficiency (PAE) of more than 40.2% over the bandwidth from 2 to 3 GHz. The peak output power and PAE are 26.18 dBm and 47.4%, respectively.

This article presents a 5-GHz band low phase noise CMOS voltage controlled oscillator (VCO) based on a high quality factor above-IC inductor that is stacked on the top of a 0.18-μm RF CMOS process using wafer level package technology. The measured phase noise of the VCO is −119.8 dBc/Hz at 1 MHz offset frequency, which is an improvement of 6 dB compared to a conventional VCO with on-chip CMOS inductor. The design challenge of the grounding of the above-IC inductor stacked on the CMOS structure is investigated in this work. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2051–2055, 2013

This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

A high gain 60-GHz on-chip dual-polarization dielectric resonator antenna (DRA) in silicon substrate based on Integrated Passive Device (IPD) technology is presented in the paper. In the proposed structure, dielectric resonator (DR) was fed by using wire-bond structures for bandwidth and antenna efficiency improvement. The Simulation and measurement regarding the antenna reflection coefficient and isolation are conducted for design validation. The measurement results show that the antenna can operate in 60-GHz band, and the impedance bandwidth with |S 11 | less than −10 dB is from 52.5 GHz to 63.5 GHz. The peak gain is 5.5 dBi. The proposed design is well suited for System-in-Package millimeter-wave radio front-ends.

A first high-gain 60-GHz PIFA implemented with a silicon substrate Integrated Passive Device (IPD) technology is presented in the paper. The PIFA which was used with L-shape ground structure could change the radiation pattern and enhance the antenna gain. Simulation and measurement regarding antenna reflection coefficient are conducted for design validation. The measured results show that the antenna can operate in 60-GHz band, and the impedance bandwidth with |S 11 | less than −10 dB is 11%. The measured gain is 5 dBi at 60 GHz. The total chip size is 1.05 × 1.25 mm2. The proposed design is well suited for System-in-Package 60-GHz radio front-ends.

This work presents new deembedded techniques for microstrip discontinuities, including bends, T-junctions, and cross junctions. Since the test structures of discontinuity devices include probe pads and interconnects, the deembedded techniques need extra test structures to remove the unwanted effects. Only two line structures are added to simply remove probe pad parasitics and to calculate the required interconnect effects. The discontinuity test structures are rebuilt by measured data and equivalent circuit models. Then, the components in the models can be extracted. Designed test structures are fabricated using standard 40-nm CMOS technology. The modeling results of discontinuity effects are obtained in lumped components from 10 MHz to 67 GHz.

A Ku-band voltage-controlled oscillator (VCO) with a low phase noise is presented in this paper. By increasing the third-harmonic of the fundamental frequency, the transformer-based topology can enforce a pseudo-square voltage waveform in the LC tank to reduce the phase noise. Implemented in a 90-nm standard CMOS technology, the VCO exhibits an average phase noise of −117.2 dc/Hz at 1 MHz offset over a 9.5–11.7 GHz tuning range. The oscillator only occupies 0.2 mm2 while drawing 13.3 mA from the 1.2-V power supply, and the achieved FoM is 185.4 dBc/Hz. The proposed VCO is suitable for applications of satellite communications.

A design of dual-band cavity-backed slot antenna is presented for GPS and S-band radar applications. In the design, a very thin cavity (0.017 λ 0 in thickness at 1.575 GHz) is used to achieve unidirectional radiation. The dual-band responses of the antenna are excited by the slot resonance at 1.575 GHz and waveguide transition effect at 2.4 GHz. Even with very small cavity thickness, reasonable impedance bandwidths are obtained as 1.6% (26 MHz) at 1.575 GHz and 8.4% (203 MHz) at 2.4 GHz. The proposed slot can also be loaded with a spurline to adjust the antenna centre frequency and the phase of the radiated field. All designs in this paper have been validated with experiments. Satisfactory results have been obtained.

This paper presents a 10-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 180 nm technology. We propose a new structure of the charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth. This structure does not only reduce the area of capacitors array and the capacitance of the DAC, but also guarantee the process variation of capacitors.

A 60 GHz CPW bandpass filter (BPF) with two controllable transmission zeros is proposed. The BPF, which utilizes the spiral defected ground structure (DGS) and interdigital structure as the resonators, is designed and fabricated on the integrated passive device (IPD) technology. The proposed filter has the measured 3dB bandwidth of 8.53 GHz (56.54–65.07 GHz) with the insertion loss of 4.84 dB including pads. The center frequency is 60.81 GHz, and the maximum return loss is better than 25 dB in the passband. A good agreement between the simulated and measured results has been shown. By comparing to other reported Si-based V-band BPFs, this work achieves a good fractional BW (FBW) of 14% with a compact size of 0.18mm2.

This paper presents an 8-bit column-driver IC with improved deviation of voltage output (DVO) for thin-film-transistor (TFT) liquid crystal displays (LCDs). The various DVO results contributed by the output buffer of a column driver are predicted by using Monte Carlo simulation under different variation conditions. Relying on this prediction, a better compromise can be achieved between DVO and chip size. This work was implemented using 0.35-μm CMOS technology and the measured maximum DVO is only 6.2 mV.

A high gain V-band on-chip 2×2 dual-polarization dielectric resonator antenna (DRA) array in silicon substrate based on Integrated Passive Device (IPD) technology is presented in the paper. In the proposed structure, dielectric resonator (DR) was fed by using wire-bond structures for bandwidth and antenna efficiency improvement. The simulation and measurement regarding the DRA element reflection coefficient and isolation are conducted for design validation. The simulated results show that the antenna can operate in V-band, and the impedance bandwidth with |S11| less than −10 dB is from 55.7 GHz to 65.8 GHz. The peak gain is 10.3 dBi. The proposed design is well suited for System-in-Package millimeter-wave radio front-ends.

A compact 60-GHz band branch-line coupler using cpacitively loaded lower-ground coplanar-waveguide (LG-CPW) lines has been successfully demonstrated in a glass-substrate integrated passive device technology. The fabricated coupler has a size reduction of more than 83% compared to that of a conventional CPW branch-line coupler. The capacitive loading is achieved by utilizing the signal layer and the LG of the LG-CPW structure to form microstrip open-circuited stubs. The measured results show a phase error of less than 0.5° between the coupler's output ports and an amplitude imbalance of less than 1.2 dB over the frequency band 57-64 GHz. The measurements also show that both the return loss and isolation are better than 25 dB at 60 GHz and better than 15 dB over the 57-64-GHz band. The proposed coupler is well suited for low-cost high-performance system-on-package V-band radio front ends for high data rate applications.