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Either at pixel or driver levels, low-temperature polysilicon (LTPS) is becoming a standard technology for the fabrication of thin-film transistors (TFTs) used in active matrix liquid crystal displays and in active matrix organic light emissive displays. Given the complexity of addressing or pixel circuits, simulation is becoming more and more necessary. In order to reach the required level of simulation efficiency, an accurate model has been developed. This model takes into account all the operating regimes, capacitors contributions, and frequency dispersion effects. In order to be able to simulate large number of matrix pixels and/or integrated drivers, this model is simple enough to allow simulator convergence. Based on 38 parameters, it presents an easy electrical parameters characterization methodology. Moreover, physical parameters use allows an easy modification of the model performances depending on polycrystalline silicon TFT technology properties and evolution.

In this work, the excimer-laser-induced crystallization of a-Si films on SiO2 was investigated using a long-pulse-duration (200 ns) XeCl source. The microstructural analysis of the laser-irradiated area, for incident energy densities comprised between the thresholds corresponding to the surface and full melting, respectively, of the Si layer, was performed by scanning electron microscopy and Raman spectroscopy. A super-lateral-growth regime was evidenced quite comparable to that which occurs when classical excimer laser pulses of short duration (≈20 ns) are used. A numerical simulation of the surface melt dynamics was also performed and compared to the experimental observations.

Polysilicon thin-film transistors (TFTs) are of great interest for their circuit application in the large area microelectronics. A successful circuit design requires an accurate prediction of the circuit performances, which in turn needs a proper modeling of the electrical device characteristics. In this present work the specific aspects of the anomalous current increase in the output characteristics, often called the “kink” effect, are analysed. A new procedure to determine the excess current is presented and we analysed the excess current for different gate voltages, temperatures and device geometries. We show that, from the parameters that can be extracted by analysing a reduced set of experimental data, the excess current can be easily predicted for any bias and temperature condition and also for devices with different geometries. These results can be used to further up-grade the modeling of the electrical characteristics of polysilicon TFTs in circuit simulators.

Polycrystalline silicon thin-film transistors (TFTs) have been fabricated by using a combined fast solid-phase crystallization (SPC) process followed by excimer laser annealing (ELA). The electrical characteristics of the devices, after post-hydrogenation, show average field effect mobilities > 100 cm2/Vs and better noise performance, if compared to conventional SPC-polysilicon TFTs. A main advantage of the presented technique is the reduced sensitivity of the device performances to the energy density used during ELA.

Resume : Dans le contexte des ecrans plats a cristal liquide, on presente dans cet article une analyse detaillee du mecanisme de cristallisation du silicium amorphe par laser a excimeres. On montre en particulier que pour certaines conditions d'irradiation, les couches de silicium polycristallin obtenues permettent de fabriquer des transistors MOS presentant des mobilites n et p (respectivement de 350 et 150 cnvTVs) comparables a celles obtenues avec du materiau monocristallin sur isolant.

Des couches de silicium amorphe de haute purete ont ete realisees dans un reacteur de type LPCVD (Low Pressure Chemical Vapour Deposition) dans des conditions ultra-pures a partir des gaz silane et disilane. L'evolution de la densite de germes par unite de surface est suivie a 580°C par microscopie electronique en cours de cristallisation en phase solide, ce qui permet d'en deduire la vitesse de germination a cette temperature. D'autre part, la variation de la taille des grains, sur les couches completement cristallisees, est etudiee par microscopie electronique a transmission (MET) en fonction de la temperature de recuit La fraction volumique cristallisee des films amorphes en cours de recuits isothermes est suivie par des mesures de conductance electrique in situ. Par combinaison de ces deux methodes de caracterisation nous pouvons remonter avec precision aux parametres thermodynamiques de la cristallisation concernant les deux types de depot.

In this work, we will present a novel graphene synthesis technique, based on the ion implantation of carbon ions into polycrystalline transition metal thin films. Ion implantation is now a routine process developed by the semiconductor industry over the past three decades. It is used to dope the source and drain contact regions as well as to adjust the channel characteristics of CMOS transistors. One of the advantages of ion implantation is that it allows one to precisely control the carbon dose introduced in a particular substrate.

Large Area Electronics (LAE) is becoming a major branch of the electronics industry with 1997 revenues exceeding $ 10b. It is supported by a large industrially-driven research and development effort mainly located in Far-East countries (Japan, Korea, Taiwan). Most of the LAE activity deals with displays along with solar cells or X-ray imagers, and, for all these applications, hydrogenated amorphous silicon (aSi-H) is the material of choice. For about twenty years, polysilicon (polySi) technology has been intensively developed in industrial or public research laboratories but the only successful technology to entre manufacture of large area electronics products was the aSi-H one (and at a much lower scale, the Cd-Se). However, polySi is becoming a challenger for aSi-H as the implementation of low-temperature processes now render this technology (LT-polySi) compatible with large area glass or plastic-type substrates.

Device quality SiO2 thin films were reproducibly fabricated using distributed electron cyclotron resonance (DECR) microwave plasma without substrate heating (substrate temperature

Polycrystalline silicon is a promising candidate for the fabrication of thin-film transistors used to control the pixel voltage of active-matrix liquid-crystal displays. Results are presented on the ultra-high vacuum chemical vapour deposition of silicon thin films and on the gate-oxide deposition at low temperature by distributed electron-cyclotron-resonance-plasma-enhanced chemical vapour deposition. It is shown that high electron mobilities and low off currents characterise the transistors fabricated with these techniques.

The purpose of this work is twofold: (i) to study the damage induced by ion implantation, with special attention to low implanted doses; (ii) to study the efficiency of annealing techniques — particularly incoherent light annealing — in order to relate the electrical activity of implanted atoms to damage annealing. We have used three methods to study the damage induced by ion implantation: (1) RBS (or nuclear reactions) in random or in channeling geometry (2) RX double crystal diffractometry and (3) electrical measurements (free carrier profiling). Damage induced by silicon implantation at doses >10 14 at/cm 2 can be monitored by all three techniques. However, the sensitivity of RBS is poor and hence this technique is not useful for low implantation doses. As device technology requires dopant levels in the range of 5 × 10 12 atoms/cm 2 , we are particularly interested to the development of analytical techniques able to detect the damage at this implantation level. The sensitivity of such techniques was checked by studying homogeneously doped (5 × 10 16 e − /cm 3 ) and semi-insulating GaAs samples implanted with 3 × 10 12 silicon atoms/cm 2 at 150 keV. The substrate temperature during implantation was 200°C. The damage produced in these samples and its subsequent annealing are evidenced by strong changes in X-ray double crystal diffraction spectra. This method hence appears as a good monitoring technique. Annealing of the implanted layers has been performed using incoherent light sources (xenon lamps) either in flash or continuous conditions. Reference samples have also been thermally annealed (850°C, 20 min in capless conditions). The results are compared, and the electrical carrier profiles obtained after continuous incoherent light irradiation indicate that the implanted silicon atoms are almost dully activated. The advantages and disadvantages of incoherent light irradiation are discussed (surface oxidation, surface damage) in comparison with standard thermal treatment.

Based on examples of mass-produced automotive oxygen sensors, we review the different physical principles of such sensors and discuss their manufacturing technologies. Emphasis is put on microionic/microelectronic approaches, which today allow the electronic combustion control concept to be generalized.

Nous avons utilisk des techniques d'analyses nuclkaires et de spectrom6trie de masse d'ions secondaires pour Ctudier le comportement d'oxydes natifs de GaAs enrichis h 1'180 et irradids sous vide au moyen d'un laser Rubis dCclench6. Nous avons examin6 Itincorporation d'160, l'incorporation et les pertes dl180 ainsi que le ddplacement des cations As et Ga hors des sites du rCseau en fonction de la densitd d'dnergie du faisceau laser. Nos rdsultats d&montrent qu'il est nkcessaire d'irradier avec une densitd d'knergie de I'ordre de 0,8 J/cmZ, afin d'dliminer compl6tement les oxydes de surface. Toutefois, avant Climination compl&te, nous observons une dissolution partielle de ces oxydes dans le mat6riau liquide sous-jacent, ce qui a pour effet d'induire un important piCgeage d'oxygine dans les couches resolidifikes. Nous observons de plus que la surface passe de facon continue d'un dtat riche en Ga & un

(100) heteroepitaxial Silicon films with thicknesses in the 0.4-1 μm range have been deposited onto single-crystal substrates of yttria-stabilized zirconia (YSZ) by pyrolysis of SiH 4 at ≈ 980° C. Using the well-known oxygen transport properties of YSZ, we have subsequently been able to grow a buried thermal SiO 2 layer at the Si-YSZ interface, resulting in a Si(100)/amorphous SiO 2 /YSZ(100) structure, in which the most defective part of the initial epitaxial film has been eliminated. The interface SiO 2 layers have been characterized by Rutherford backscattering spectroscopy and scanning electron microscopy. The oxygen transport mechanism through the YSZ substrate is also briefly discussed.

(100) single crystal silicon films have been deposited on (100) oriented yttria stabilized zirconia (YSZ) single crystal substrates. Taking advantage of the high‐temperature oxygen ion and electronic transport properties of YSZ material, we have subsequently grown buried SiO2 layers (with thicknesses in the 1000‐A range) at the Si/YSZ interface, the result being a Si(100)/a‐SiO2/YSZ (100) structure. Since, similarly to silicon films on sapphire, the planar defect density in as‐deposited material is highest at the Si/substrate interface, the oxidation process results in an overall increase of the crystalline quality of the epi‐Si deposits. We present here our first results of thermal and anodic oxidation of the interface. The buried SiO2 layers have been characterized by Rutherford backscattering spectroscopy and scanning electron microscopy on chemically delineated cross sections. Thermal oxidation has been performed at typically 1150 °C with oxygen pressures ranging from 10−1 to 2 atm. In our operating c...

Gallium arsenide single crystals and thin GaAs amorphous deposits (in the 100‐nm range) on Si have been irradiated by pulsed (15 ns) ruby laser under various pressures of 16O2. All the samples were anodically preoxidized in order to obtain a 10‐nm‐thick 18O enriched oxide, the aim being to study the influence of native oxide on oxygen incorporation during irradiation. Nuclear microanalysis and channeling experiments provide information on (i) 16O incorporation, (ii) 18O losses and concentration profile, (iii) Ga and As atoms out of crystallographic sites for single crystal irradiations, and (iv) Ga and As losses for thin films irradations. Our results demonstrate that a surface oxide is formed with a composition near the Ga2O3‐As2O3 stoichiometry via oxygen penetration in the melted layer once the native oxide has been evaporated at irradiation energies above 1 J/cm2. Before complete evaporation,this latter oxide diffuses in GaAs and is responsible for defect creation at irradiation energies as low as 0.4...

The selective growth of GaAs by HVPE was studied on (001), (110), (111)Ga and (111)As, GaAs patterned substrates by varying the I1I/V ratio. A kinetic modelling of the growth was developed, based upon the SEM observations of the growth morphologies as well as on experimental curve synthesis. The growth rate is written as a function of the diffusion fluxes of the adsorbed AsGa and AsGaCI molecules and takes into account the chlorine desorption by H2. 1.5 μm thick GaAs films were then fabricated on Si (001) by a confined epitaxial lateral overgrowth technique. These conformal films exhibit intense and uniform luminescence signals, showing that the dislocation densities of GaAs are lower than 105 cm−2. SEM analyses reveal that conformal growth fronts consist in (110) and (111)As A planes under the III/V ratios (superior to 1) which were tested.

Direct-view active matrix liquid crystal displays (AMLCDs) are now fabricated in very large volumes using amorphous silicon (a-Si:H) technology. For this purpose, high temperature polysilicon technology is currently used in Japan, with the active matrix fabricated on a quartz substrate. However, quartz substrates of display quality are rather expensive and low temperature polysilicon technology on glass substrates using laser annealing has been introduced as one possible alternative. Recently the transfer of single-crystalline Si layers on glass has been reported. In this case, circuits are fabricated on SOI substrates obtained by a zone melting recrystallisation process and transfered on the glass after completion of almost all the processing steps. This technique is of interest, as high temperature processing steps and fine design rules can be utilized. The main drawback of the technique is that the transfer operation is the final step. We propose an alternative and new technique based on the transfer before processing of a single crystalline Si layer on glass. Processing is subsequently performed at low temperature, using technological steps developed for the fabrication of low temperature polysilicon devices. A SIMOX substrate is thermally oxydized and then bonded at 450/spl deg/C to the glass substrate (Corning 7059 or 1737). The silicon substrate and the thin buried oxide are then removed by a combination of mechanical and chemical etching.

Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.