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Four emitters based on the naphthyridine acceptor moiety and various donor units exhibiting thermally activated delayed fluorescence (TADF) were designed and synthesized. The emitters exhibited excellent TADF properties with a small ΔE ST and a high photoluminescence quantum yield. A green TADF organic light-emitting diode based on 10-(4-(1,8-naphthyridin-2-yl)phenyl)-10H-phenothiazine exhibited a maximum external quantum efficiency of 16.4% with Commission Internationale de L'éclairage coordinates of (0.368, 0.569) as well as a high current and power efficiency of 58.6 cd/A and 57.1 lm/W, respectively. The supreme power efficiency is a record-high value among the reported values of devices with naphthyridine-based emitters. This results from its high photoluminescence quantum yield, efficient TADF, and horizontal molecular orientation. The molecular orientations of the films of the host and the host doped with the naphthyridine emitter were explored by angle-dependent photoluminescence and grazing-incidence small-angle X-ray scattering (GIWAXS). The orientation order parameters (ΘADPL) were found to be 0.37, 0.45, 0.62, and 0.74 for the naphthyridine dopants with dimethylacridan, carbazole, phenoxazine, and phenothiazine donor moieties, respectively. These results were also proven by GIWAXS measurement. The derivative of naphthyridine and phenothiazine was shown to be more flexible to align with the host and to show the favorable horizontal molecular orientation and crystalline domain size, benefiting the outcoupling efficiency and contributing to the device efficiency.

PurposeTo build machine learning models for predicting the risk of in-hospital death in patients with sepsis within 48 h, using only dynamic changes in the patient's vital signs.MethodsThis retrospective observational cohort study enrolled septic patients from five emergency departments (ED) in Taiwan. We adopted seven variables, i.e., age, sex, systolic blood pressure, diastolic blood pressure, heart rate, respiratory rate, and body temperature.ResultsAmong all 353,253 visits, after excluding 159,607 visits (45%), the study group consisted of 193,646 ED visits. With a leading time of 6 h, the convolutional neural networks (CNNs), long short-term memory (LSTM), and random forest (RF) had accuracy rates of 0.905, 0.817, and 0.835, respectively, and the area under the receiver operating characteristic curve (AUC) was 0.840, 0.761, and 0.770, respectively. With a leading time of 48 h, the CNN, LSTM, and RF achieved accuracy rates of 0.828, 0759, and 0.805, respectively, and an AUC of 0.811, 0.734, and 0.776, respectively.ConclusionBy analyzing dynamic vital sign data, machine learning models can predict mortality in septic patients within 6 to 48 h of admission. The performance of the testing models is more accurate if the lead time is closer to the event.

New derivatives of trifluoromethyl benzene and tert-butyl disubstituted acridan or phenothiazine were designed and obtained by single-step synthesis, i.e., by Buchwald-Hartwig cross-coupling reactions of 1,3-dibromo-5-(trifluoromethyl)benzene with 3,7-di-tert-butyldimethylacridan, or 3,7-di-tert-butyl-10H-phenothiazine. The advantages in high thermal and photophysical characteristics were utilized in exciplex emission based OLEDs. In the optimal case, device showed maximum current, power, and external quantum efficiencies of 27.4 cd/A, 28.6 lm/W and 7.6%, respectively. Taking into account that successful employment of acridan or phenothiazine derivatives as donors in exciplex-forming systems remains scarce, the proposed design of donor compounds in this work shows their potential for successful implementation in complex emissive systems of OLEDs.

Monolithically electro-absorption modulating the DFBLD with pre-emphasized PAM-4 data at 52 Gbaud (104 Gbit/s) for back-to-back link and 48 Gbaud (96 Gbit/s) after 10-km-long SMF transmissions is demonstrated for inter-data-center application.

This paper proposes a modularized three-dimensional (3D) heterogeneous system integration platform architecture, namely, MorPACK (morphing package). The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. An efficient reconfiguration is enabled thanks to the use of system bus interfaces and exchange the bare die/module by system dividing and tri-state interface connecting. Six SoC projects/designs are implemented to demonstrate the effectiveness of the proposed MorPACK platform. The average silicon area of each project is about 122.59 mm2 using the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 587.44 mm2 obtained by implementing these projects separately, the results show that there are 79.13% fabrication cost reduced by the MorPACK platform. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

This paper presents a boundary scan test solution for three-dimensional (3D) heterogeneous system integration platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. In order to verify the function of MorPACK platform, the interconnection wire is a critical component between circuit modules and connection modules on PCB board. The boundary scan test is used to check the correctness of interconnection wire on PCB board and then achieves high fault coverage and high quality. The simulation results show that the proposed boundary scan test solution is slightly increased in area and timing of ARM CPU with 1.4% and 1.9% respectively. The south-bridge only consumes the area plenty with 4.5%. Therefore, the proposed method can arrange the routing of PCB board to achieve the verification of interconnection wire and then obtains the small area cost without addressable scan port chip.

This paper presents a novel design flow for three-dimensional (3D) heterogeneous system prototyping platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. Based on system partition and tri-state interface connecting, the MorPACK system can be efficiently extended by system bus interfaces and can improve the functions by only updating the bare die/module. In addition, the total silicon prototyping cost of heterogeneous SoC projects can be greatly reduced by sharing the MorPACK common system platform. To demonstrate the effectiveness of the proposed platform, six SoC projects are implemented. The results show that there are 79.13% fabrication cost reduced by the MorPACK platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited.

This paper presents an efficient memory controller VLSI design for integrating a 3D heterogeneous MorPACK system. The MorPACK system is a platform-based integration system and its structure is stacked by heterogeneous sub-modules. In order to reduce fabrication cost and increase the flexibility of memory extension, a novel multimode memory controller is proposed in this paper. The multimode memory controller supports NOR flash, NAND flash, and SDRAM memory with a wide capacity range. Hence, different MorPACK systems for various applications can be integrated by using the same multi-mode memory controller to satisfy different memory requirements. To demonstrate the effectiveness of the proposed methodology, three single-mode memory controllers are also implemented. With the technique of sharing one system-side signals, the pin count can reduce 41.9% while the pin count can reduce 19.2% by applying the technique of sharing memory-side signals. The total silicon area of single-mode memory controllers is about 6.83-mm2 in the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 3.1-mm2 of our proposed multi-mode memory controller, the results show that there are 54.7 % fabrication cost reduced.

This paper presents a thermal analysis result for a 3D heterogeneous embedded system integration MorPACK (morphing package) platform. The MorPACK platform is stacked by heterogeneous submodules composed of bare dies, a substrate, connection bridges, and solder balls. Since the tiny, heterogeneous and integrable characteristics of MorPACK platform, it needs to be fabricated in high-density and laminar structure. The cooling ability of forced convection is restricted. This study presents an important characteristic for this 3D structure and two indications to optimize thermal solution for MorPACK structure. The characteristic shows the lowest layer owns the best cooling condition, so the bare die chip with highest power consumption should be placed on the lowest layer. It achieves cooling a 0.45-W consuming chip by 12-degree more than it put on the top layer. One of the indications shows the vertical thermal conductivity can be improved by filling up whole MorPACK with mold material. This skill efficiently cools down the 0.45-W consuming chip by 10-degree more than non-filled-up structure. The other indication shows removing the connection bridges and cutting out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPACK can be minimized and also reduce thermal resistance in out-plan direction.