Search

Poster session 2, September 22, 2022, 12:30 PM - 1:30 PM It is known that the incidence and epidemiology of candidemia vary according to different geographic regions and/or hosts. Between 1998 and 2019, the incidence in a university hospital in the city of Buenos Aires Argentina, ‘HCJSM’, was 2.19/1000 discharges. The coronavirus disease 2019 (COVID-19) pandemic altered the previously recognized course of severe infections, including candidemia. Objective The aim of this report is to determine the incidence of candidemia in critically ill COVID-19 patients, and the clinical and microbiological aspects of these episodes hospitalized at HCJSM. Methods The source documents of this retrospective study are medical records from patients with Sars-Cov-2 and candidemia who were diagnosed between March 1, 2020 and June 30, 2021. At the onset of the pandemic, the HCJSM began admitting patients with COVID-19, and elective procedures were canceled. Demographic, clinical, and laboratory data were reviewed. All data were analyzed using RStudio, a statistical computing platform (version 4.0.2). Results During the period under review, 61 episodes of candidemia were identified: 23 episodes (39.7%) in COVID-19 patients, and 38 episodes (60,3%) in no COVID-19 patients. Incidence (x 1000 admission) in no COVID-19 patients was 2.5 (38/14 903): in COVID-19 patients 14.4 (23/1595) and in COVID-19–ICU was 42.3 (20/472). The average age of patients is of 65 years (32-84 range years). The time from admission to ICU to the development of candidemia had a median of 18 days (RIC 9-23). A total of 87.5% of the patients had been on mechanical ventilation and 100% of the patients received broad-spectrum antibiotics and had catheters. Episodes were caused by C. parapsilosis (39.7%), C. albicans (35%), C. glabrata (14%), and other species of Candida (11%). A total of 62% of COVID-19 patients who developed episodes of candidemia died during the period under examination. The survival likelihood at 30 days of COVID-19 patients who developed candidemia was higher for C. parapsilosis episodes and lower for C. glabrata episodes. Conclusion The incidence of candidemia showed an increase in COVID-19 hospitalized severe patients. The use of broad-spectrum antibiotics, the presence of catheters, and the use of ventilatory support in COVID-19 patients were the risk factors most associated with the development of candidemia. Although the number of episodes of candidemia is low, without the strength of statistical analysis, it is important to consider that the likelihood of survival of patients with episodes of candidemia varies according to the species recovered.

We investigate 3D charge-trap (CT) nand flash cells using device-physics based multi-scale simulations to explore their potential and optimum operating conditions as electronic synapses of the neuromorphic hardware. A set of figure of merits (FOMs) has been adopted to indicate their goodness of operation under incremental pulse inputs. The results of this study suggest that excellent synaptic FOMs can be attained from 3D CT nands by designing and calibrating the input pulse trains. The impact of variations of device dimensions on charge capture and release phenomena have been investigated and linked to output characteristics in order to obtain intuitive guidelines for attaining desired synaptic functionalities. By co-designing gate dielectric stack and input pulses, the threshold voltage (VT) of the 3D CT cell can be sequentially increased and decreased in a linear and symmetric fashion, providing a large number of distinct VT levels with good retention characteristics. Statistical simulations suggest that device-to-device variations of electrical responses have a negligible impact on the synaptic capabilities of these devices. It has also been shown that the incorporation of deeper traps through material engineering improves synaptic reliability of the 3D CT cells under prolonged operations.

Dielectric breakdown in 2D insulating films for future logic device technology is not well understood yet, in contrast to the extensive insight we have in the breakdown of bulk dielectric films, such as HfO2 and SiO2. In this letter, we investigate the stochastic nature of breakdown (BD) in hexagonal boron nitride (h-BN) films using ramp voltage stress and examine the BD trends as a function of stress polarity, area, and temperature. We present evidence that points to a non-Weibull distribution for h-BN BD and use the multi-scale physics-based simulations to extract the energetics of the defects that are precursors to BD, which happens to be boron vacancies.

We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current ( ${J}$ – ${V}$ ), capacitance ( ${C}$ – ${V}$ ), and conductance ( ${G}$ – ${V}$ ) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce ${J}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal–insulator–metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data is understood, and the atomic structure of the relevant stack defects is identified.

III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature. The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data. In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled ‘border traps’) and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results. Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures. [1] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” John Wiley & Sons, New York, 1982. [2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997). [3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020) [4] G. Sereni, et al. “IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).

Discovery of ferroelectricity (FE) in binary oxides enables the advent of FE memories and a plethora of novel CMOS compatible building blocks spanning from the logic domain to high-density storage and neuromorphic computing. In this paper we develop the first comprehensive model of vertical Ferroelectric Field Effect Transistor, V-FeFET, to identify sources of variability, understand retention problems, and point a path to improving reliability and enabling high-density storage FE memories with extended endurance.

The ferroelectric HfO 2 based field effect transistor (FeFET) has been under research for many years and shows unique properties for applications in the field of emerging memories and in-memory computing. This work for the first time demonstrates how a target programming algorithm can improve the FeFET device characteristics with respect to endurance performance and variability for small device geometries. With this technique the threshold voltage V t of the memory cell can be targeted to any desired value, which is essential for multilevel cells and analog in-memory computing as used in AI accelerators. The switching, trapping and detrapping characteristics of the cell and their influence on the target programming algorithm are presented. The trapping and leakage characteristics are modelled using the GinestraTM simulation software to extract the trap distribution in ferroelectric HfO 2 . Finally, a model for the underlying mechanism of the endurance degradation is proposed.

The biography of Irnerius (ca. 1055–ca. 1125) and his scientific production remain—chiefly in recent years—one of the most debated and controversial issues among historians. In this chapter, I expound my personal views in the hope of shedding some light on the whole problem. The very first teacher of what, in the following decades, became the University of Bologna, Irnerius boosted the renewed study of the Roman-Justinian law (almost neglected for five centuries) that still today constitutes the basic foundation of the legal Western civilization. In his glosses to the Corpus Iuris Civilis (probably the sole reliable evidences of Irnerius’s activity in the legal field) he revealed himself not only as a refined technician, a subtle logician, and an acute lawyer, but also as a man endowed with a noteworthy religious and ethical sensitiveness leading, in time, to firm and permanent achievements (e.g., in terms of individual freedom, human dignity, and social equity) commonly shared by modern world.

We use experiments and device simulations to investigate pulsed SET operation of HfO2-based RRAM devices for their possible use as electronic synapses. The application of a train of identical pulses only allows for an abrupt change of the device current, which is not suitable for synaptic devices. By using simulations, we link the microscopic properties and changes of the conductive filament during the pulsed operation to the measured conductance and its dependence on pulse voltage, width, and number. The results allow us to derive guidelines that we use to design optimized SET pulses (or pulse trains) allowing extending the conventional binary operation of HfO2-based RRAMs to the multi-level cell operation required by electronic synapses.

The breakdown (BD) sequence in high-K/interfacial layer (HK/IL) stacks for time-dependent dielectric breakdown (TDDB) has remained controversial for sub-45 nm CMOS nodes, as many attempts to decode it were not based on proper experimental methods. Know-how of this sequence is critical to the future design for reliability of FinFETs and nanosheet transistors. We present here the use of radiation fluence as a tool to precisely tune the defect density in the dielectric layer, which jointly with the statistical study of the soft, progressive and hard BD, allow us to infer the BD sequence using a single HfO2–SiO x bilayered MOS structure.

RRAM devices have been subjected to intense research efforts and are proposed for nonvolatile memory and neuromorphic applications. In this paper we describe a multiscale modeling platform connecting the microscopic properties of the resistive switching material to the electrical characteristics and operation of RRAM devices. The platform allows self-consistently modeling the charge and ion transport and the material structural modifications occurring during RRAM operations and reliability, i.e., conductive filament creation and partial disruption. It allows describing the electrical behavior (current, forming, switching, cycling, reliability tests) of RRAM devices in static and transient conditions and their dependence on external conditions (e.g., temperature). Thanks to the kinetic Monte Carlo approach, the inherent variability of physical processes is properly accounted for. Simulation results can be used both to investigate material properties (including atomic defect distributions) and to optimize stack and bias pulses for optimum device performances and reliability.

Editor’s note: Retention time is one of the key parameters of emerging memories, which define the time duration the data can be retained when the power supply is removed. In this work, the authors investigate the forming voltage and the data retention of aluminum (Al)-doped HfO2-based RRAM devices and suggest a way to improve the device’s data retention time. ——Yiran Chen, Duke University

3D NAND Flash represents the unmatchable non- volatile memory concerning the bit-cost scaling efficiency and a role model for all emerging memories. Yet some reliability features of these devices i.e. quantification of the threshold voltage shift due to the lateral and vertical migration/loss of charges (LCL and VCL, respectively) is not fully understood. In this study we use a multi-scale modeling approach start from identification of the defects responsible for the charge trapping and quantify the LCL and VLC. As a part of engineering of the barrier we investigate also band-gap engineered (BGE) devices. We show that LCL dominates the charge loss during the retention and that highest portion of injected charge ends up in Al 2 O 3 layer of BGE device.

In this chapter, we focus on the necessary interplay between “modeling for characterization” and “characterization for modeling” approaches for a detailed yet manageable physics-based description of resistive random access memory (RRAM) device operations. Particularly, the “modeling for characterization” is based on a multiscale modeling platform that accounts for all the relevant physical mechanisms involved in charge transport and structural changes at the basis of resistive switching. The “characterization for modeling” instead provides a set of specific characterization methodologies to support the simulation engine and to confirm its results. The excellent agreement between the multiscale model predictions and the experimental results obtained on different material systems and device structures confirms the accuracy of the proposed solution. This makes the proposed platform a tool for the analysis of RRAM technologies and TCAD-assisted material/device codesign, potentially accelerating the introduction of RRAM-based solutions for several different applications.

In this paper we present a comprehensive examination of the characteristics of complex Random Telegraph Noise (RTN) signals in Resistive Random Access Memory (RRAM) devices with TiN/Ti/HfO2/TiN structure. Initially, the anomalous RTN (aRTN) is investigated through careful systematic experiment, dedicated characterization procedures, and physics-based simulations to gain insights into the physics of this phenomenon. The experimentally observed RTN parameters (amplitude of the current fluctuations, capture and emission times) are analyzed in different operating conditions. Anomalous behaviors are characterized and their statistical characteristics are evaluated. Physics-based simulations considering both the Coulomb interactions among different defects in the device and the possible existence of defects with metastable states are exploited to suggest a possible physical origin of aRTN. The same simulation framework is also shown to be able to predict other temporary phenomena related to RTN, such as the temporary change in RTN stochastic properties or the sudden and iterative random appearing and vanishing of RTN fluctuations always exhibiting the same statistical characteristics. Results highlight the central role of the electrostatic interactions among individual defects and the trapped charge in describing RTN and related phenomena.

In this paper, we thoroughly investigate the characteristics of the ${\rm TiN/Ti/HfO}_{2}/{\rm TiN}$ resistive random access memory (RRAM) device. The physical mechanisms involved in the device operations are comprehensively explored from the atomistic standpoint. Self-consistent physics simulations based on a multi-scale approach are employed to achieve a complete understanding of the device physics. The latter includes different charge and ion transport phenomena, as well as structural modifications occurring during the device operations. The main sources of variability are also included by connecting the electrical response of the device to the atomistic material properties. The detailed understanding of the device physics allows developing a physics-based compact model describing the device switching in different operating conditions, including also the effects of cycling variability. Random telegraph noise (RTN), which constitutes an additional variability source, and its relations with cycling variability are analyzed. A statistical link between the programmed resistance and the worst-case RTN effect is found and exploited to include RTN effects in the compact model. Finally, we show how implementing an advanced programming scheme tailored on the device physics allows optimal control over variability and RTN, eventually achieving reliable and RTN-resilient two-bits/cell operations.

After more than a decade working with graphene there is still a preoccupying lack of commercial devices based on this wonder material. Here we report the use of high-quality solution-processed graphene sheets to fabricate ultra-sharp probes with superior performance. Nanoprobes are versatile tools used in many fields of science, but they can wear fast after some experiments, reducing the quality and increasing the cost of the research. As the market of nanoprobes is huge, providing a solution for this problem should be a priority for the nanotechnology industry. Our graphene-coated nanoprobes not only show enhanced lifetime, but also additional unique properties of graphene, such as hydrophobicity. Moreover, we have functionalized the surface of graphene to provide piezoelectric capability, and have fabricated a nano relay. The simplicity and low cost of this method, which can be used to coat any kind of sharp tip, make it suitable for the industry, allowing production on demand.

We present in this paper a multiscale modeling platform that is used to study the effect of atomic level defects on the electrical characteristics of nanoscale devices. This allows identifying ways to engineer material (and defects) and device properties to achieve optimum performance and reliability in logic and memory circuits. Atom scale defects in multilayer thin film material stacks have a profound effect on the electrical performance and reliability of nanoscale electronic devices. These defects include both point defects such as vacancies and interstitial ions as well as extended defects such as grain boundaries, dislocations. We developed a multiscale modeling platform connecting the atomic material properties to the electrical device performance, which allows understanding the optimum material characteristics for different types of logic devices and memory cells. These include logic devices, conventional memories (e.g. DRAM, 3D-NAND) as well as emerging devices (e.g. RRAM, PCM). The simulations allow learning how to scale these technologies through material and process improvement and how to co-optimize materials and devices. I. MULTISCALE MODELING Figure 1 shows the flowchart of the multiscale multiphysics simulation platform along with its main blocks [1]. The ab-initio material properties relevant for the electrical device performances (e.g. bandgap, permittivity, defects energies, defect diffusion barrier ...) are computed using DFT calculations (gray portion). These material properties are then used for the device level simulations (green portion), and the output device electrical characteristics allows calibrating the circuit simulations (yellow portion). The device simulator couples classical and quantum charge transport mechanisms with stress induced material changes (e.g. atomic breakage, creation and diffusion of ions/vacancies), whose occurrence probability is calculated by accounting for the temperature increase and power dissipation associated with the current. The charge transport mechanisms include drift/diffusion in conduction band (CB) or valence band (VB), which is the primary carrier transport mode in semiconductors, and Trap Assisted Tunneling (TAT), which is the dominant mechanism in dielectrics and amorphous semiconductors. Defects with energy levels in the bandgap play a crucial role in the conduction, assisting electron transfer. The charge transport is coupled to the kinetics of atomic level material modifications caused by electrical and thermal stresses encompassing distortion and breakage of bonds, diffusion of vacancies and interstitial ions leading to changes in local fields, stoichiometry and phase changes including ferroelectricity. This allows modeling the reliability of devices to be calculated in addition to static electrical characteristics as well as the device variability. In this presentation, we will show how this multiscale simulation platform can be used to extract defect properties for advanced logic stack as well as to understand the physics of operation of RRAM devices. II. UNDERSTANDING DEFECT IMPACT ON LOGIC STACKS The multiscale approach presented in Section II can be used to characterize and understand the role of the dielectric defects on device electrical characteristics and reliability. Oxide defects are at the bases of the most relevant reliability phenomena in both logic and memory devices, e.g. Random Telegraph Noise (RTN), Bias Temperature Instabilities (BTI), Stress Induced Leakage Currents (SILC) and breakdown (BD). Identifying their nature and their spatial/energy distributions in the dielectric stack is crucial for process optimization and device operation/reliability improvement. The developed simulation framework implements a fast defect spectroscopy (DS) technique based on the modeling and simulation of the charge transport within the dielectric. This technique is applied to identify the defects responsible for I-V, CV. GV in a variety of different stack configurations. III. UNDERSTANDING RRAM OPERATIONS We used this modeling platform proposed to investigate the kinetics of the operation processes of HfO2-based RRAM devices. Forming, set and reset operations are consistently described within the modeling framework described in Section II, accounting for species (i.e. O ions and vacancies) generation, recombination and diffusion. Simulations can reproduce the evolution of the current simulated for a full cycle comprised by forming, reset and set operations. The simulated current exhibits the expected features: an abrupt jump at forming, a gradual reduction in reset, and a lower set voltage compared to forming. The evolution of potential, temperature and generated oxygen vacancies and ions during simulations can be monitored to gain insights on the mechanisms controlling device operations, including the structural changes such as the creation and disruption of the conductive filament, as well as the high temperature reached during forming. IV. REFERENCES [1] GINESTRATM , http://www.mdlsoft.com Fig 1: Schematic flow chart describing the main blocks of multiscale simulation platform. Figure 1

We investigated possible mechanisms for correlated defect production in amorphous (a) SiO 2 and HfO 2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films may lead to the localization of up to two electrons at intrinsic trapping sites which are present due to the natural structural disorder in amorphous structures. Trapping two electrons weakens Si-O and Hf-O bonds to such an extent that the thermally activated creation of Frenkel defects, O vacancies and O2- interstitial ions, becomes efficient even at room temperature. Bias application affects defect creation barriers and O2- interstitial diffusion. The density of trapping sites is different in a-SiO 2 and a-HfO 2 . This leads to qualitatively different degradation kinetics, which results from different correlation in defect creation in the two materials. These effects affect TDDB statistics and its dependence on the film thickness.

We use a multi-scale modeling framework to investigate time dependent dielectric breakdown (TDDB) distributions in SiO 2 - and HfO 2 -based stacks. We show that the low and thickness independent Weibull slope (β) observed in HfO 2 is due to the high intrinsic defect density and to the spatial correlation of the defect generation process. We investigate the origin of the double slope observed on TDDB distributions in IL-HfO 2 stacks: we have found that it is related to the stochastic nature of the bond-breakage process. This is important for a correct evaluation of the lifetime of logic devices.

In this paper, a multiscale modeling platform for neuromorphic computing devices connecting the atomic material properties to the electrical device performances is presented. The main ingredients of the modeling platform are discussed in view of the different technologies (e.g. RRAM, PCM, FTJ) proposed for 3D integrated neuromorphic computing.

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance.

We propose a model describing the operations of hafnium oxide-based resistive random access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport are self-consistently described starting from the leakage current in pristine HfO2. Material structural modifications occurring during the RRAM operations, such as conductive filament (CF) creation and disruption, are accounted for. The model describes the complex processes leading to a formation of the CF and its dependence on both electrical conditions (e.g., current compliance, voltage stress, and temperature) and device characteristics (e.g., electrodes material and dielectric thickness).

We present a multiscale modeling platform that exploits ab-initio calculation results and a material-related description of the most relevant defect-related phenomena in dieledtrics (charge trapping and transport, degradation and atomic species motion) to interpret and understand the electrical characteristics of OxRAM memory devices for non-volatile memories and neuromorphic applications. Simulation results provide a deep and quantitative understanding of the factors controlling device operation. The proposed multiscale modeling platform represents a powerful tool for investigating material properties and optimizing device performances and reliability.

In this paper we report about the scaling perspective of ultra-scaled HfO 2 Resistive Random Access Memory devices. Due to filamentary conduction, the scalability of these devices is considered to be ultimately limited by the size of the conductive filament. However, even though the precise size and shape of the filament is not fully elucidated, it is widely accepted that its size is mainly controlled by the current compliance. In turn, the latter sets the operating current level of the cell. The reduction of the current level is nevertheless accompanied by performance instabilities, which are the main reliability threat for low-current operations. The resulting tradeoff raises concerns about the scalability potential of RRAM devices. In this work, we combine device-level measurements, Conductive Atomic-Force Microscopy (C-AFM), and physics-based simulations of HfO 2 RRAM devices to elucidate the reason for these instabilities. Results clarify the scaling perspectives of ultra-low cell size (< 10×10 nm2) RRAMs and their reliability.

RRAM technology represents an attractive option for the embedded non-volatile memory systems. Optimizing the RRAM performance requires understanding the physical processes governing the electrical characteristics and identifying the major performance-driving forces from the standpoint of device structural properties and device operation conditions. We use a simulation model, which explicitly considers HfOx-specific nature of RRAM characteristics to understand at microscopic level the RRAM device operations [1-3]. This model is based on the description of the physical processes leading to the formation of the conductive filament and the subsequent resistive switching. The impact of the material properties are included at different levels (i.e. charge transport, ion diffusion, atomic bond breakage) by adopting a multi-scale approach. A full 3D description combined with a Monte-Carlo method is considered to account for the stochastic nature of microscopic RRAM mechanisms. The conductive filament formation is modeled as a metal-oxygen bond breakage and a subsequent out-diffusion of the released oxygen ions. The rates of the oxygen vacancy and ion generation are calculated using a thermochemical model [4]. The 3D temperature map is calculated from the power dissipation by solving the Fourier heat equation, while the power dissipated at isolated and extended defects is directly calculated from the charge transport model, Fig.1. The charge transport is described by a trap-assisted tunneling (TAT) model including carrier-phonon coupling and lattice relaxation [4], accounting for the role of grain boundaries as a preferential conductive spots [5]. The reduction of the relaxation energy with increasing the O vacancy density and the electron drift through the defect sub-band at very high O vacancy density are also included. The model successfully reproduces the current evolution during forming, Fig. 2, and the whole dynamics of the forming process including both charge transport (with the associated temperature increase) and ion diffusion, Fig. 1, as well as the characteristic dependencies on temperature and voltage ramp [1-3]. The concurrent description of charge transport and O ion diffusion allows understanding the effect of forming conditions on the stability of the conductive filament, which is found to be strongly controlled by ramp-rate of the forming pulse, which strongly affects the final ion position [1]. The simulations of the reset operation (bringing the device into high resistance state, HRS) shows that this process is controlled by re-oxidation of the filament tip caused by field-induced back-diffusion of oxygen ions. The charge transport in HRS is governed by TAT through O vacancies in the re-oxidized CF portion, Fig. 3. Simulations successfully reproduce the measured HRS current [2]. The activation and deactivation of O vacancies is found to be responsible of noise observed on HRS current, which is successfully simulated in both time and frequency domains, Fig. 3. Fig. 1. Current evolution during forming and the 3D maps of power dissipation, temperature and oxygen vacancy (blue) and ion (red) distributions, simulated on a TiN/TiOy/5nm-HfO2/TiN RRAM device biased at constant voltage of 1.7Va t the end of forming. Fig. 2. Current evolution measured and simulated during forming on a TiN/Ti/7nm-HfO2/TiN RRAM device. Fig. 3. a) Schematic illustration of the CF in HRS conditions. Simulations of RTN current fluctuations in time b) and frequency (power spectral density) domain. d) Measured and Experimental and simulated distribution of HRS current amplitude. References [1] L. Larcher, A. Padovani, O. Pirotta, L. Vandelli, G. Bersuker, Tech. Dig. IEDM, pp. 20.1.1-20.1.4, 2012. [2] G. Bersuker et al., J. Appl. Phys., Vol. 110, Issue 12, December, 2011. [3] L. Vandelli et al, Tech. Dig. IEDM, pp. 17.5.1-17.5.4, 2011. [4] L. Vandelli et al., Trans. Elect. Dev., Vol. 58, Issue 9, 2011. [5] O.Pirrotta et al., J. Appl. Phys. 114, 134503, 2013.

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.

We propose a physical model for the fast component ( \( s) of the positive bias temperature instability (PBTI) process in SiO x /HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the \(V_{\mathrm {{TH}}}\) shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).

In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.